Lines Matching +full:sdhci +full:- +full:caps +full:- +full:mask
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
166 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
188 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
233 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
242 /* 4C-4F reserved for more max current */
249 /* 55-57 reserved */
254 /* 60-FB reserved */
262 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
292 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
294 /* ADMA2 32-bit DMA descriptor size */
297 /* ADMA2 32-bit descriptor */
306 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
310 * alignment for the descriptor table even in 32-bit DMA mode. Memory
316 * ADMA2 64-bit DMA descriptor size
318 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
320 * register, 128-bit Descriptor will be selected.
322 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)
325 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
371 /* Controller has bad caps bits, but really supports DMA */
383 /* Controller can only DMA from 32-bit aligned addresses */
397 /* Controller does not provide transfer-complete interrupt when not busy */
401 /* Controller reports inverted write-protect state */
411 /* Controller cannot do multi-block transfers */
413 /* Controller can only handle 1-bit data transfers */
423 /* Controller is missing device caps. Use caps provided by host */
427 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
431 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
442 /* Controller has a non-standard host control register */
450 /* Controller does not support 64-bit DMA */
454 /* Capability register bit-63 indicates HS400 support */
472 * 32-bit block count may not support eMMC where upper bits of CMD23 are used
473 * for other purposes. Consequently we support 16-bit block count by default.
474 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
491 u64 dma_mask; /* custom DMA mask */
509 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
515 unsigned int version; /* SDHCI spec. version */
569 u32 caps; /* CAPABILITY_0 */ member
573 bool sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */
587 u32 cqe_ier; /* CQE interrupt mask */
588 u32 cqe_err_ier; /* CQE error interrupt mask */
593 unsigned int tuning_count; /* Timer count for re-tuning */
594 unsigned int tuning_mode; /* Re-tuning mode supported by host */
595 unsigned int tuning_err; /* Error code for re-tuning */
643 void (*reset)(struct sdhci_host *host, u8 mask);
664 if (unlikely(host->ops->write_l)) in sdhci_writel()
665 host->ops->write_l(host, val, reg); in sdhci_writel()
667 writel(val, host->ioaddr + reg); in sdhci_writel()
672 if (unlikely(host->ops->write_w)) in sdhci_writew()
673 host->ops->write_w(host, val, reg); in sdhci_writew()
675 writew(val, host->ioaddr + reg); in sdhci_writew()
680 if (unlikely(host->ops->write_b)) in sdhci_writeb()
681 host->ops->write_b(host, val, reg); in sdhci_writeb()
683 writeb(val, host->ioaddr + reg); in sdhci_writeb()
688 if (unlikely(host->ops->read_l)) in sdhci_readl()
689 return host->ops->read_l(host, reg); in sdhci_readl()
691 return readl(host->ioaddr + reg); in sdhci_readl()
696 if (unlikely(host->ops->read_w)) in sdhci_readw()
697 return host->ops->read_w(host, reg); in sdhci_readw()
699 return readw(host->ioaddr + reg); in sdhci_readw()
704 if (unlikely(host->ops->read_b)) in sdhci_readb()
705 return host->ops->read_b(host, reg); in sdhci_readb()
707 return readb(host->ioaddr + reg); in sdhci_readb()
714 writel(val, host->ioaddr + reg); in sdhci_writel()
719 writew(val, host->ioaddr + reg); in sdhci_writew()
724 writeb(val, host->ioaddr + reg); in sdhci_writeb()
729 return readl(host->ioaddr + reg); in sdhci_readl()
734 return readw(host->ioaddr + reg); in sdhci_readw()
739 return readb(host->ioaddr + reg); in sdhci_readb()
749 return host->private; in sdhci_priv()
754 const u32 *caps, const u32 *caps1);
780 void sdhci_reset(struct sdhci_host *host, u8 mask);