Lines Matching full:phydev
19 #define BRCM_PHY_MODEL(phydev) \ argument
20 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
22 #define BRCM_PHY_REV(phydev) \ argument
23 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
29 static int bcm54xx_config_clock_delay(struct phy_device *phydev) in bcm54xx_config_clock_delay() argument
34 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); in bcm54xx_config_clock_delay()
36 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || in bcm54xx_config_clock_delay()
37 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in bcm54xx_config_clock_delay()
41 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in bcm54xx_config_clock_delay()
42 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { in bcm54xx_config_clock_delay()
46 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, in bcm54xx_config_clock_delay()
52 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL); in bcm54xx_config_clock_delay()
53 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || in bcm54xx_config_clock_delay()
54 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { in bcm54xx_config_clock_delay()
58 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in bcm54xx_config_clock_delay()
59 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in bcm54xx_config_clock_delay()
63 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val); in bcm54xx_config_clock_delay()
70 static int bcm54210e_config_init(struct phy_device *phydev) in bcm54210e_config_init() argument
74 bcm54xx_config_clock_delay(phydev); in bcm54210e_config_init()
76 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) { in bcm54210e_config_init()
77 val = phy_read(phydev, MII_CTRL1000); in bcm54210e_config_init()
79 phy_write(phydev, MII_CTRL1000, val); in bcm54210e_config_init()
85 static int bcm54612e_config_init(struct phy_device *phydev) in bcm54612e_config_init() argument
89 bcm54xx_config_clock_delay(phydev); in bcm54612e_config_init()
92 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) { in bcm54612e_config_init()
95 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0); in bcm54612e_config_init()
96 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0, in bcm54612e_config_init()
106 static int bcm54616s_config_init(struct phy_device *phydev) in bcm54616s_config_init() argument
110 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && in bcm54616s_config_init()
111 phydev->interface != PHY_INTERFACE_MODE_1000BASEX) in bcm54616s_config_init()
116 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); in bcm54616s_config_init()
121 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, in bcm54616s_config_init()
127 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE); in bcm54616s_config_init()
131 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); in bcm54616s_config_init()
136 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN); in bcm54616s_config_init()
142 val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ? in bcm54616s_config_init()
145 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); in bcm54616s_config_init()
150 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); in bcm54616s_config_init()
156 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val); in bcm54616s_config_init()
161 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); in bcm54616s_config_init()
165 static int bcm50610_a0_workaround(struct phy_device *phydev) in bcm50610_a0_workaround() argument
169 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0, in bcm50610_a0_workaround()
175 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3, in bcm50610_a0_workaround()
180 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, in bcm50610_a0_workaround()
185 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96, in bcm50610_a0_workaround()
190 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97, in bcm50610_a0_workaround()
196 static int bcm54xx_phydsp_config(struct phy_device *phydev) in bcm54xx_phydsp_config() argument
201 err = bcm54xx_auxctl_write(phydev, in bcm54xx_phydsp_config()
208 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 || in bcm54xx_phydsp_config()
209 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) { in bcm54xx_phydsp_config()
211 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, in bcm54xx_phydsp_config()
216 if (phydev->drv->phy_id == PHY_ID_BCM50610) { in bcm54xx_phydsp_config()
217 err = bcm50610_a0_workaround(phydev); in bcm54xx_phydsp_config()
223 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) { in bcm54xx_phydsp_config()
226 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75); in bcm54xx_phydsp_config()
231 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val); in bcm54xx_phydsp_config()
236 err2 = bcm54xx_auxctl_write(phydev, in bcm54xx_phydsp_config()
244 static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev) in bcm54xx_adjust_rxrefclk() argument
251 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 && in bcm54xx_adjust_rxrefclk()
252 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 && in bcm54xx_adjust_rxrefclk()
253 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M && in bcm54xx_adjust_rxrefclk()
254 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 && in bcm54xx_adjust_rxrefclk()
255 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) in bcm54xx_adjust_rxrefclk()
258 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3); in bcm54xx_adjust_rxrefclk()
264 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 || in bcm54xx_adjust_rxrefclk()
265 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) && in bcm54xx_adjust_rxrefclk()
266 BRCM_PHY_REV(phydev) >= 0x3) { in bcm54xx_adjust_rxrefclk()
273 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) { in bcm54xx_adjust_rxrefclk()
274 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) { in bcm54xx_adjust_rxrefclk()
282 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) in bcm54xx_adjust_rxrefclk()
287 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) { in bcm54xx_adjust_rxrefclk()
288 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 || in bcm54xx_adjust_rxrefclk()
289 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811) in bcm54xx_adjust_rxrefclk()
296 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val); in bcm54xx_adjust_rxrefclk()
298 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD); in bcm54xx_adjust_rxrefclk()
304 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE)) in bcm54xx_adjust_rxrefclk()
310 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val); in bcm54xx_adjust_rxrefclk()
313 static int bcm54xx_config_init(struct phy_device *phydev) in bcm54xx_config_init() argument
317 reg = phy_read(phydev, MII_BCM54XX_ECR); in bcm54xx_config_init()
323 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm54xx_config_init()
331 err = phy_write(phydev, MII_BCM54XX_IMR, reg); in bcm54xx_config_init()
335 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 || in bcm54xx_config_init()
336 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) && in bcm54xx_config_init()
337 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE)) in bcm54xx_config_init()
338 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0); in bcm54xx_config_init()
340 bcm54xx_adjust_rxrefclk(phydev); in bcm54xx_config_init()
342 switch (BRCM_PHY_MODEL(phydev)) { in bcm54xx_config_init()
345 err = bcm54xx_config_clock_delay(phydev); in bcm54xx_config_init()
348 err = bcm54210e_config_init(phydev); in bcm54xx_config_init()
351 err = bcm54612e_config_init(phydev); in bcm54xx_config_init()
354 err = bcm54616s_config_init(phydev); in bcm54xx_config_init()
358 val = bcm_phy_read_exp(phydev, in bcm54xx_config_init()
361 err = bcm_phy_write_exp(phydev, in bcm54xx_config_init()
369 bcm54xx_phydsp_config(phydev); in bcm54xx_config_init()
377 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, val); in bcm54xx_config_init()
382 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val); in bcm54xx_config_init()
387 static int bcm54xx_resume(struct phy_device *phydev) in bcm54xx_resume() argument
394 ret = genphy_resume(phydev); in bcm54xx_resume()
403 return bcm54xx_config_init(phydev); in bcm54xx_resume()
406 static int bcm54811_config_init(struct phy_device *phydev) in bcm54811_config_init() argument
411 reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL); in bcm54811_config_init()
413 err = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL, in bcm54811_config_init()
418 err = bcm54xx_config_init(phydev); in bcm54811_config_init()
421 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) { in bcm54811_config_init()
422 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0); in bcm54811_config_init()
423 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0, in bcm54811_config_init()
432 static int bcm5482_config_init(struct phy_device *phydev) in bcm5482_config_init() argument
436 err = bcm54xx_config_init(phydev); in bcm5482_config_init()
438 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) { in bcm5482_config_init()
442 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD); in bcm5482_config_init()
443 bcm_phy_write_shadow(phydev, BCM5482_SHD_SSD, in bcm5482_config_init()
452 err = bcm_phy_read_exp(phydev, reg); in bcm5482_config_init()
455 err = bcm_phy_write_exp(phydev, reg, err | in bcm5482_config_init()
465 err = bcm_phy_read_exp(phydev, reg); in bcm5482_config_init()
468 err = bcm_phy_write_exp(phydev, reg, in bcm5482_config_init()
476 reg = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE); in bcm5482_config_init()
477 bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, in bcm5482_config_init()
484 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, in bcm5482_config_init()
494 phydev->autoneg = AUTONEG_DISABLE; in bcm5482_config_init()
495 phydev->speed = SPEED_1000; in bcm5482_config_init()
496 phydev->duplex = DUPLEX_FULL; in bcm5482_config_init()
502 static int bcm5482_read_status(struct phy_device *phydev) in bcm5482_read_status() argument
506 err = genphy_read_status(phydev); in bcm5482_read_status()
508 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) { in bcm5482_read_status()
513 if (phydev->link) { in bcm5482_read_status()
514 phydev->speed = SPEED_1000; in bcm5482_read_status()
515 phydev->duplex = DUPLEX_FULL; in bcm5482_read_status()
522 static int bcm5481_config_aneg(struct phy_device *phydev) in bcm5481_config_aneg() argument
524 struct device_node *np = phydev->mdio.dev.of_node; in bcm5481_config_aneg()
528 ret = genphy_config_aneg(phydev); in bcm5481_config_aneg()
531 bcm54xx_config_clock_delay(phydev); in bcm5481_config_aneg()
535 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9, in bcm5481_config_aneg()
544 static int bcm54616s_probe(struct phy_device *phydev) in bcm54616s_probe() argument
548 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE); in bcm54616s_probe()
559 val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL); in bcm54616s_probe()
569 phydev->dev_flags |= PHY_BCM_FLAGS_MODE_1000BX; in bcm54616s_probe()
571 phydev->port = PORT_FIBRE; in bcm54616s_probe()
577 static int bcm54616s_config_aneg(struct phy_device *phydev) in bcm54616s_config_aneg() argument
582 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) in bcm54616s_config_aneg()
583 ret = genphy_c37_config_aneg(phydev); in bcm54616s_config_aneg()
585 ret = genphy_config_aneg(phydev); in bcm54616s_config_aneg()
588 bcm54xx_config_clock_delay(phydev); in bcm54616s_config_aneg()
593 static int bcm54616s_read_status(struct phy_device *phydev) in bcm54616s_read_status() argument
597 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) in bcm54616s_read_status()
598 err = genphy_c37_read_status(phydev); in bcm54616s_read_status()
600 err = genphy_read_status(phydev); in bcm54616s_read_status()
605 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set) in brcm_phy_setbits() argument
609 val = phy_read(phydev, reg); in brcm_phy_setbits()
613 return phy_write(phydev, reg, val | set); in brcm_phy_setbits()
616 static int brcm_fet_config_init(struct phy_device *phydev) in brcm_fet_config_init() argument
621 err = phy_write(phydev, MII_BMCR, BMCR_RESET); in brcm_fet_config_init()
625 reg = phy_read(phydev, MII_BRCM_FET_INTREG); in brcm_fet_config_init()
636 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_init()
641 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); in brcm_fet_config_init()
647 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); in brcm_fet_config_init()
652 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4); in brcm_fet_config_init()
661 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); in brcm_fet_config_init()
666 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL, in brcm_fet_config_init()
671 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) { in brcm_fet_config_init()
673 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2, in brcm_fet_config_init()
679 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); in brcm_fet_config_init()
686 static int brcm_fet_ack_interrupt(struct phy_device *phydev) in brcm_fet_ack_interrupt() argument
691 reg = phy_read(phydev, MII_BRCM_FET_INTREG); in brcm_fet_ack_interrupt()
698 static int brcm_fet_config_intr(struct phy_device *phydev) in brcm_fet_config_intr() argument
702 reg = phy_read(phydev, MII_BRCM_FET_INTREG); in brcm_fet_config_intr()
706 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in brcm_fet_config_intr()
711 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_intr()
719 static int bcm53xx_phy_probe(struct phy_device *phydev) in bcm53xx_phy_probe() argument
723 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); in bcm53xx_phy_probe()
727 phydev->priv = priv; in bcm53xx_phy_probe()
729 priv->stats = devm_kcalloc(&phydev->mdio.dev, in bcm53xx_phy_probe()
730 bcm_phy_get_sset_count(phydev), sizeof(u64), in bcm53xx_phy_probe()
738 static void bcm53xx_phy_get_stats(struct phy_device *phydev, in bcm53xx_phy_get_stats() argument
741 struct bcm53xx_phy_priv *priv = phydev->priv; in bcm53xx_phy_get_stats()
743 bcm_phy_get_stats(phydev, priv->stats, stats, data); in bcm53xx_phy_get_stats()