Lines Matching full:phydev
110 static int vsc85xx_phy_read_page(struct phy_device *phydev) in vsc85xx_phy_read_page() argument
112 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS); in vsc85xx_phy_read_page()
115 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page) in vsc85xx_phy_write_page() argument
117 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page); in vsc85xx_phy_write_page()
120 static int vsc85xx_get_sset_count(struct phy_device *phydev) in vsc85xx_get_sset_count() argument
122 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_sset_count()
130 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data) in vsc85xx_get_strings() argument
132 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_strings()
143 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i) in vsc85xx_get_stat() argument
145 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_stat()
148 val = phy_read_paged(phydev, priv->hw_stats[i].page, in vsc85xx_get_stat()
159 static void vsc85xx_get_stats(struct phy_device *phydev, in vsc85xx_get_stats() argument
162 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_stats()
169 data[i] = vsc85xx_get_stat(phydev, i); in vsc85xx_get_stats()
172 static int vsc85xx_led_cntl_set(struct phy_device *phydev, in vsc85xx_led_cntl_set() argument
179 mutex_lock(&phydev->lock); in vsc85xx_led_cntl_set()
180 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL); in vsc85xx_led_cntl_set()
183 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val); in vsc85xx_led_cntl_set()
184 mutex_unlock(&phydev->lock); in vsc85xx_led_cntl_set()
189 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix) in vsc85xx_mdix_get() argument
193 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL); in vsc85xx_mdix_get()
202 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix) in vsc85xx_mdix_set() argument
207 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL); in vsc85xx_mdix_set()
217 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val); in vsc85xx_mdix_set()
228 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_mdix_set()
234 return genphy_restart_aneg(phydev); in vsc85xx_mdix_set()
237 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count) in vsc85xx_downshift_get() argument
241 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_downshift_get()
255 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count) in vsc85xx_downshift_set() argument
261 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n"); in vsc85xx_downshift_set()
268 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_downshift_set()
273 static int vsc85xx_wol_set(struct phy_device *phydev, in vsc85xx_wol_set() argument
281 u8 *mac_addr = phydev->attached_dev->dev_addr; in vsc85xx_wol_set()
283 mutex_lock(&phydev->lock); in vsc85xx_wol_set()
284 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_wol_set()
286 rc = phy_restore_page(phydev, rc, rc); in vsc85xx_wol_set()
295 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]); in vsc85xx_wol_set()
296 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]); in vsc85xx_wol_set()
297 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]); in vsc85xx_wol_set()
299 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0); in vsc85xx_wol_set()
300 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0); in vsc85xx_wol_set()
301 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0); in vsc85xx_wol_set()
308 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]); in vsc85xx_wol_set()
309 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]); in vsc85xx_wol_set()
310 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]); in vsc85xx_wol_set()
312 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0); in vsc85xx_wol_set()
313 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0); in vsc85xx_wol_set()
314 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0); in vsc85xx_wol_set()
317 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); in vsc85xx_wol_set()
322 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val); in vsc85xx_wol_set()
324 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_set()
330 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); in vsc85xx_wol_set()
332 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); in vsc85xx_wol_set()
337 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); in vsc85xx_wol_set()
339 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); in vsc85xx_wol_set()
344 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_wol_set()
347 mutex_unlock(&phydev->lock); in vsc85xx_wol_set()
352 static void vsc85xx_wol_get(struct phy_device *phydev, in vsc85xx_wol_get() argument
361 mutex_lock(&phydev->lock); in vsc85xx_wol_get()
362 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_wol_get()
366 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); in vsc85xx_wol_get()
370 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD); in vsc85xx_wol_get()
371 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD); in vsc85xx_wol_get()
372 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD); in vsc85xx_wol_get()
381 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_get()
382 mutex_unlock(&phydev->lock); in vsc85xx_wol_get()
386 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) in vsc85xx_edge_rate_magic_get() argument
390 struct device *dev = &phydev->mdio.dev; in vsc85xx_edge_rate_magic_get()
412 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, in vsc85xx_dt_led_mode_get() argument
416 struct vsc8531_private *priv = phydev->priv; in vsc85xx_dt_led_mode_get()
417 struct device *dev = &phydev->mdio.dev; in vsc85xx_dt_led_mode_get()
428 phydev_err(phydev, "DT %s invalid\n", led); in vsc85xx_dt_led_mode_get()
436 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) in vsc85xx_edge_rate_magic_get() argument
441 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, in vsc85xx_dt_led_mode_get() argument
449 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev, in vsc85xx_dt_led_modes_get() argument
452 struct vsc8531_private *priv = phydev->priv; in vsc85xx_dt_led_modes_get()
461 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop, in vsc85xx_dt_led_modes_get()
471 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate) in vsc85xx_edge_rate_cntl_set() argument
475 mutex_lock(&phydev->lock); in vsc85xx_edge_rate_cntl_set()
476 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, in vsc85xx_edge_rate_cntl_set()
479 mutex_unlock(&phydev->lock); in vsc85xx_edge_rate_cntl_set()
484 static int vsc85xx_mac_if_set(struct phy_device *phydev, in vsc85xx_mac_if_set() argument
490 mutex_lock(&phydev->lock); in vsc85xx_mac_if_set()
491 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); in vsc85xx_mac_if_set()
511 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val); in vsc85xx_mac_if_set()
515 rc = genphy_soft_reset(phydev); in vsc85xx_mac_if_set()
518 mutex_unlock(&phydev->lock); in vsc85xx_mac_if_set()
530 static int vsc85xx_rgmii_set_skews(struct phy_device *phydev, u32 rgmii_cntl, in vsc85xx_rgmii_set_skews() argument
539 mutex_lock(&phydev->lock); in vsc85xx_rgmii_set_skews()
541 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || in vsc85xx_rgmii_set_skews()
542 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in vsc85xx_rgmii_set_skews()
544 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || in vsc85xx_rgmii_set_skews()
545 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in vsc85xx_rgmii_set_skews()
548 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, in vsc85xx_rgmii_set_skews()
553 mutex_unlock(&phydev->lock); in vsc85xx_rgmii_set_skews()
558 static int vsc85xx_default_config(struct phy_device *phydev) in vsc85xx_default_config() argument
562 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc85xx_default_config()
564 if (phy_interface_mode_is_rgmii(phydev->interface)) { in vsc85xx_default_config()
565 rc = vsc85xx_rgmii_set_skews(phydev, VSC8502_RGMII_CNTL, in vsc85xx_default_config()
575 static int vsc85xx_get_tunable(struct phy_device *phydev, in vsc85xx_get_tunable() argument
580 return vsc85xx_downshift_get(phydev, (u8 *)data); in vsc85xx_get_tunable()
586 static int vsc85xx_set_tunable(struct phy_device *phydev, in vsc85xx_set_tunable() argument
592 return vsc85xx_downshift_set(phydev, *(u8 *)data); in vsc85xx_set_tunable()
599 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val) in vsc85xx_tr_write() argument
601 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16); in vsc85xx_tr_write()
602 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc85xx_tr_write()
603 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); in vsc85xx_tr_write()
606 static int vsc8531_pre_init_seq_set(struct phy_device *phydev) in vsc8531_pre_init_seq_set() argument
618 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD, in vsc8531_pre_init_seq_set()
623 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
627 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
631 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
636 mutex_lock(&phydev->lock); in vsc8531_pre_init_seq_set()
637 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); in vsc8531_pre_init_seq_set()
642 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val); in vsc8531_pre_init_seq_set()
645 oldpage = phy_restore_page(phydev, oldpage, oldpage); in vsc8531_pre_init_seq_set()
646 mutex_unlock(&phydev->lock); in vsc8531_pre_init_seq_set()
651 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev) in vsc85xx_eee_init_seq_set() argument
676 mutex_lock(&phydev->lock); in vsc85xx_eee_init_seq_set()
677 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); in vsc85xx_eee_init_seq_set()
682 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val); in vsc85xx_eee_init_seq_set()
685 oldpage = phy_restore_page(phydev, oldpage, oldpage); in vsc85xx_eee_init_seq_set()
686 mutex_unlock(&phydev->lock); in vsc85xx_eee_init_seq_set()
691 /* phydev->bus->mdio_lock should be locked when using this function */
692 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val) in phy_base_write() argument
694 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { in phy_base_write()
695 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); in phy_base_write()
699 return __phy_package_write(phydev, regnum, val); in phy_base_write()
702 /* phydev->bus->mdio_lock should be locked when using this function */
703 static int phy_base_read(struct phy_device *phydev, u32 regnum) in phy_base_read() argument
705 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { in phy_base_read()
706 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); in phy_base_read()
710 return __phy_package_read(phydev, regnum); in phy_base_read()
713 static u32 vsc85xx_csr_read(struct phy_device *phydev, in vsc85xx_csr_read() argument
719 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); in vsc85xx_csr_read()
729 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, in vsc85xx_csr_read()
739 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, in vsc85xx_csr_read()
748 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); in vsc85xx_csr_read()
756 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17); in vsc85xx_csr_read()
759 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18); in vsc85xx_csr_read()
761 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc85xx_csr_read()
767 static int vsc85xx_csr_write(struct phy_device *phydev, in vsc85xx_csr_write() argument
772 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); in vsc85xx_csr_write()
782 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, in vsc85xx_csr_write()
786 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val); in vsc85xx_csr_write()
789 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16)); in vsc85xx_csr_write()
798 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, in vsc85xx_csr_write()
807 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); in vsc85xx_csr_write()
814 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc85xx_csr_write()
821 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val) in vsc8584_csr_write() argument
823 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16); in vsc8584_csr_write()
824 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc8584_csr_write()
825 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); in vsc8584_csr_write()
829 static int vsc8584_cmd(struct phy_device *phydev, u16 val) in vsc8584_cmd() argument
834 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_cmd()
837 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val); in vsc8584_cmd()
841 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD); in vsc8584_cmd()
846 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_cmd()
858 static int vsc8584_micro_deassert_reset(struct phy_device *phydev, in vsc8584_micro_deassert_reset() argument
863 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_deassert_reset()
875 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); in vsc8584_micro_deassert_reset()
881 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
883 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
885 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_micro_deassert_reset()
891 static int vsc8584_micro_assert_reset(struct phy_device *phydev) in vsc8584_micro_assert_reset() argument
896 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); in vsc8584_micro_assert_reset()
900 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_assert_reset()
903 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
905 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
907 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
908 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
910 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
912 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
914 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP); in vsc8584_micro_assert_reset()
916 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
918 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
920 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF | in vsc8584_micro_assert_reset()
924 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
926 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
928 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_micro_assert_reset()
934 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size, in vsc8584_get_fw_crc() argument
939 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_fw_crc()
941 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start); in vsc8584_get_fw_crc()
942 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size); in vsc8584_get_fw_crc()
945 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16); in vsc8584_get_fw_crc()
949 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_fw_crc()
951 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2); in vsc8584_get_fw_crc()
954 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_get_fw_crc()
960 static int vsc8584_patch_fw(struct phy_device *phydev, in vsc8584_patch_fw() argument
965 ret = vsc8584_micro_assert_reset(phydev); in vsc8584_patch_fw()
967 dev_err(&phydev->mdio.dev, in vsc8584_patch_fw()
972 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_patch_fw()
978 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM | in vsc8584_patch_fw()
981 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN | in vsc8584_patch_fw()
983 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000); in vsc8584_patch_fw()
986 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | in vsc8584_patch_fw()
990 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); in vsc8584_patch_fw()
992 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_patch_fw()
998 static bool vsc8574_is_serdes_init(struct phy_device *phydev) in vsc8574_is_serdes_init() argument
1003 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_is_serdes_init()
1006 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1)); in vsc8574_is_serdes_init()
1012 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1)); in vsc8574_is_serdes_init()
1018 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8574_is_serdes_init()
1024 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
1033 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_is_serdes_init()
1039 static int vsc8574_config_pre_init(struct phy_device *phydev) in vsc8574_config_pre_init() argument
1105 struct device *dev = &phydev->mdio.dev; in vsc8574_config_pre_init()
1112 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1115 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8574_config_pre_init()
1117 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8574_config_pre_init()
1119 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8574_config_pre_init()
1126 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040); in vsc8574_config_pre_init()
1128 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8574_config_pre_init()
1130 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320); in vsc8574_config_pre_init()
1131 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00); in vsc8574_config_pre_init()
1132 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca); in vsc8574_config_pre_init()
1133 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20); in vsc8574_config_pre_init()
1135 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8574_config_pre_init()
1137 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8574_config_pre_init()
1139 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8574_config_pre_init()
1142 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8574_config_pre_init()
1144 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); in vsc8574_config_pre_init()
1146 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8574_config_pre_init()
1148 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8574_config_pre_init()
1151 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); in vsc8574_config_pre_init()
1153 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8574_config_pre_init()
1155 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8574_config_pre_init()
1157 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8574_config_pre_init()
1159 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1162 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8574_config_pre_init()
1164 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8574_config_pre_init()
1174 ret = vsc8584_get_fw_crc(phydev, in vsc8574_config_pre_init()
1181 serdes_init = vsc8574_is_serdes_init(phydev); in vsc8574_config_pre_init()
1184 ret = vsc8584_micro_assert_reset(phydev); in vsc8574_config_pre_init()
1197 if (vsc8584_patch_fw(phydev, fw)) in vsc8574_config_pre_init()
1203 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
1206 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7); in vsc8574_config_pre_init()
1207 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012); in vsc8574_config_pre_init()
1208 phy_base_write(phydev, MSCC_INT_MEM_CNTL, in vsc8574_config_pre_init()
1211 vsc8584_micro_deassert_reset(phydev, false); in vsc8574_config_pre_init()
1216 ret = vsc8584_get_fw_crc(phydev, in vsc8574_config_pre_init()
1227 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
1230 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT | in vsc8574_config_pre_init()
1234 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1242 static void vsc8584_pll5g_cfg2_wr(struct phy_device *phydev, in vsc8584_pll5g_cfg2_wr() argument
1247 rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2); in vsc8584_pll5g_cfg2_wr()
1250 vsc85xx_csr_write(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2, rd_dat); in vsc8584_pll5g_cfg2_wr()
1254 static int vsc8584_mcb_rd_trig(struct phy_device *phydev, in vsc8584_mcb_rd_trig() argument
1260 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, in vsc8584_mcb_rd_trig()
1266 phydev, MACRO_CTRL, mcb_reg_addr); in vsc8584_mcb_rd_trig()
1270 static int vsc8584_mcb_wr_trig(struct phy_device *phydev, in vsc8584_mcb_wr_trig() argument
1277 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr, in vsc8584_mcb_wr_trig()
1283 phydev, MACRO_CTRL, mcb_reg_addr); in vsc8584_mcb_wr_trig()
1287 static int vsc8584_pll5g_reset(struct phy_device *phydev) in vsc8584_pll5g_reset() argument
1292 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1298 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm); in vsc8584_pll5g_reset()
1301 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1309 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1315 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm); in vsc8584_pll5g_reset()
1318 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1328 static int vsc8584_config_pre_init(struct phy_device *phydev) in vsc8584_config_pre_init() argument
1360 struct device *dev = &phydev->mdio.dev; in vsc8584_config_pre_init()
1365 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1368 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8584_config_pre_init()
1370 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8584_config_pre_init()
1372 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8584_config_pre_init()
1374 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL); in vsc8584_config_pre_init()
1376 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg); in vsc8584_config_pre_init()
1383 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3); in vsc8584_config_pre_init()
1385 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000); in vsc8584_config_pre_init()
1387 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8584_config_pre_init()
1389 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20); in vsc8584_config_pre_init()
1391 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8584_config_pre_init()
1393 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8584_config_pre_init()
1395 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8584_config_pre_init()
1397 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4)); in vsc8584_config_pre_init()
1399 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB); in vsc8584_config_pre_init()
1402 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg); in vsc8584_config_pre_init()
1404 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4)); in vsc8584_config_pre_init()
1407 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8584_config_pre_init()
1409 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); in vsc8584_config_pre_init()
1411 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8584_config_pre_init()
1413 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8584_config_pre_init()
1416 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); in vsc8584_config_pre_init()
1418 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8584_config_pre_init()
1420 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8584_config_pre_init()
1422 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8584_config_pre_init()
1424 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1427 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8584_config_pre_init()
1429 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8584_config_pre_init()
1439 ret = vsc8584_get_fw_crc(phydev, in vsc8584_config_pre_init()
1447 if (vsc8584_patch_fw(phydev, fw)) in vsc8584_config_pre_init()
1452 vsc8584_micro_deassert_reset(phydev, false); in vsc8584_config_pre_init()
1455 ret = vsc8584_get_fw_crc(phydev, in vsc8584_config_pre_init()
1465 ret = vsc8584_micro_assert_reset(phydev); in vsc8584_config_pre_init()
1469 vsc8584_micro_deassert_reset(phydev, true); in vsc8584_config_pre_init()
1472 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1479 static void vsc8584_get_base_addr(struct phy_device *phydev) in vsc8584_get_base_addr() argument
1481 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_get_base_addr()
1484 phy_lock_mdio_bus(phydev); in vsc8584_get_base_addr()
1485 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_base_addr()
1487 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4); in vsc8584_get_base_addr()
1490 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL); in vsc8584_get_base_addr()
1492 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_get_base_addr()
1493 phy_unlock_mdio_bus(phydev); in vsc8584_get_base_addr()
1499 vsc8531->ts_base_addr = phydev->mdio.addr; in vsc8584_get_base_addr()
1503 vsc8531->base_addr = phydev->mdio.addr + addr; in vsc8584_get_base_addr()
1509 vsc8531->base_addr = phydev->mdio.addr - addr; in vsc8584_get_base_addr()
1519 static int vsc8584_config_init(struct phy_device *phydev) in vsc8584_config_init() argument
1521 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_config_init()
1525 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc8584_config_init()
1527 phy_lock_mdio_bus(phydev); in vsc8584_config_init()
1542 if (phy_package_init_once(phydev)) { in vsc8584_config_init()
1547 WARN_ON(phydev->drv->phy_id_mask & 0xf); in vsc8584_config_init()
1549 switch (phydev->phy_id & phydev->drv->phy_id_mask) { in vsc8584_config_init()
1554 ret = vsc8574_config_pre_init(phydev); in vsc8584_config_init()
1560 ret = vsc8584_config_pre_init(phydev); in vsc8584_config_init()
1571 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_init()
1576 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); in vsc8584_config_init()
1578 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { in vsc8584_config_init()
1580 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in vsc8584_config_init()
1582 } else if (phy_interface_is_rgmii(phydev)) { in vsc8584_config_init()
1589 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); in vsc8584_config_init()
1593 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_init()
1598 if (!phy_interface_is_rgmii(phydev)) { in vsc8584_config_init()
1601 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) in vsc8584_config_init()
1606 ret = vsc8584_cmd(phydev, val); in vsc8584_config_init()
1614 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8584_config_init()
1623 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8584_config_init()
1631 phy_unlock_mdio_bus(phydev); in vsc8584_config_init()
1633 ret = vsc8584_macsec_init(phydev); in vsc8584_config_init()
1637 ret = vsc8584_ptp_init(phydev); in vsc8584_config_init()
1641 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); in vsc8584_config_init()
1645 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val); in vsc8584_config_init()
1649 if (phy_interface_is_rgmii(phydev)) { in vsc8584_config_init()
1650 ret = vsc85xx_rgmii_set_skews(phydev, VSC8572_RGMII_CNTL, in vsc8584_config_init()
1657 ret = genphy_soft_reset(phydev); in vsc8584_config_init()
1662 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc8584_config_init()
1670 phy_unlock_mdio_bus(phydev); in vsc8584_config_init()
1674 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev) in vsc8584_handle_interrupt() argument
1679 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc8584_handle_interrupt()
1686 ret = vsc8584_handle_ts_interrupt(phydev); in vsc8584_handle_interrupt()
1691 vsc8584_handle_macsec_interrupt(phydev); in vsc8584_handle_interrupt()
1694 phy_mac_interrupt(phydev); in vsc8584_handle_interrupt()
1699 static int vsc85xx_config_init(struct phy_device *phydev) in vsc85xx_config_init() argument
1702 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_config_init()
1704 rc = vsc85xx_default_config(phydev); in vsc85xx_config_init()
1708 rc = vsc85xx_mac_if_set(phydev, phydev->interface); in vsc85xx_config_init()
1712 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic); in vsc85xx_config_init()
1716 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask; in vsc85xx_config_init()
1719 rc = vsc8531_pre_init_seq_set(phydev); in vsc85xx_config_init()
1724 rc = vsc85xx_eee_init_seq_set(phydev); in vsc85xx_config_init()
1729 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc85xx_config_init()
1737 static int vsc8584_did_interrupt(struct phy_device *phydev) in vsc8584_did_interrupt() argument
1741 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in vsc8584_did_interrupt()
1742 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc8584_did_interrupt()
1747 static int vsc8514_config_pre_init(struct phy_device *phydev) in vsc8514_config_pre_init() argument
1775 struct device *dev = &phydev->mdio.dev; in vsc8514_config_pre_init()
1780 ret = vsc8584_pll5g_reset(phydev); in vsc8514_config_pre_init()
1786 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8514_config_pre_init()
1789 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8514_config_pre_init()
1791 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8514_config_pre_init()
1793 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8514_config_pre_init()
1795 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8514_config_pre_init()
1797 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8514_config_pre_init()
1799 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8514_config_pre_init()
1802 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8514_config_pre_init()
1804 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8514_config_pre_init()
1806 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8514_config_pre_init()
1808 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8514_config_pre_init()
1810 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8514_config_pre_init()
1812 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8514_config_pre_init()
1814 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8514_config_pre_init()
1819 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb, in __phy_write_mcb_s6g() argument
1826 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg, in __phy_write_mcb_s6g()
1834 val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg); in __phy_write_mcb_s6g()
1848 static int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) in phy_update_mcb_s6g() argument
1850 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ); in phy_update_mcb_s6g()
1854 static int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) in phy_commit_mcb_s6g() argument
1856 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE); in phy_commit_mcb_s6g()
1859 static int vsc8514_config_init(struct phy_device *phydev) in vsc8514_config_init() argument
1861 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8514_config_init()
1867 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc8514_config_init()
1869 phy_lock_mdio_bus(phydev); in vsc8514_config_init()
1882 if (phy_package_init_once(phydev)) in vsc8514_config_init()
1883 vsc8514_config_pre_init(phydev); in vsc8514_config_init()
1885 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8514_config_init()
1890 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); in vsc8514_config_init()
1894 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); in vsc8514_config_init()
1898 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8514_config_init()
1903 ret = vsc8584_cmd(phydev, in vsc8514_config_init()
1911 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc8514_config_init()
1913 phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); in vsc8514_config_init()
1915 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1920 phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); in vsc8514_config_init()
1922 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1931 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1942 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1948 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1953 phy_commit_mcb_s6g(phydev, PHY_S6G_DFT_CFG2, 0); in vsc8514_config_init()
1958 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, in vsc8514_config_init()
1960 reg = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1963 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
1970 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
1975 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1980 phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc8514_config_init()
1985 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, in vsc8514_config_init()
1987 reg = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
1990 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
1997 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
2001 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
2003 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK, in vsc8514_config_init()
2009 ret = genphy_soft_reset(phydev); in vsc8514_config_init()
2015 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc8514_config_init()
2023 phy_unlock_mdio_bus(phydev); in vsc8514_config_init()
2027 static int vsc85xx_ack_interrupt(struct phy_device *phydev) in vsc85xx_ack_interrupt() argument
2031 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in vsc85xx_ack_interrupt()
2032 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_ack_interrupt()
2037 static int vsc85xx_config_intr(struct phy_device *phydev) in vsc85xx_config_intr() argument
2041 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in vsc85xx_config_intr()
2042 vsc8584_config_macsec_intr(phydev); in vsc85xx_config_intr()
2043 vsc8584_config_ts_intr(phydev); in vsc85xx_config_intr()
2045 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, in vsc85xx_config_intr()
2048 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc85xx_config_intr()
2051 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_config_intr()
2057 static int vsc85xx_config_aneg(struct phy_device *phydev) in vsc85xx_config_aneg() argument
2061 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl); in vsc85xx_config_aneg()
2065 return genphy_config_aneg(phydev); in vsc85xx_config_aneg()
2068 static int vsc85xx_read_status(struct phy_device *phydev) in vsc85xx_read_status() argument
2072 rc = vsc85xx_mdix_get(phydev, &phydev->mdix); in vsc85xx_read_status()
2076 return genphy_read_status(phydev); in vsc85xx_read_status()
2079 static int vsc8514_probe(struct phy_device *phydev) in vsc8514_probe() argument
2086 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8514_probe()
2090 phydev->priv = vsc8531; in vsc8514_probe()
2092 vsc8584_get_base_addr(phydev); in vsc8514_probe()
2093 devm_phy_package_join(&phydev->mdio.dev, phydev, in vsc8514_probe()
2100 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8514_probe()
2105 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8514_probe()
2108 static int vsc8574_probe(struct phy_device *phydev) in vsc8574_probe() argument
2115 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8574_probe()
2119 phydev->priv = vsc8531; in vsc8574_probe()
2121 vsc8584_get_base_addr(phydev); in vsc8574_probe()
2122 devm_phy_package_join(&phydev->mdio.dev, phydev, in vsc8574_probe()
2129 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8574_probe()
2134 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8574_probe()
2137 static int vsc8584_probe(struct phy_device *phydev) in vsc8584_probe() argument
2145 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) { in vsc8584_probe()
2146 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n"); in vsc8584_probe()
2150 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8584_probe()
2154 phydev->priv = vsc8531; in vsc8584_probe()
2156 vsc8584_get_base_addr(phydev); in vsc8584_probe()
2157 devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr, in vsc8584_probe()
2164 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8584_probe()
2169 if (phy_package_probe_once(phydev)) { in vsc8584_probe()
2170 ret = vsc8584_ptp_probe_once(phydev); in vsc8584_probe()
2175 ret = vsc8584_ptp_probe(phydev); in vsc8584_probe()
2179 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8584_probe()
2182 static int vsc85xx_probe(struct phy_device *phydev) in vsc85xx_probe() argument
2189 rate_magic = vsc85xx_edge_rate_magic_get(phydev); in vsc85xx_probe()
2193 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc85xx_probe()
2197 phydev->priv = vsc8531; in vsc85xx_probe()
2204 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc85xx_probe()
2209 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc85xx_probe()