Lines Matching full:pcie
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
30 /* PCIe core registers */
120 /* PCIe window configuration */
211 /* PCIe core controller registers */
219 /* PCIe Central Interrupts Registers */
298 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
300 writel(val, pcie->base + reg); in advk_writel()
303 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
305 return readl(pcie->base + reg); in advk_readl()
308 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) in advk_pcie_ltssm_state() argument
313 val = advk_readl(pcie, CFG_REG); in advk_pcie_ltssm_state()
318 static inline bool advk_pcie_link_up(struct advk_pcie *pcie) in advk_pcie_link_up() argument
321 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_up()
325 static inline bool advk_pcie_link_active(struct advk_pcie *pcie) in advk_pcie_link_active() argument
328 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_active()
335 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_active()
339 static inline bool advk_pcie_link_training(struct advk_pcie *pcie) in advk_pcie_link_training() argument
342 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_training()
346 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_training()
353 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) in advk_pcie_wait_for_link() argument
359 if (advk_pcie_link_up(pcie)) in advk_pcie_wait_for_link()
368 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) in advk_pcie_wait_for_retrain() argument
373 if (advk_pcie_link_training(pcie)) in advk_pcie_wait_for_retrain()
379 static void advk_pcie_issue_perst(struct advk_pcie *pcie) in advk_pcie_issue_perst() argument
381 if (!pcie->reset_gpio) in advk_pcie_issue_perst()
385 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); in advk_pcie_issue_perst()
386 gpiod_set_value_cansleep(pcie->reset_gpio, 1); in advk_pcie_issue_perst()
388 gpiod_set_value_cansleep(pcie->reset_gpio, 0); in advk_pcie_issue_perst()
391 static void advk_pcie_train_link(struct advk_pcie *pcie) in advk_pcie_train_link() argument
393 struct device *dev = &pcie->pdev->dev; in advk_pcie_train_link()
398 * Setup PCIe rev / gen compliance based on device tree property in advk_pcie_train_link()
401 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
403 if (pcie->link_gen == 3) in advk_pcie_train_link()
405 else if (pcie->link_gen == 2) in advk_pcie_train_link()
409 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
412 * Set maximal link speed value also into PCIe Link Control 2 register. in advk_pcie_train_link()
416 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); in advk_pcie_train_link()
418 if (pcie->link_gen == 3) in advk_pcie_train_link()
420 else if (pcie->link_gen == 2) in advk_pcie_train_link()
424 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); in advk_pcie_train_link()
426 /* Enable link training after selecting PCIe generation */ in advk_pcie_train_link()
427 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
429 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
432 * Reset PCIe card via PERST# signal. Some cards are not detected in advk_pcie_train_link()
435 advk_pcie_issue_perst(pcie); in advk_pcie_train_link()
445 * So wait until PCIe link is up. Function advk_pcie_wait_for_link() in advk_pcie_train_link()
448 ret = advk_pcie_wait_for_link(pcie); in advk_pcie_train_link()
456 * Set PCIe address window register which could be used for memory
459 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num, in advk_pcie_set_ob_win() argument
463 advk_writel(pcie, OB_WIN_ENABLE | in advk_pcie_set_ob_win()
465 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num)); in advk_pcie_set_ob_win()
466 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num)); in advk_pcie_set_ob_win()
467 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num)); in advk_pcie_set_ob_win()
468 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num)); in advk_pcie_set_ob_win()
469 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num)); in advk_pcie_set_ob_win()
470 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num)); in advk_pcie_set_ob_win()
473 static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) in advk_pcie_disable_ob_win() argument
475 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num)); in advk_pcie_disable_ob_win()
476 advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num)); in advk_pcie_disable_ob_win()
477 advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num)); in advk_pcie_disable_ob_win()
478 advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num)); in advk_pcie_disable_ob_win()
479 advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num)); in advk_pcie_disable_ob_win()
480 advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num)); in advk_pcie_disable_ob_win()
481 advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num)); in advk_pcie_disable_ob_win()
484 static void advk_pcie_setup_hw(struct advk_pcie *pcie) in advk_pcie_setup_hw() argument
490 * Configure PCIe Reference clock. Direction is from the PCIe in advk_pcie_setup_hw()
495 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
498 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
501 reg = advk_readl(pcie, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
504 advk_writel(pcie, reg, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
507 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
509 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
519 advk_writel(pcie, reg, VENDOR_ID_REG); in advk_pcie_setup_hw()
536 reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); in advk_pcie_setup_hw()
539 advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG); in advk_pcie_setup_hw()
542 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
544 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
551 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); in advk_pcie_setup_hw()
553 /* Set PCIe Device Control register */ in advk_pcie_setup_hw()
554 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
561 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
563 /* Program PCIe Control 2 to disable strict ordering */ in advk_pcie_setup_hw()
566 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
569 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
572 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
575 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
577 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
580 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); in advk_pcie_setup_hw()
581 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); in advk_pcie_setup_hw()
582 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); in advk_pcie_setup_hw()
587 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
589 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); in advk_pcie_setup_hw()
592 advk_writel(pcie, 0, PCIE_MSI_MASK_REG); in advk_pcie_setup_hw()
596 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); in advk_pcie_setup_hw()
603 * the outbound transactions. Thus, PCIe address in advk_pcie_setup_hw()
608 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
610 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
614 * is not required to configure PCIe address for in advk_pcie_setup_hw()
617 advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS); in advk_pcie_setup_hw()
625 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_setup_hw()
627 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_setup_hw()
630 * Configure PCIe address windows for non-memory or in advk_pcie_setup_hw()
631 * non-transparent access as by default PCIe uses in advk_pcie_setup_hw()
634 for (i = 0; i < pcie->wins_count; i++) in advk_pcie_setup_hw()
635 advk_pcie_set_ob_win(pcie, i, in advk_pcie_setup_hw()
636 pcie->wins[i].match, pcie->wins[i].remap, in advk_pcie_setup_hw()
637 pcie->wins[i].mask, pcie->wins[i].actions); in advk_pcie_setup_hw()
639 /* Disable remaining PCIe outbound windows */ in advk_pcie_setup_hw()
640 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) in advk_pcie_setup_hw()
641 advk_pcie_disable_ob_win(pcie, i); in advk_pcie_setup_hw()
643 advk_pcie_train_link(pcie); in advk_pcie_setup_hw()
646 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val) in advk_pcie_check_pio_status() argument
648 struct device *dev = &pcie->pdev->dev; in advk_pcie_check_pio_status()
654 reg = advk_readl(pcie, PIO_STAT); in advk_pcie_check_pio_status()
682 *val = advk_readl(pcie, PIO_RD_DATA); in advk_pcie_check_pio_status()
693 /* PCIe r4.0, sec 2.3.2, says: in advk_pcie_check_pio_status()
710 /* PCIe r4.0, sec 2.3.2, says: in advk_pcie_check_pio_status()
748 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); in advk_pcie_check_pio_status()
753 static int advk_pcie_wait_pio(struct advk_pcie *pcie) in advk_pcie_wait_pio() argument
755 struct device *dev = &pcie->pdev->dev; in advk_pcie_wait_pio()
761 start = advk_readl(pcie, PIO_START); in advk_pcie_wait_pio()
762 isr = advk_readl(pcie, PIO_ISR); in advk_pcie_wait_pio()
776 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_read() local
780 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pci_bridge_emul_base_conf_read()
791 if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) in advk_pci_bridge_emul_base_conf_read()
808 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_write() local
812 advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); in advk_pci_bridge_emul_base_conf_write()
817 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write()
822 advk_writel(pcie, val, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write()
835 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_read() local
844 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_pcie_conf_read()
852 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG); in advk_pci_bridge_emul_pcie_conf_read()
853 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG); in advk_pci_bridge_emul_pcie_conf_read()
859 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
872 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & in advk_pci_bridge_emul_pcie_conf_read()
874 if (advk_pcie_link_training(pcie)) in advk_pci_bridge_emul_pcie_conf_read()
876 if (advk_pcie_link_active(pcie)) in advk_pci_bridge_emul_pcie_conf_read()
884 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
896 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_write() local
900 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_write()
904 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_write()
906 advk_pcie_wait_for_retrain(pcie); in advk_pci_bridge_emul_pcie_conf_write()
911 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) & in advk_pci_bridge_emul_pcie_conf_write()
915 advk_writel(pcie, val, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_pcie_conf_write()
921 advk_writel(pcie, new, PCIE_ISR0_REG); in advk_pci_bridge_emul_pcie_conf_write()
938 * associated with the given PCIe interface.
940 static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) in advk_sw_pci_bridge_init() argument
942 struct pci_bridge_emul *bridge = &pcie->bridge; in advk_sw_pci_bridge_init()
945 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); in advk_sw_pci_bridge_init()
947 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); in advk_sw_pci_bridge_init()
949 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); in advk_sw_pci_bridge_init()
962 /* Aardvark HW provides PCIe Capability structure in version 2 */ in advk_sw_pci_bridge_init()
969 bridge->data = pcie; in advk_sw_pci_bridge_init()
975 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, in advk_pcie_valid_device() argument
985 if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie)) in advk_pcie_valid_device()
991 static bool advk_pcie_pio_is_running(struct advk_pcie *pcie) in advk_pcie_pio_is_running() argument
993 struct device *dev = &pcie->pdev->dev; in advk_pcie_pio_is_running()
1012 if (advk_readl(pcie, PIO_START)) { in advk_pcie_pio_is_running()
1023 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_rd_conf() local
1029 if (!advk_pcie_valid_device(pcie, bus, devfn)) { in advk_pcie_rd_conf()
1035 return pci_bridge_emul_conf_read(&pcie->bridge, where, in advk_pcie_rd_conf()
1044 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & in advk_pcie_rd_conf()
1047 if (advk_pcie_pio_is_running(pcie)) in advk_pcie_rd_conf()
1051 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_rd_conf()
1057 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_rd_conf()
1061 advk_writel(pcie, reg, PIO_ADDR_LS); in advk_pcie_rd_conf()
1062 advk_writel(pcie, 0, PIO_ADDR_MS); in advk_pcie_rd_conf()
1065 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); in advk_pcie_rd_conf()
1070 advk_writel(pcie, 1, PIO_ISR); in advk_pcie_rd_conf()
1071 advk_writel(pcie, 1, PIO_START); in advk_pcie_rd_conf()
1073 ret = advk_pcie_wait_pio(pcie); in advk_pcie_rd_conf()
1080 ret = advk_pcie_check_pio_status(pcie, allow_crs, val); in advk_pcie_rd_conf()
1111 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_wr_conf() local
1118 if (!advk_pcie_valid_device(pcie, bus, devfn)) in advk_pcie_wr_conf()
1122 return pci_bridge_emul_conf_write(&pcie->bridge, where, in advk_pcie_wr_conf()
1128 if (advk_pcie_pio_is_running(pcie)) in advk_pcie_wr_conf()
1132 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_wr_conf()
1138 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_wr_conf()
1142 advk_writel(pcie, reg, PIO_ADDR_LS); in advk_pcie_wr_conf()
1143 advk_writel(pcie, 0, PIO_ADDR_MS); in advk_pcie_wr_conf()
1151 advk_writel(pcie, reg, PIO_WR_DATA); in advk_pcie_wr_conf()
1154 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); in advk_pcie_wr_conf()
1159 advk_writel(pcie, 1, PIO_ISR); in advk_pcie_wr_conf()
1160 advk_writel(pcie, 1, PIO_START); in advk_pcie_wr_conf()
1162 ret = advk_pcie_wait_pio(pcie); in advk_pcie_wr_conf()
1168 ret = advk_pcie_check_pio_status(pcie, false, NULL); in advk_pcie_wr_conf()
1182 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); in advk_msi_irq_compose_msi_msg() local
1183 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); in advk_msi_irq_compose_msi_msg()
1200 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_alloc() local
1203 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1204 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM, in advk_msi_irq_domain_alloc()
1207 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1211 bitmap_set(pcie->msi_used, hwirq, nr_irqs); in advk_msi_irq_domain_alloc()
1212 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1216 &pcie->msi_bottom_irq_chip, in advk_msi_irq_domain_alloc()
1227 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_free() local
1229 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1230 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs); in advk_msi_irq_domain_free()
1231 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1241 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_mask() local
1246 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1247 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1249 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1250 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1255 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_unmask() local
1260 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1261 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1263 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1264 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1270 struct advk_pcie *pcie = h->host_data; in advk_pcie_irq_map() local
1274 irq_set_chip_and_handler(virq, &pcie->irq_chip, in advk_pcie_irq_map()
1276 irq_set_chip_data(virq, pcie); in advk_pcie_irq_map()
1286 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_msi_irq_domain() argument
1288 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_msi_irq_domain()
1294 mutex_init(&pcie->msi_used_lock); in advk_pcie_init_msi_irq_domain()
1296 bottom_ic = &pcie->msi_bottom_irq_chip; in advk_pcie_init_msi_irq_domain()
1302 msi_ic = &pcie->msi_irq_chip; in advk_pcie_init_msi_irq_domain()
1305 msi_di = &pcie->msi_domain_info; in advk_pcie_init_msi_irq_domain()
1310 msi_msg_phys = virt_to_phys(&pcie->msi_msg); in advk_pcie_init_msi_irq_domain()
1312 advk_writel(pcie, lower_32_bits(msi_msg_phys), in advk_pcie_init_msi_irq_domain()
1314 advk_writel(pcie, upper_32_bits(msi_msg_phys), in advk_pcie_init_msi_irq_domain()
1317 pcie->msi_inner_domain = in advk_pcie_init_msi_irq_domain()
1319 &advk_msi_domain_ops, pcie); in advk_pcie_init_msi_irq_domain()
1320 if (!pcie->msi_inner_domain) in advk_pcie_init_msi_irq_domain()
1323 pcie->msi_domain = in advk_pcie_init_msi_irq_domain()
1325 msi_di, pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1326 if (!pcie->msi_domain) { in advk_pcie_init_msi_irq_domain()
1327 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1334 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_msi_irq_domain() argument
1336 irq_domain_remove(pcie->msi_domain); in advk_pcie_remove_msi_irq_domain()
1337 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_remove_msi_irq_domain()
1340 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_irq_domain() argument
1342 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_irq_domain()
1348 raw_spin_lock_init(&pcie->irq_lock); in advk_pcie_init_irq_domain()
1352 dev_err(dev, "No PCIe Intc node found\n"); in advk_pcie_init_irq_domain()
1356 irq_chip = &pcie->irq_chip; in advk_pcie_init_irq_domain()
1369 pcie->irq_domain = in advk_pcie_init_irq_domain()
1371 &advk_pcie_irq_domain_ops, pcie); in advk_pcie_init_irq_domain()
1372 if (!pcie->irq_domain) { in advk_pcie_init_irq_domain()
1383 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_irq_domain() argument
1385 irq_domain_remove(pcie->irq_domain); in advk_pcie_remove_irq_domain()
1388 static void advk_pcie_handle_msi(struct advk_pcie *pcie) in advk_pcie_handle_msi() argument
1393 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_pcie_handle_msi()
1394 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1405 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1406 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK; in advk_pcie_handle_msi()
1410 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, in advk_pcie_handle_msi()
1414 static void advk_pcie_handle_int(struct advk_pcie *pcie) in advk_pcie_handle_int() argument
1420 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); in advk_pcie_handle_int()
1421 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_handle_int()
1424 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); in advk_pcie_handle_int()
1425 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_handle_int()
1430 advk_pcie_handle_msi(pcie); in advk_pcie_handle_int()
1437 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), in advk_pcie_handle_int()
1440 virq = irq_find_mapping(pcie->irq_domain, i); in advk_pcie_handle_int()
1447 struct advk_pcie *pcie = arg; in advk_pcie_irq_handler() local
1450 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1454 advk_pcie_handle_int(pcie); in advk_pcie_irq_handler()
1457 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1462 static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie) in advk_pcie_disable_phy() argument
1464 phy_power_off(pcie->phy); in advk_pcie_disable_phy()
1465 phy_exit(pcie->phy); in advk_pcie_disable_phy()
1468 static int advk_pcie_enable_phy(struct advk_pcie *pcie) in advk_pcie_enable_phy() argument
1472 if (!pcie->phy) in advk_pcie_enable_phy()
1475 ret = phy_init(pcie->phy); in advk_pcie_enable_phy()
1479 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); in advk_pcie_enable_phy()
1481 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1485 ret = phy_power_on(pcie->phy); in advk_pcie_enable_phy()
1487 dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n"); in advk_pcie_enable_phy()
1489 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1496 static int advk_pcie_setup_phy(struct advk_pcie *pcie) in advk_pcie_setup_phy() argument
1498 struct device *dev = &pcie->pdev->dev; in advk_pcie_setup_phy()
1502 pcie->phy = devm_of_phy_get(dev, node, NULL); in advk_pcie_setup_phy()
1503 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) in advk_pcie_setup_phy()
1504 return PTR_ERR(pcie->phy); in advk_pcie_setup_phy()
1507 if (IS_ERR(pcie->phy)) { in advk_pcie_setup_phy()
1508 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); in advk_pcie_setup_phy()
1509 pcie->phy = NULL; in advk_pcie_setup_phy()
1513 ret = advk_pcie_enable_phy(pcie); in advk_pcie_setup_phy()
1523 struct advk_pcie *pcie; in advk_pcie_probe() local
1532 pcie = pci_host_bridge_priv(bridge); in advk_pcie_probe()
1533 pcie->pdev = pdev; in advk_pcie_probe()
1534 platform_set_drvdata(pdev, pcie); in advk_pcie_probe()
1543 * Aardvark hardware allows to configure also PCIe window in advk_pcie_probe()
1546 * not use PCIe window configuration. in advk_pcie_probe()
1562 * The n-th PCIe window is configured by tuple (match, remap, mask) in advk_pcie_probe()
1565 * So every PCIe window size must be a power of two and every start in advk_pcie_probe()
1570 while (pcie->wins_count < OB_WIN_COUNT && size > 0) { in advk_pcie_probe()
1579 "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n", in advk_pcie_probe()
1580 pcie->wins_count, (unsigned long long)start, in advk_pcie_probe()
1584 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO; in advk_pcie_probe()
1585 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start); in advk_pcie_probe()
1587 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM; in advk_pcie_probe()
1588 pcie->wins[pcie->wins_count].match = start; in advk_pcie_probe()
1590 pcie->wins[pcie->wins_count].remap = start - entry->offset; in advk_pcie_probe()
1591 pcie->wins[pcie->wins_count].mask = ~(win_size - 1); in advk_pcie_probe()
1593 if (pcie->wins[pcie->wins_count].remap & (win_size - 1)) in advk_pcie_probe()
1598 pcie->wins_count++; in advk_pcie_probe()
1602 dev_err(&pcie->pdev->dev, in advk_pcie_probe()
1603 "Invalid PCIe region [0x%llx-0x%llx]\n", in advk_pcie_probe()
1610 pcie->base = devm_platform_ioremap_resource(pdev, 0); in advk_pcie_probe()
1611 if (IS_ERR(pcie->base)) in advk_pcie_probe()
1612 return PTR_ERR(pcie->base); in advk_pcie_probe()
1619 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", in advk_pcie_probe()
1620 pcie); in advk_pcie_probe()
1626 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, in advk_pcie_probe()
1630 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); in advk_pcie_probe()
1633 pcie->reset_gpio = NULL; in advk_pcie_probe()
1644 pcie->link_gen = 3; in advk_pcie_probe()
1646 pcie->link_gen = ret; in advk_pcie_probe()
1648 ret = advk_pcie_setup_phy(pcie); in advk_pcie_probe()
1652 advk_pcie_setup_hw(pcie); in advk_pcie_probe()
1654 ret = advk_sw_pci_bridge_init(pcie); in advk_pcie_probe()
1660 ret = advk_pcie_init_irq_domain(pcie); in advk_pcie_probe()
1666 ret = advk_pcie_init_msi_irq_domain(pcie); in advk_pcie_probe()
1669 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1673 bridge->sysdata = pcie; in advk_pcie_probe()
1678 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_probe()
1679 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1688 struct advk_pcie *pcie = platform_get_drvdata(pdev); in advk_pcie_remove() local
1689 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in advk_pcie_remove()
1697 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_remove()
1698 advk_pcie_remove_irq_domain(pcie); in advk_pcie_remove()
1702 advk_pcie_disable_ob_win(pcie, i); in advk_pcie_remove()
1708 { .compatible = "marvell,armada-3700-pcie", },
1715 .name = "advk-pcie",
1723 MODULE_DESCRIPTION("Aardvark PCIe controller");