Lines Matching +full:0 +full:x1fc
30 #define RC_PCIE_RST_OUTPUT_SHIFT 0
32 #define PAXC_RESET_MASK 0x7f
34 #define GIC_V3_CFG_SHIFT 0
37 #define MSI_ENABLE_CFG_SHIFT 0
40 #define CFG_IND_ADDR_MASK 0x00001ffc
43 #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
45 #define CFG_ADDR_DEV_NUM_MASK 0x000f8000
47 #define CFG_ADDR_FUNC_NUM_MASK 0x00007000
49 #define CFG_ADDR_REG_NUM_MASK 0x00000ffc
50 #define CFG_ADDR_CFG_TYPE_SHIFT 0
51 #define CFG_ADDR_CFG_TYPE_MASK 0x00000003
53 #define SYS_RC_INTX_MASK 0xf
60 #define APB_ERR_EN_SHIFT 0
63 #define CFG_RD_SUCCESS 0
67 #define CFG_RETRY_STATUS 0xffff0001
79 #define OARR_VALID_SHIFT 0
89 #define IMAP_VALID_SHIFT 0
92 #define IPROC_PCI_PM_CAP 0x48
93 #define IPROC_PCI_PM_CAP_MASK 0xffff
94 #define IPROC_PCI_EXP_CAP 0xac
96 #define IPROC_PCIE_REG_INVALID 0xffff
150 IPROC_PCIE_IB_MAP_MEM = 0,
191 .imap_addr_offset = 0x40,
192 .imap_window_offset = 0x4,
201 .imap_addr_offset = 0x4,
202 .imap_window_offset = 0x8,
213 .imap_addr_offset = 0x4,
214 .imap_window_offset = 0x8,
223 .imap_addr_offset = 0x4,
224 .imap_window_offset = 0x8,
233 .imap_addr_offset = 0x4,
234 .imap_window_offset = 0x8,
243 IPROC_PCIE_CLK_CTRL = 0,
318 [IPROC_PCIE_CLK_CTRL] = 0x000,
319 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
320 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
321 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
322 [IPROC_PCIE_CFG_DATA] = 0x1fc,
323 [IPROC_PCIE_INTX_EN] = 0x330,
324 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
329 [IPROC_PCIE_CLK_CTRL] = 0x000,
330 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
331 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
332 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
333 [IPROC_PCIE_CFG_DATA] = 0x1fc,
334 [IPROC_PCIE_INTX_EN] = 0x330,
335 [IPROC_PCIE_OARR0] = 0xd20,
336 [IPROC_PCIE_OMAP0] = 0xd40,
337 [IPROC_PCIE_OARR1] = 0xd28,
338 [IPROC_PCIE_OMAP1] = 0xd48,
339 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
340 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
345 [IPROC_PCIE_CLK_CTRL] = 0x000,
346 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
347 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
348 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
349 [IPROC_PCIE_CFG_DATA] = 0x1fc,
350 [IPROC_PCIE_INTX_EN] = 0x330,
351 [IPROC_PCIE_OARR0] = 0xd20,
352 [IPROC_PCIE_OMAP0] = 0xd40,
353 [IPROC_PCIE_OARR1] = 0xd28,
354 [IPROC_PCIE_OMAP1] = 0xd48,
355 [IPROC_PCIE_OARR2] = 0xd60,
356 [IPROC_PCIE_OMAP2] = 0xd68,
357 [IPROC_PCIE_OARR3] = 0xdf0,
358 [IPROC_PCIE_OMAP3] = 0xdf8,
359 [IPROC_PCIE_IARR0] = 0xd00,
360 [IPROC_PCIE_IMAP0] = 0xc00,
361 [IPROC_PCIE_IARR1] = 0xd08,
362 [IPROC_PCIE_IMAP1] = 0xd70,
363 [IPROC_PCIE_IARR2] = 0xd10,
364 [IPROC_PCIE_IMAP2] = 0xcc0,
365 [IPROC_PCIE_IARR3] = 0xe00,
366 [IPROC_PCIE_IMAP3] = 0xe08,
367 [IPROC_PCIE_IARR4] = 0xe68,
368 [IPROC_PCIE_IMAP4] = 0xe70,
369 [IPROC_PCIE_CFG_RD_STATUS] = 0xee0,
370 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
371 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
376 [IPROC_PCIE_CLK_CTRL] = 0x000,
377 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
378 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
379 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
380 [IPROC_PCIE_CFG_DATA] = 0x1fc,
385 [IPROC_PCIE_MSI_GIC_MODE] = 0x050,
386 [IPROC_PCIE_MSI_BASE_ADDR] = 0x074,
387 [IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078,
388 [IPROC_PCIE_MSI_ADDR_LO] = 0x07c,
389 [IPROC_PCIE_MSI_ADDR_HI] = 0x080,
390 [IPROC_PCIE_MSI_EN_CFG] = 0x09c,
391 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
392 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
393 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
394 [IPROC_PCIE_CFG_DATA] = 0x1fc,
402 0x16cd,
403 0x16f0,
404 0xd802,
405 0xd804
431 return 0; in iproc_pcie_read_reg()
516 * eventually return the wrong data (0xffffffff). in iproc_pcie_cfg_retry()
534 data = 0xffffffff; in iproc_pcie_cfg_retry()
543 switch (where & ~0x3) { in iproc_pcie_fix_cap()
551 for (i = 0; i < ARRAY_SIZE(iproc_pcie_corrupt_cap_did); i++) in iproc_pcie_fix_cap()
594 if (busno == 0) { in iproc_pcie_config_read()
621 * ID of 0x168e (PCI_DEVICE_ID_NX2_57810), we try to catch those access in iproc_pcie_config_read()
624 #define DEVICE_ID_MASK 0xffff0000 in iproc_pcie_config_read()
648 if (busno == 0) { in iproc_pcie_map_cfg_bus()
649 if (slot > 0 || fn > 0) in iproc_pcie_map_cfg_bus()
678 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3); in iproc_pci_raw_config_read32()
680 *val = ~0; in iproc_pci_raw_config_read32()
699 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3); in iproc_pci_raw_config_write32()
708 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); in iproc_pci_raw_config_write32()
710 tmp |= val << ((where & 0x3) * 8); in iproc_pci_raw_config_write32()
781 return 0; in iproc_pcie_shutdown()
796 return 0; in iproc_pcie_check_link()
805 iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type); in iproc_pcie_check_link()
806 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) { in iproc_pcie_check_link()
811 /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */ in iproc_pcie_check_link()
812 #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c in iproc_pcie_check_link()
813 #define PCI_CLASS_BRIDGE_MASK 0xffff00 in iproc_pcie_check_link()
815 iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, in iproc_pcie_check_link()
819 iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, in iproc_pcie_check_link()
823 iproc_pci_raw_config_read32(pcie, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA, in iproc_pcie_check_link()
830 #define PCI_TARGET_LINK_SPEED_MASK 0xf in iproc_pcie_check_link()
831 #define PCI_TARGET_LINK_SPEED_GEN2 0x2 in iproc_pcie_check_link()
832 #define PCI_TARGET_LINK_SPEED_GEN1 0x1 in iproc_pcie_check_link()
833 iproc_pci_raw_config_read32(pcie, 0, in iproc_pcie_check_link()
840 iproc_pci_raw_config_write32(pcie, 0, in iproc_pcie_check_link()
845 iproc_pci_raw_config_read32(pcie, 0, in iproc_pcie_check_link()
855 return link_is_active ? 0 : -ENODEV; in iproc_pcie_check_link()
903 dev_dbg(dev, "ob window [%d]: offset 0x%x axi %pap pci %pap\n", in iproc_pcie_ob_write()
905 dev_dbg(dev, "oarr lo 0x%x oarr hi 0x%x\n", in iproc_pcie_ob_write()
908 dev_dbg(dev, "omap lo 0x%x omap hi 0x%x\n", in iproc_pcie_ob_write()
912 return 0; in iproc_pcie_ob_write()
946 for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) { in iproc_pcie_setup_ob()
962 for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0; in iproc_pcie_setup_ob()
974 if (size_idx > 0 || window_idx > 0) in iproc_pcie_setup_ob()
1005 if (size == 0) in iproc_pcie_setup_ob()
1006 return 0; in iproc_pcie_setup_ob()
1056 return 0; in iproc_pcie_map_ranges()
1094 dev_dbg(dev, "ib region [%d]: offset 0x%x axi %pap pci %pap\n", in iproc_pcie_ib_write()
1105 dev_dbg(dev, "iarr lo 0x%x iarr hi 0x%x\n", in iproc_pcie_ib_write()
1114 for (window_idx = 0; window_idx < nr_windows; window_idx++) { in iproc_pcie_ib_write()
1121 dev_dbg(dev, "imap window [%d] lo 0x%x hi 0x%x\n", in iproc_pcie_ib_write()
1130 return 0; in iproc_pcie_ib_write()
1146 for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) { in iproc_pcie_setup_ib()
1159 for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) { in iproc_pcie_setup_ib()
1181 return 0; in iproc_pcie_setup_ib()
1199 int ret = 0; in iproc_pcie_map_dma_ranges()
1222 for (idx = ob->nr_windows - 1; idx >= 0; idx--) { in iproc_pcie_invalidate_mapping()
1224 MAP_REG(IPROC_PCIE_OARR0, idx), 0); in iproc_pcie_invalidate_mapping()
1230 for (idx = 0; idx < ib->nr_regions; idx++) { in iproc_pcie_invalidate_mapping()
1232 MAP_REG(IPROC_PCIE_IARR0, idx), 0); in iproc_pcie_invalidate_mapping()
1255 ret = of_address_to_resource(msi_node, 0, &res); in iproce_pcie_get_msi()
1256 if (ret < 0) { in iproce_pcie_get_msi()
1262 return 0; in iproce_pcie_get_msi()
1270 memset(&entry, 0, sizeof(entry)); in iproc_pcie_paxb_v2_msi_steer()
1299 * bits [30:0] of the MSI base address register. In fact, in all iProc in iproc_pcie_paxc_v2_msi_steer()
1307 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_WINDOW_SIZE, 0); in iproc_pcie_paxc_v2_msi_steer()
1338 if (ret < 0) { in iproc_pcie_msi_steer()
1356 return 0; in iproc_pcie_msi_steer()
1369 msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0); in iproc_pcie_msi_enable()
1469 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ? in iproc_pcie_rev_init()
1470 IPROC_PCIE_REG_INVALID : regs[0]; in iproc_pcie_rev_init()
1475 return 0; in iproc_pcie_rev_init()
1540 if (ret < 0) { in iproc_pcie_setup()
1545 return 0; in iproc_pcie_setup()
1567 return 0; in iproc_pcie_remove()
1580 iproc_pcie_paxc_v2_msi_steer(pcie, 0, false); in quirk_paxc_disable_msi_parsing()
1582 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0,
1584 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802,
1586 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804,
1600 * MPSS is not being set properly (as it is currently 0). This is in quirk_paxc_bridge()
1607 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
1608 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
1609 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge);
1610 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge);
1611 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge);