Lines Matching +full:0 +full:x028
25 ((x) ? (11 + ((x) - 1) * 6) : 0)
26 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
28 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
30 #define FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT 0
31 #define FUSE_USB_CALIB_EXT_RPD_CTRL_MASK 0x1f
33 #define XUSB_PADCTL_USB2_PAD_MUX 0x004
35 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK 0x3
36 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB 0x1
38 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK 0x3
39 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB 0x1
41 #define XUSB_PADCTL_USB2_PORT_CAP 0x008
42 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4))
43 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
44 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4))
45 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4))
46 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
48 #define XUSB_PADCTL_SS_PORT_MAP 0x014
51 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 5))
52 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5))
53 #define XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED 0x7
55 #define XUSB_PADCTL_ELPG_PROGRAM1 0x024
64 #define XUSB_PADCTL_USB3_PAD_MUX 0x028
68 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(x) (0x080 + (x) * 0x40)
72 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x084 + (x) * 0x40)
74 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x3
75 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL 0x1
78 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40)
82 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT 0
83 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK 0x3f
85 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x08c + (x) * 0x40)
87 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK 0x1f
89 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK 0xf
92 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0)
94 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
97 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK 0x7
98 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x7
99 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT 0
100 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK 0x7
101 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL 0x2
103 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
106 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK 0x7f
107 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL 0x0a
109 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK 0x7f
110 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL 0x1e
112 #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
129 #define XUSB_PADCTL_HSIC_PADX_CTL1(x) (0x304 + (x) * 0x20)
130 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT 0
131 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK 0xf
133 #define XUSB_PADCTL_HSIC_PADX_CTL2(x) (0x308 + (x) * 0x20)
135 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK 0xf
136 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT 0
137 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK 0xff
139 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL 0x340
142 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK 0x7f
143 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL 0x0a
145 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK 0x7f
146 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL 0x1e
148 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x344
150 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
152 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK 0xff
153 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL 0x19
154 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL 0x1e
156 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK 0x3
161 #define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK 0x3
162 #define XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ (1 << 0)
164 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
166 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK 0xffffff
167 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL 0x136
170 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN (1 << 0)
172 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
176 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK 0x3
177 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL 0x2
178 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL 0x0
181 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK 0xf
183 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
185 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK 0xff
186 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL 0x2a
188 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
194 #define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(x) (0x460 + (x) * 0x40)
196 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK 0x3
197 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL 0x1
201 #define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860
203 #define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864
205 #define XUSB_PADCTL_UPHY_PLL_S0_CTL4 0x86c
207 #define XUSB_PADCTL_UPHY_PLL_S0_CTL5 0x870
209 #define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c
211 #define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960
213 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(x) (0xa60 + (x) * 0x40)
215 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK 0x3
216 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL 0x2
218 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(x) (0xa64 + (x) * 0x40)
219 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT 0
220 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK 0xffff
221 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL 0x00fc
223 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(x) (0xa68 + (x) * 0x40)
224 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL 0xc0077f1f
226 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(x) (0xa6c + (x) * 0x40)
228 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK 0xffff
229 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL 0x01c7
231 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(x) (0xa74 + (x) * 0x40)
232 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL 0xfcf01368
234 #define XUSB_PADCTL_USB2_VBUS_ID 0xc60
237 #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK 0xf
239 #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED 0
267 if (pcie->enable > 0) { in tegra210_pex_uphy_enable()
269 return 0; in tegra210_pex_uphy_enable()
273 if (err < 0) in tegra210_pex_uphy_enable()
277 if (err < 0) in tegra210_pex_uphy_enable()
460 return 0; in tegra210_pex_uphy_enable()
475 if (WARN_ON(pcie->enable == 0)) in tegra210_pex_uphy_disable()
478 if (--pcie->enable > 0) in tegra210_pex_uphy_disable()
496 if (sata->enable > 0) { in tegra210_sata_uphy_enable()
498 return 0; in tegra210_sata_uphy_enable()
502 if (err < 0) in tegra210_sata_uphy_enable()
506 if (err < 0) in tegra210_sata_uphy_enable()
702 return 0; in tegra210_sata_uphy_enable()
717 if (WARN_ON(sata->enable == 0)) in tegra210_sata_uphy_disable()
720 if (--sata->enable > 0) in tegra210_sata_uphy_disable()
736 if (padctl->enable++ > 0) in tegra210_xusb_padctl_enable()
757 return 0; in tegra210_xusb_padctl_enable()
766 if (WARN_ON(padctl->enable == 0)) in tegra210_xusb_padctl_disable()
769 if (--padctl->enable > 0) in tegra210_xusb_padctl_disable()
790 return 0; in tegra210_xusb_padctl_disable()
815 return 0; in tegra210_hsic_set_idle()
852 return 0; in tegra210_usb3_set_lfps_detect()
872 TEGRA210_LANE("usb2-0", 0x004, 0, 0x3, usb2),
873 TEGRA210_LANE("usb2-1", 0x004, 2, 0x3, usb2),
874 TEGRA210_LANE("usb2-2", 0x004, 4, 0x3, usb2),
875 TEGRA210_LANE("usb2-3", 0x004, 6, 0x3, usb2),
896 if (err < 0) { in tegra210_usb2_lane_probe()
960 return 0; in tegra210_xusb_padctl_vbus_override()
994 return 0; in tegra210_xusb_padctl_id_override()
1004 int err = 0; in tegra210_usb2_phy_set_mode()
1157 if (pad->enable > 0) { in tegra210_usb2_phy_power_on()
1160 return 0; in tegra210_usb2_phy_power_on()
1195 return 0; in tegra210_usb2_phy_power_on()
1246 if (WARN_ON(pad->enable == 0)) in tegra210_usb2_phy_power_off()
1249 if (--pad->enable > 0) in tegra210_usb2_phy_power_off()
1259 return 0; in tegra210_usb2_phy_power_off()
1289 if (err < 0) { in tegra210_usb2_pad_probe()
1302 if (err < 0) in tegra210_usb2_pad_probe()
1340 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic),
1361 if (err < 0) { in tegra210_hsic_lane_probe()
1482 return 0; in tegra210_hsic_phy_power_on()
1511 return 0; in tegra210_hsic_phy_power_off()
1540 if (err < 0) { in tegra210_hsic_pad_probe()
1553 if (err < 0) in tegra210_hsic_pad_probe()
1593 TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, pcie),
1594 TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, pcie),
1595 TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, pcie),
1596 TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, pcie),
1597 TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, pcie),
1598 TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, pcie),
1599 TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, pcie),
1620 if (err < 0) { in tegra210_pcie_lane_probe()
1664 if (err < 0) in tegra210_pcie_phy_power_on()
1688 return 0; in tegra210_pcie_phy_power_off()
1717 if (err < 0) { in tegra210_pcie_pad_probe()
1737 if (err < 0) in tegra210_pcie_pad_probe()
1770 TEGRA210_LANE("sata-0", 0x028, 30, 0x3, pcie),
1791 if (err < 0) { in tegra210_sata_lane_probe()
1835 if (err < 0) in tegra210_sata_phy_power_on()
1859 return 0; in tegra210_sata_phy_power_off()
1888 if (err < 0) { in tegra210_sata_pad_probe()
1901 if (err < 0) in tegra210_sata_pad_probe()
1942 return 0; in tegra210_usb2_port_enable()
1965 return 0; in tegra210_hsic_port_enable()
2011 if (err < 0) in tegra210_usb3_port_enable()
2068 return 0; in tegra210_usb3_port_enable()
2104 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, 0x7); in tegra210_usb3_port_disable()
2109 { 0, "pcie", 6 },
2111 { 2, "pcie", 0 },
2115 { 0, NULL, 0 }
2151 return 0; in tegra210_utmi_port_reset()
2162 if (err < 0) in tegra210_xusb_read_fuse_calibration()
2165 for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) { in tegra210_xusb_read_fuse_calibration()
2176 if (err < 0) in tegra210_xusb_read_fuse_calibration()
2183 return 0; in tegra210_xusb_read_fuse_calibration()
2201 if (err < 0) in tegra210_xusb_padctl_probe()