1 // SPDX-License-Identifier: GPL-2.0-only
20 static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
36 	__raw_writel(val, &qmgr_regs->acc[queue][0]);  in qmgr_put_entry()
42 	val = __raw_readl(&qmgr_regs->acc[queue][0]);  in qmgr_get_entry()
54 	return (__raw_readl(&qmgr_regs->stat1[queue >> 3])  in __qmgr_get_stat1()
61 	return (__raw_readl(&qmgr_regs->stat2[queue >> 4])  in __qmgr_get_stat2()
66  * qmgr_stat_empty() - checks if a hardware queue is empty
69  * Returns non-zero value if the queue is empty.
78  * qmgr_stat_below_low_watermark() - checks if a queue is below low watermark
81  * Returns non-zero value if the queue is below low watermark.
86 		return (__raw_readl(&qmgr_regs->statne_h) >>  in qmgr_stat_below_low_watermark()
87 			(queue - HALF_QUEUES)) & 0x01;  in qmgr_stat_below_low_watermark()
92  * qmgr_stat_full() - checks if a hardware queue is full
95  * Returns non-zero value if the queue is full.
100 		return (__raw_readl(&qmgr_regs->statf_h) >>  in qmgr_stat_full()
101 			(queue - HALF_QUEUES)) & 0x01;  in qmgr_stat_full()
106  * qmgr_stat_overflow() - checks if a hardware queue experienced overflow
109  * Returns non-zero value if the queue experienced overflow.
124 		int bit;  in qmgr_set_irq()  local
126 		reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */  in qmgr_set_irq()
127 		bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */  in qmgr_set_irq()
128 		__raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit),  in qmgr_set_irq()
131 		/* IRQ source for queues 32-63 is fixed */  in qmgr_set_irq()
145 	/* ACK - it may clear any bits so don't rely on it */  in qmgr_irq1_a0()
146 	__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]);  in qmgr_irq1_a0()
148 	en_bitmap = __raw_readl(&qmgr_regs->irqen[0]);  in qmgr_irq1_a0()
151 		en_bitmap &= ~BIT(i);  in qmgr_irq1_a0()
152 		src = __raw_readl(&qmgr_regs->irqsrc[i >> 3]);  in qmgr_irq1_a0()
153 		stat = __raw_readl(&qmgr_regs->stat1[i >> 3]);  in qmgr_irq1_a0()
156 		if (stat & BIT(src & 3)) {  in qmgr_irq1_a0()
170 	/* ACK - it may clear any bits so don't rely on it */  in qmgr_irq2_a0()
171 	__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[1]);  in qmgr_irq2_a0()
173 	req_bitmap = __raw_readl(&qmgr_regs->irqen[1]) &  in qmgr_irq2_a0()
174 		     __raw_readl(&qmgr_regs->statne_h);  in qmgr_irq2_a0()
177 		req_bitmap &= ~BIT(i);  in qmgr_irq2_a0()
187 	int i, half = (irq == qmgr_irq_1 ? 0 : 1);  in qmgr_irq()  local
188 	u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[half]);  in qmgr_irq()
192 	__raw_writel(req_bitmap, &qmgr_regs->irqstat[half]); /* ACK */  in qmgr_irq()
196 		req_bitmap &= ~BIT(i);  in qmgr_irq()
197 		i += half * HALF_QUEUES;  in qmgr_irq()
207 	int half = queue / 32;  in qmgr_enable_irq()  local
208 	u32 mask = 1 << (queue & (HALF_QUEUES - 1));  in qmgr_enable_irq()
211 	__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask,  in qmgr_enable_irq()
212 		     &qmgr_regs->irqen[half]);  in qmgr_enable_irq()
219 	int half = queue / 32;  in qmgr_disable_irq()  local
220 	u32 mask = 1 << (queue & (HALF_QUEUES - 1));  in qmgr_disable_irq()
223 	__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask,  in qmgr_disable_irq()
224 		     &qmgr_regs->irqen[half]);  in qmgr_disable_irq()
225 	__raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */  in qmgr_disable_irq()
248 	u32 cfg, addr = 0, mask[4]; /* in 16-dwords */  in qmgr_request_queue()
254 		return -EINVAL;  in qmgr_request_queue()
274 		return -EINVAL;  in qmgr_request_queue()
279 	len /= 16;		/* in 16-dwords: 1, 2, 4 or 8 */  in qmgr_request_queue()
283 		return -ENODEV;  in qmgr_request_queue()
286 	if (__raw_readl(&qmgr_regs->sram[queue])) {  in qmgr_request_queue()
287 		err = -EBUSY;  in qmgr_request_queue()
300 		if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {  in qmgr_request_queue()
303 			err = -ENOMEM;  in qmgr_request_queue()
312 	__raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);  in qmgr_request_queue()
335 	cfg = __raw_readl(&qmgr_regs->sram[queue]);  in qmgr_release_queue()
349 	while (addr--)  in qmgr_release_queue()
362 	__raw_writel(0, &qmgr_regs->sram[queue]);  in qmgr_release_queue()
378 	struct device *dev = &pdev->dev;  in ixp4xx_qmgr_probe()
384 		return -ENODEV;  in ixp4xx_qmgr_probe()
391 		return irq1 ? irq1 : -EINVAL;  in ixp4xx_qmgr_probe()
395 		return irq2 ? irq2 : -EINVAL;  in ixp4xx_qmgr_probe()
400 		__raw_writel(0x33333333, &qmgr_regs->stat1[i]);  in ixp4xx_qmgr_probe()
401 		__raw_writel(0, &qmgr_regs->irqsrc[i]);  in ixp4xx_qmgr_probe()
404 		__raw_writel(0, &qmgr_regs->stat2[i]);  in ixp4xx_qmgr_probe()
405 		__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */  in ixp4xx_qmgr_probe()
406 		__raw_writel(0, &qmgr_regs->irqen[i]);  in ixp4xx_qmgr_probe()
409 	__raw_writel(0xFFFFFFFF, &qmgr_regs->statne_h);  in ixp4xx_qmgr_probe()
410 	__raw_writel(0, &qmgr_regs->statf_h);  in ixp4xx_qmgr_probe()
413 		__raw_writel(0, &qmgr_regs->sram[i]);  in ixp4xx_qmgr_probe()
453 		.compatible = "intel,ixp4xx-ahb-queue-manager",
460 		.name           = "ixp4xx-qmgr",