Lines Matching +full:spi +full:- +full:samsung
1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 // Jaswinder Singh <jassi.brar@samsung.com>
11 #include <linux/dma-mapping.h>
15 #include <linux/spi/spi.h>
20 #include <linux/platform_data/spi-s3c64xx.h>
27 /* Registers and bit-fields */
105 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
107 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
109 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
118 #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
130 * struct s3c64xx_spi_info - SPI Controller hardware info
131 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
140 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
141 * differ in some aspects such as the size of the fifo and spi bus clock
156 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
157 * @clk: Pointer to the spi clock.
158 * @src_clk: Pointer to the clock used to generate SPI signals.
161 * @master: Pointer to the SPI Protocol master.
165 * @sfr_start: BUS address of SPI controller regs.
173 * @port_conf: Local SPI port configuartion data
198 void __iomem *regs = sdd->regs; in s3c64xx_flush_fifo()
217 } while (TX_FIFO_LVL(val, sdd) && loops--); in s3c64xx_flush_fifo()
220 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); in s3c64xx_flush_fifo()
230 } while (loops--); in s3c64xx_flush_fifo()
233 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); in s3c64xx_flush_fifo()
250 if (dma->direction == DMA_DEV_TO_MEM) in s3c64xx_spi_dmacb()
257 spin_lock_irqsave(&sdd->lock, flags); in s3c64xx_spi_dmacb()
259 if (dma->direction == DMA_DEV_TO_MEM) { in s3c64xx_spi_dmacb()
260 sdd->state &= ~RXBUSY; in s3c64xx_spi_dmacb()
261 if (!(sdd->state & TXBUSY)) in s3c64xx_spi_dmacb()
262 complete(&sdd->xfer_completion); in s3c64xx_spi_dmacb()
264 sdd->state &= ~TXBUSY; in s3c64xx_spi_dmacb()
265 if (!(sdd->state & RXBUSY)) in s3c64xx_spi_dmacb()
266 complete(&sdd->xfer_completion); in s3c64xx_spi_dmacb()
269 spin_unlock_irqrestore(&sdd->lock, flags); in s3c64xx_spi_dmacb()
282 if (dma->direction == DMA_DEV_TO_MEM) { in prepare_dma()
285 config.direction = dma->direction; in prepare_dma()
286 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; in prepare_dma()
287 config.src_addr_width = sdd->cur_bpw / 8; in prepare_dma()
289 dmaengine_slave_config(dma->ch, &config); in prepare_dma()
293 config.direction = dma->direction; in prepare_dma()
294 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; in prepare_dma()
295 config.dst_addr_width = sdd->cur_bpw / 8; in prepare_dma()
297 dmaengine_slave_config(dma->ch, &config); in prepare_dma()
300 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, in prepare_dma()
301 dma->direction, DMA_PREP_INTERRUPT); in prepare_dma()
303 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist", in prepare_dma()
304 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx"); in prepare_dma()
305 return -ENOMEM; in prepare_dma()
308 desc->callback = s3c64xx_spi_dmacb; in prepare_dma()
309 desc->callback_param = dma; in prepare_dma()
311 dma->cookie = dmaengine_submit(desc); in prepare_dma()
312 ret = dma_submit_error(dma->cookie); in prepare_dma()
314 dev_err(&sdd->pdev->dev, "DMA submission failed"); in prepare_dma()
315 return -EIO; in prepare_dma()
318 dma_async_issue_pending(dma->ch); in prepare_dma()
322 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable) in s3c64xx_spi_set_cs() argument
325 spi_master_get_devdata(spi->master); in s3c64xx_spi_set_cs()
327 if (sdd->cntrlr_info->no_cs) in s3c64xx_spi_set_cs()
331 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { in s3c64xx_spi_set_cs()
332 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
334 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
338 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
341 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) in s3c64xx_spi_set_cs()
343 sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
347 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) in s3c64xx_spi_prepare_transfer() argument
349 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); in s3c64xx_spi_prepare_transfer()
354 spi->dma_rx = sdd->rx_dma.ch; in s3c64xx_spi_prepare_transfer()
355 spi->dma_tx = sdd->tx_dma.ch; in s3c64xx_spi_prepare_transfer()
361 struct spi_device *spi, in s3c64xx_spi_can_dma() argument
366 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; in s3c64xx_spi_can_dma()
372 void __iomem *regs = sdd->regs; in s3c64xx_enable_datapath()
390 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) in s3c64xx_enable_datapath()
395 if (xfer->tx_buf != NULL) { in s3c64xx_enable_datapath()
396 sdd->state |= TXBUSY; in s3c64xx_enable_datapath()
400 ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg); in s3c64xx_enable_datapath()
402 switch (sdd->cur_bpw) { in s3c64xx_enable_datapath()
405 xfer->tx_buf, xfer->len / 4); in s3c64xx_enable_datapath()
409 xfer->tx_buf, xfer->len / 2); in s3c64xx_enable_datapath()
413 xfer->tx_buf, xfer->len); in s3c64xx_enable_datapath()
419 if (xfer->rx_buf != NULL) { in s3c64xx_enable_datapath()
420 sdd->state |= RXBUSY; in s3c64xx_enable_datapath()
422 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL in s3c64xx_enable_datapath()
423 && !(sdd->cur_mode & SPI_CPHA)) in s3c64xx_enable_datapath()
429 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) in s3c64xx_enable_datapath()
432 ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg); in s3c64xx_enable_datapath()
448 void __iomem *regs = sdd->regs; in s3c64xx_spi_wait_for_timeout()
460 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); in s3c64xx_spi_wait_for_timeout()
469 void __iomem *regs = sdd->regs; in s3c64xx_wait_for_dma()
475 ms = xfer->len * 8 * 1000 / sdd->cur_speed; in s3c64xx_wait_for_dma()
480 val = wait_for_completion_timeout(&sdd->xfer_completion, val); in s3c64xx_wait_for_dma()
484 * proceed further else return -EIO. in s3c64xx_wait_for_dma()
491 if (val && !xfer->rx_buf) { in s3c64xx_wait_for_dma()
496 && --val) { in s3c64xx_wait_for_dma()
505 return -EIO; in s3c64xx_wait_for_dma()
513 void __iomem *regs = sdd->regs; in s3c64xx_wait_for_pio()
522 ms = xfer->len * 8 * 1000 / sdd->cur_speed; in s3c64xx_wait_for_pio()
528 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); in s3c64xx_wait_for_pio()
531 return -EIO; in s3c64xx_wait_for_pio()
534 if (!xfer->rx_buf) { in s3c64xx_wait_for_pio()
535 sdd->state &= ~TXBUSY; in s3c64xx_wait_for_pio()
547 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); in s3c64xx_wait_for_pio()
548 buf = xfer->rx_buf; in s3c64xx_wait_for_pio()
554 switch (sdd->cur_bpw) { in s3c64xx_wait_for_pio()
570 } while (loops--); in s3c64xx_wait_for_pio()
571 sdd->state &= ~RXBUSY; in s3c64xx_wait_for_pio()
578 void __iomem *regs = sdd->regs; in s3c64xx_spi_config()
583 if (!sdd->port_conf->clk_from_cmu) { in s3c64xx_spi_config()
595 if (sdd->cur_mode & SPI_CPOL) in s3c64xx_spi_config()
598 if (sdd->cur_mode & SPI_CPHA) in s3c64xx_spi_config()
608 switch (sdd->cur_bpw) { in s3c64xx_spi_config()
625 if (sdd->port_conf->clk_from_cmu) { in s3c64xx_spi_config()
627 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); in s3c64xx_spi_config()
630 sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2; in s3c64xx_spi_config()
635 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) in s3c64xx_spi_config()
654 struct spi_device *spi = msg->spi; in s3c64xx_spi_prepare_message() local
655 struct s3c64xx_spi_csinfo *cs = spi->controller_data; in s3c64xx_spi_prepare_message()
658 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); in s3c64xx_spi_prepare_message()
664 struct spi_device *spi, in s3c64xx_spi_transfer_one() argument
678 reinit_completion(&sdd->xfer_completion); in s3c64xx_spi_transfer_one()
681 bpw = xfer->bits_per_word; in s3c64xx_spi_transfer_one()
682 speed = xfer->speed_hz; in s3c64xx_spi_transfer_one()
684 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { in s3c64xx_spi_transfer_one()
685 sdd->cur_bpw = bpw; in s3c64xx_spi_transfer_one()
686 sdd->cur_speed = speed; in s3c64xx_spi_transfer_one()
687 sdd->cur_mode = spi->mode; in s3c64xx_spi_transfer_one()
693 if (!is_polling(sdd) && (xfer->len > fifo_len) && in s3c64xx_spi_transfer_one()
694 sdd->rx_dma.ch && sdd->tx_dma.ch) { in s3c64xx_spi_transfer_one()
697 } else if (is_polling(sdd) && xfer->len > fifo_len) { in s3c64xx_spi_transfer_one()
698 tx_buf = xfer->tx_buf; in s3c64xx_spi_transfer_one()
699 rx_buf = xfer->rx_buf; in s3c64xx_spi_transfer_one()
700 origin_len = xfer->len; in s3c64xx_spi_transfer_one()
702 target_len = xfer->len; in s3c64xx_spi_transfer_one()
703 if (xfer->len > fifo_len) in s3c64xx_spi_transfer_one()
704 xfer->len = fifo_len; in s3c64xx_spi_transfer_one()
708 spin_lock_irqsave(&sdd->lock, flags); in s3c64xx_spi_transfer_one()
711 sdd->state &= ~RXBUSY; in s3c64xx_spi_transfer_one()
712 sdd->state &= ~TXBUSY; in s3c64xx_spi_transfer_one()
715 s3c64xx_spi_set_cs(spi, true); in s3c64xx_spi_transfer_one()
719 spin_unlock_irqrestore(&sdd->lock, flags); in s3c64xx_spi_transfer_one()
722 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status); in s3c64xx_spi_transfer_one()
732 dev_err(&spi->dev, in s3c64xx_spi_transfer_one()
733 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n", in s3c64xx_spi_transfer_one()
734 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, in s3c64xx_spi_transfer_one()
735 (sdd->state & RXBUSY) ? 'f' : 'p', in s3c64xx_spi_transfer_one()
736 (sdd->state & TXBUSY) ? 'f' : 'p', in s3c64xx_spi_transfer_one()
737 xfer->len, use_dma ? 1 : 0, status); in s3c64xx_spi_transfer_one()
742 if (xfer->tx_buf && (sdd->state & TXBUSY)) { in s3c64xx_spi_transfer_one()
743 dmaengine_pause(sdd->tx_dma.ch); in s3c64xx_spi_transfer_one()
744 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s); in s3c64xx_spi_transfer_one()
745 dmaengine_terminate_all(sdd->tx_dma.ch); in s3c64xx_spi_transfer_one()
746 dev_err(&spi->dev, "TX residue: %d\n", s.residue); in s3c64xx_spi_transfer_one()
749 if (xfer->rx_buf && (sdd->state & RXBUSY)) { in s3c64xx_spi_transfer_one()
750 dmaengine_pause(sdd->rx_dma.ch); in s3c64xx_spi_transfer_one()
751 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s); in s3c64xx_spi_transfer_one()
752 dmaengine_terminate_all(sdd->rx_dma.ch); in s3c64xx_spi_transfer_one()
753 dev_err(&spi->dev, "RX residue: %d\n", s.residue); in s3c64xx_spi_transfer_one()
760 target_len -= xfer->len; in s3c64xx_spi_transfer_one()
762 if (xfer->tx_buf) in s3c64xx_spi_transfer_one()
763 xfer->tx_buf += xfer->len; in s3c64xx_spi_transfer_one()
765 if (xfer->rx_buf) in s3c64xx_spi_transfer_one()
766 xfer->rx_buf += xfer->len; in s3c64xx_spi_transfer_one()
769 xfer->len = fifo_len; in s3c64xx_spi_transfer_one()
771 xfer->len = target_len; in s3c64xx_spi_transfer_one()
777 xfer->tx_buf = tx_buf; in s3c64xx_spi_transfer_one()
778 xfer->rx_buf = rx_buf; in s3c64xx_spi_transfer_one()
779 xfer->len = origin_len; in s3c64xx_spi_transfer_one()
786 struct spi_device *spi) in s3c64xx_get_slave_ctrldata() argument
792 slave_np = spi->dev.of_node; in s3c64xx_get_slave_ctrldata()
794 dev_err(&spi->dev, "device node not found\n"); in s3c64xx_get_slave_ctrldata()
795 return ERR_PTR(-EINVAL); in s3c64xx_get_slave_ctrldata()
798 data_np = of_get_child_by_name(slave_np, "controller-data"); in s3c64xx_get_slave_ctrldata()
800 dev_err(&spi->dev, "child node 'controller-data' not found\n"); in s3c64xx_get_slave_ctrldata()
801 return ERR_PTR(-EINVAL); in s3c64xx_get_slave_ctrldata()
807 return ERR_PTR(-ENOMEM); in s3c64xx_get_slave_ctrldata()
810 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); in s3c64xx_get_slave_ctrldata()
811 cs->fb_delay = fb_delay; in s3c64xx_get_slave_ctrldata()
818 * and save the configuration in a local data-structure.
822 static int s3c64xx_spi_setup(struct spi_device *spi) in s3c64xx_spi_setup() argument
824 struct s3c64xx_spi_csinfo *cs = spi->controller_data; in s3c64xx_spi_setup()
828 sdd = spi_master_get_devdata(spi->master); in s3c64xx_spi_setup()
829 if (spi->dev.of_node) { in s3c64xx_spi_setup()
830 cs = s3c64xx_get_slave_ctrldata(spi); in s3c64xx_spi_setup()
831 spi->controller_data = cs; in s3c64xx_spi_setup()
833 /* On non-DT platforms the SPI core will set spi->cs_gpio in s3c64xx_spi_setup()
834 * to -ENOENT. The GPIO pin used to drive the chip select in s3c64xx_spi_setup()
835 * is defined by using platform data so spi->cs_gpio value in s3c64xx_spi_setup()
838 spi->cs_gpio = cs->line; in s3c64xx_spi_setup()
842 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); in s3c64xx_spi_setup()
843 return -ENODEV; in s3c64xx_spi_setup()
846 if (!spi_get_ctldata(spi)) { in s3c64xx_spi_setup()
847 if (gpio_is_valid(spi->cs_gpio)) { in s3c64xx_spi_setup()
848 err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH, in s3c64xx_spi_setup()
849 dev_name(&spi->dev)); in s3c64xx_spi_setup()
851 dev_err(&spi->dev, in s3c64xx_spi_setup()
853 spi->cs_gpio, err); in s3c64xx_spi_setup()
858 spi_set_ctldata(spi, cs); in s3c64xx_spi_setup()
861 pm_runtime_get_sync(&sdd->pdev->dev); in s3c64xx_spi_setup()
864 if (!sdd->port_conf->clk_from_cmu) { in s3c64xx_spi_setup()
868 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); in s3c64xx_spi_setup()
870 if (spi->max_speed_hz > speed) in s3c64xx_spi_setup()
871 spi->max_speed_hz = speed; in s3c64xx_spi_setup()
873 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; in s3c64xx_spi_setup()
876 psr--; in s3c64xx_spi_setup()
878 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); in s3c64xx_spi_setup()
879 if (spi->max_speed_hz < speed) { in s3c64xx_spi_setup()
883 err = -EINVAL; in s3c64xx_spi_setup()
888 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); in s3c64xx_spi_setup()
889 if (spi->max_speed_hz >= speed) { in s3c64xx_spi_setup()
890 spi->max_speed_hz = speed; in s3c64xx_spi_setup()
892 dev_err(&spi->dev, "Can't set %dHz transfer speed\n", in s3c64xx_spi_setup()
893 spi->max_speed_hz); in s3c64xx_spi_setup()
894 err = -EINVAL; in s3c64xx_spi_setup()
899 pm_runtime_mark_last_busy(&sdd->pdev->dev); in s3c64xx_spi_setup()
900 pm_runtime_put_autosuspend(&sdd->pdev->dev); in s3c64xx_spi_setup()
901 s3c64xx_spi_set_cs(spi, false); in s3c64xx_spi_setup()
906 pm_runtime_mark_last_busy(&sdd->pdev->dev); in s3c64xx_spi_setup()
907 pm_runtime_put_autosuspend(&sdd->pdev->dev); in s3c64xx_spi_setup()
908 /* setup() returns with device de-selected */ in s3c64xx_spi_setup()
909 s3c64xx_spi_set_cs(spi, false); in s3c64xx_spi_setup()
911 if (gpio_is_valid(spi->cs_gpio)) in s3c64xx_spi_setup()
912 gpio_free(spi->cs_gpio); in s3c64xx_spi_setup()
913 spi_set_ctldata(spi, NULL); in s3c64xx_spi_setup()
916 if (spi->dev.of_node) in s3c64xx_spi_setup()
922 static void s3c64xx_spi_cleanup(struct spi_device *spi) in s3c64xx_spi_cleanup() argument
924 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); in s3c64xx_spi_cleanup()
926 if (gpio_is_valid(spi->cs_gpio)) { in s3c64xx_spi_cleanup()
927 gpio_free(spi->cs_gpio); in s3c64xx_spi_cleanup()
928 if (spi->dev.of_node) in s3c64xx_spi_cleanup()
931 /* On non-DT platforms, the SPI core sets in s3c64xx_spi_cleanup()
932 * spi->cs_gpio to -ENOENT and .setup() in s3c64xx_spi_cleanup()
936 spi->cs_gpio = -ENOENT; in s3c64xx_spi_cleanup()
940 spi_set_ctldata(spi, NULL); in s3c64xx_spi_cleanup()
946 struct spi_master *spi = sdd->master; in s3c64xx_spi_irq() local
949 val = readl(sdd->regs + S3C64XX_SPI_STATUS); in s3c64xx_spi_irq()
953 dev_err(&spi->dev, "RX overrun\n"); in s3c64xx_spi_irq()
957 dev_err(&spi->dev, "RX underrun\n"); in s3c64xx_spi_irq()
961 dev_err(&spi->dev, "TX overrun\n"); in s3c64xx_spi_irq()
965 dev_err(&spi->dev, "TX underrun\n"); in s3c64xx_spi_irq()
969 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); in s3c64xx_spi_irq()
970 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); in s3c64xx_spi_irq()
977 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; in s3c64xx_spi_hwinit()
978 void __iomem *regs = sdd->regs; in s3c64xx_spi_hwinit()
981 sdd->cur_speed = 0; in s3c64xx_spi_hwinit()
983 if (sci->no_cs) in s3c64xx_spi_hwinit()
984 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_hwinit()
985 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) in s3c64xx_spi_hwinit()
986 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_hwinit()
988 /* Disable Interrupts - we use Polling if not DMA mode */ in s3c64xx_spi_hwinit()
991 if (!sdd->port_conf->clk_from_cmu) in s3c64xx_spi_hwinit()
992 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, in s3c64xx_spi_hwinit()
1024 return ERR_PTR(-ENOMEM); in s3c64xx_spi_parse_dt()
1026 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { in s3c64xx_spi_parse_dt()
1027 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); in s3c64xx_spi_parse_dt()
1028 sci->src_clk_nr = 0; in s3c64xx_spi_parse_dt()
1030 sci->src_clk_nr = temp; in s3c64xx_spi_parse_dt()
1033 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { in s3c64xx_spi_parse_dt()
1035 sci->num_cs = 1; in s3c64xx_spi_parse_dt()
1037 sci->num_cs = temp; in s3c64xx_spi_parse_dt()
1040 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback"); in s3c64xx_spi_parse_dt()
1057 if (pdev->dev.of_node) { in s3c64xx_spi_get_port_config()
1059 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); in s3c64xx_spi_get_port_config()
1060 return (struct s3c64xx_spi_port_config *)match->data; in s3c64xx_spi_get_port_config()
1064 platform_get_device_id(pdev)->driver_data; in s3c64xx_spi_get_port_config()
1071 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); in s3c64xx_spi_probe()
1076 if (!sci && pdev->dev.of_node) { in s3c64xx_spi_probe()
1077 sci = s3c64xx_spi_parse_dt(&pdev->dev); in s3c64xx_spi_probe()
1083 dev_err(&pdev->dev, "platform_data missing!\n"); in s3c64xx_spi_probe()
1084 return -ENODEV; in s3c64xx_spi_probe()
1089 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); in s3c64xx_spi_probe()
1090 return -ENXIO; in s3c64xx_spi_probe()
1095 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); in s3c64xx_spi_probe()
1099 master = spi_alloc_master(&pdev->dev, in s3c64xx_spi_probe()
1102 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); in s3c64xx_spi_probe()
1103 return -ENOMEM; in s3c64xx_spi_probe()
1109 sdd->port_conf = s3c64xx_spi_get_port_config(pdev); in s3c64xx_spi_probe()
1110 sdd->master = master; in s3c64xx_spi_probe()
1111 sdd->cntrlr_info = sci; in s3c64xx_spi_probe()
1112 sdd->pdev = pdev; in s3c64xx_spi_probe()
1113 sdd->sfr_start = mem_res->start; in s3c64xx_spi_probe()
1114 if (pdev->dev.of_node) { in s3c64xx_spi_probe()
1115 ret = of_alias_get_id(pdev->dev.of_node, "spi"); in s3c64xx_spi_probe()
1117 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", in s3c64xx_spi_probe()
1121 sdd->port_id = ret; in s3c64xx_spi_probe()
1123 sdd->port_id = pdev->id; in s3c64xx_spi_probe()
1126 sdd->cur_bpw = 8; in s3c64xx_spi_probe()
1128 sdd->tx_dma.direction = DMA_MEM_TO_DEV; in s3c64xx_spi_probe()
1129 sdd->rx_dma.direction = DMA_DEV_TO_MEM; in s3c64xx_spi_probe()
1131 master->dev.of_node = pdev->dev.of_node; in s3c64xx_spi_probe()
1132 master->bus_num = sdd->port_id; in s3c64xx_spi_probe()
1133 master->setup = s3c64xx_spi_setup; in s3c64xx_spi_probe()
1134 master->cleanup = s3c64xx_spi_cleanup; in s3c64xx_spi_probe()
1135 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; in s3c64xx_spi_probe()
1136 master->prepare_message = s3c64xx_spi_prepare_message; in s3c64xx_spi_probe()
1137 master->transfer_one = s3c64xx_spi_transfer_one; in s3c64xx_spi_probe()
1138 master->num_chipselect = sci->num_cs; in s3c64xx_spi_probe()
1139 master->dma_alignment = 8; in s3c64xx_spi_probe()
1140 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | in s3c64xx_spi_probe()
1142 /* the spi->mode bits understood by this driver: */ in s3c64xx_spi_probe()
1143 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in s3c64xx_spi_probe()
1144 master->auto_runtime_pm = true; in s3c64xx_spi_probe()
1146 master->can_dma = s3c64xx_spi_can_dma; in s3c64xx_spi_probe()
1148 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); in s3c64xx_spi_probe()
1149 if (IS_ERR(sdd->regs)) { in s3c64xx_spi_probe()
1150 ret = PTR_ERR(sdd->regs); in s3c64xx_spi_probe()
1154 if (sci->cfg_gpio && sci->cfg_gpio()) { in s3c64xx_spi_probe()
1155 dev_err(&pdev->dev, "Unable to config gpio\n"); in s3c64xx_spi_probe()
1156 ret = -EBUSY; in s3c64xx_spi_probe()
1161 sdd->clk = devm_clk_get(&pdev->dev, "spi"); in s3c64xx_spi_probe()
1162 if (IS_ERR(sdd->clk)) { in s3c64xx_spi_probe()
1163 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); in s3c64xx_spi_probe()
1164 ret = PTR_ERR(sdd->clk); in s3c64xx_spi_probe()
1168 ret = clk_prepare_enable(sdd->clk); in s3c64xx_spi_probe()
1170 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); in s3c64xx_spi_probe()
1174 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); in s3c64xx_spi_probe()
1175 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); in s3c64xx_spi_probe()
1176 if (IS_ERR(sdd->src_clk)) { in s3c64xx_spi_probe()
1177 dev_err(&pdev->dev, in s3c64xx_spi_probe()
1179 ret = PTR_ERR(sdd->src_clk); in s3c64xx_spi_probe()
1183 ret = clk_prepare_enable(sdd->src_clk); in s3c64xx_spi_probe()
1185 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); in s3c64xx_spi_probe()
1189 if (sdd->port_conf->clk_ioclk) { in s3c64xx_spi_probe()
1190 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk"); in s3c64xx_spi_probe()
1191 if (IS_ERR(sdd->ioclk)) { in s3c64xx_spi_probe()
1192 dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n"); in s3c64xx_spi_probe()
1193 ret = PTR_ERR(sdd->ioclk); in s3c64xx_spi_probe()
1197 ret = clk_prepare_enable(sdd->ioclk); in s3c64xx_spi_probe()
1199 dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n"); in s3c64xx_spi_probe()
1206 sdd->rx_dma.ch = dma_request_chan(&pdev->dev, "rx"); in s3c64xx_spi_probe()
1207 if (IS_ERR(sdd->rx_dma.ch)) { in s3c64xx_spi_probe()
1208 dev_err(&pdev->dev, "Failed to get RX DMA channel\n"); in s3c64xx_spi_probe()
1209 ret = PTR_ERR(sdd->rx_dma.ch); in s3c64xx_spi_probe()
1212 sdd->tx_dma.ch = dma_request_chan(&pdev->dev, "tx"); in s3c64xx_spi_probe()
1213 if (IS_ERR(sdd->tx_dma.ch)) { in s3c64xx_spi_probe()
1214 dev_err(&pdev->dev, "Failed to get TX DMA channel\n"); in s3c64xx_spi_probe()
1215 ret = PTR_ERR(sdd->tx_dma.ch); in s3c64xx_spi_probe()
1220 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); in s3c64xx_spi_probe()
1221 pm_runtime_use_autosuspend(&pdev->dev); in s3c64xx_spi_probe()
1222 pm_runtime_set_active(&pdev->dev); in s3c64xx_spi_probe()
1223 pm_runtime_enable(&pdev->dev); in s3c64xx_spi_probe()
1224 pm_runtime_get_sync(&pdev->dev); in s3c64xx_spi_probe()
1229 spin_lock_init(&sdd->lock); in s3c64xx_spi_probe()
1230 init_completion(&sdd->xfer_completion); in s3c64xx_spi_probe()
1232 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, in s3c64xx_spi_probe()
1233 "spi-s3c64xx", sdd); in s3c64xx_spi_probe()
1235 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", in s3c64xx_spi_probe()
1242 sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_probe()
1244 ret = devm_spi_register_master(&pdev->dev, master); in s3c64xx_spi_probe()
1246 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); in s3c64xx_spi_probe()
1250 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", in s3c64xx_spi_probe()
1251 sdd->port_id, master->num_chipselect); in s3c64xx_spi_probe()
1252 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", in s3c64xx_spi_probe()
1255 pm_runtime_mark_last_busy(&pdev->dev); in s3c64xx_spi_probe()
1256 pm_runtime_put_autosuspend(&pdev->dev); in s3c64xx_spi_probe()
1261 pm_runtime_put_noidle(&pdev->dev); in s3c64xx_spi_probe()
1262 pm_runtime_disable(&pdev->dev); in s3c64xx_spi_probe()
1263 pm_runtime_set_suspended(&pdev->dev); in s3c64xx_spi_probe()
1266 dma_release_channel(sdd->tx_dma.ch); in s3c64xx_spi_probe()
1269 dma_release_channel(sdd->rx_dma.ch); in s3c64xx_spi_probe()
1271 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_probe()
1273 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_probe()
1275 clk_disable_unprepare(sdd->clk); in s3c64xx_spi_probe()
1287 pm_runtime_get_sync(&pdev->dev); in s3c64xx_spi_remove()
1289 writel(0, sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_remove()
1292 dma_release_channel(sdd->rx_dma.ch); in s3c64xx_spi_remove()
1293 dma_release_channel(sdd->tx_dma.ch); in s3c64xx_spi_remove()
1296 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_remove()
1298 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_remove()
1300 clk_disable_unprepare(sdd->clk); in s3c64xx_spi_remove()
1302 pm_runtime_put_noidle(&pdev->dev); in s3c64xx_spi_remove()
1303 pm_runtime_disable(&pdev->dev); in s3c64xx_spi_remove()
1304 pm_runtime_set_suspended(&pdev->dev); in s3c64xx_spi_remove()
1323 sdd->cur_speed = 0; /* Output Clock is stopped */ in s3c64xx_spi_suspend()
1332 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; in s3c64xx_spi_resume()
1335 if (sci->cfg_gpio) in s3c64xx_spi_resume()
1336 sci->cfg_gpio(); in s3c64xx_spi_resume()
1352 clk_disable_unprepare(sdd->clk); in s3c64xx_spi_runtime_suspend()
1353 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_runtime_suspend()
1354 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_runtime_suspend()
1365 if (sdd->port_conf->clk_ioclk) { in s3c64xx_spi_runtime_resume()
1366 ret = clk_prepare_enable(sdd->ioclk); in s3c64xx_spi_runtime_resume()
1371 ret = clk_prepare_enable(sdd->src_clk); in s3c64xx_spi_runtime_resume()
1375 ret = clk_prepare_enable(sdd->clk); in s3c64xx_spi_runtime_resume()
1383 sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_runtime_resume()
1388 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_runtime_resume()
1390 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_runtime_resume()
1452 .name = "s3c2443-spi",
1455 .name = "s3c6410-spi",
1462 { .compatible = "samsung,s3c2443-spi",
1465 { .compatible = "samsung,s3c6410-spi",
1468 { .compatible = "samsung,s5pv210-spi",
1471 { .compatible = "samsung,exynos4210-spi",
1474 { .compatible = "samsung,exynos7-spi",
1477 { .compatible = "samsung,exynos5433-spi",
1486 .name = "s3c64xx-spi",
1494 MODULE_ALIAS("platform:s3c64xx-spi");
1498 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1499 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");