183 	u32 config_reg;  in zynq_qspi_init_hw()  local
189 	config_reg = 0;  in zynq_qspi_init_hw()
192 		config_reg |= ZYNQ_QSPI_LCFG_TWO_MEM;  in zynq_qspi_init_hw()
194 	zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);  in zynq_qspi_init_hw()
202 	config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);  in zynq_qspi_init_hw()
203 	config_reg &= ~(ZYNQ_QSPI_CONFIG_MSTREN_MASK |  in zynq_qspi_init_hw()
210 	config_reg |= (ZYNQ_QSPI_CONFIG_MSTREN_MASK |  in zynq_qspi_init_hw()
214 	zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);  in zynq_qspi_init_hw()
294 	u32 config_reg;  in zynq_qspi_chipselect()  local
298 		config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET);  in zynq_qspi_chipselect()
300 			config_reg &= ~ZYNQ_QSPI_LCFG_U_PAGE;  in zynq_qspi_chipselect()
302 			config_reg |= ZYNQ_QSPI_LCFG_U_PAGE;  in zynq_qspi_chipselect()
304 		zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);  in zynq_qspi_chipselect()
308 	config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);  in zynq_qspi_chipselect()
310 		config_reg &= ~ZYNQ_QSPI_CONFIG_PCS;  in zynq_qspi_chipselect()
312 		config_reg |= ZYNQ_QSPI_CONFIG_PCS;  in zynq_qspi_chipselect()
314 	zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);  in zynq_qspi_chipselect()
336 	u32 config_reg, baud_rate_val = 0;  in zynq_qspi_config_op()  local
352 	config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);  in zynq_qspi_config_op()
355 	config_reg &= (~ZYNQ_QSPI_CONFIG_CPHA_MASK) &  in zynq_qspi_config_op()
358 		config_reg |= ZYNQ_QSPI_CONFIG_CPHA_MASK;  in zynq_qspi_config_op()
360 		config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK;  in zynq_qspi_config_op()
362 	config_reg &= ~ZYNQ_QSPI_CONFIG_BDRATE_MASK;  in zynq_qspi_config_op()
363 	config_reg |= (baud_rate_val << ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT);  in zynq_qspi_config_op()
364 	zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);  in zynq_qspi_config_op()