Lines Matching +full:fifo +full:- +full:watermark +full:- +full:aligned
1 // SPDX-License-Identifier: GPL-2.0
5 * High-speed serial driver for NVIDIA Tegra SoCs
7 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
16 #include <linux/dma-mapping.h>
57 * Tx fifo trigger level setting in tegra uart is in
80 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
81 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
155 return readl(tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_read()
161 writel(val, tup->uport.membase + (reg << tup->uport.regshift)); in tegra_uart_write()
174 * RI - Ring detector is active in tegra_uart_get_mctrl()
175 * CD/DCD/CAR - Carrier detect is always active. For some reason in tegra_uart_get_mctrl()
177 * DSR - Data Set ready is active as the hardware doesn't support it. in tegra_uart_get_mctrl()
179 * CTS - Clear to send. Always set to active, as the hardware handles in tegra_uart_get_mctrl()
182 if (tup->enable_modem_interrupt) in tegra_uart_get_mctrl()
191 mcr = tup->mcr_shadow; in set_rts()
196 if (mcr != tup->mcr_shadow) { in set_rts()
198 tup->mcr_shadow = mcr; in set_rts()
206 mcr = tup->mcr_shadow; in set_dtr()
211 if (mcr != tup->mcr_shadow) { in set_dtr()
213 tup->mcr_shadow = mcr; in set_dtr()
219 unsigned long mcr = tup->mcr_shadow; in set_loopbk()
226 if (mcr != tup->mcr_shadow) { in set_loopbk()
228 tup->mcr_shadow = mcr; in set_loopbk()
237 tup->rts_active = !!(mctrl & TIOCM_RTS); in tegra_uart_set_mctrl()
238 set_rts(tup, tup->rts_active); in tegra_uart_set_mctrl()
252 lcr = tup->lcr_shadow; in tegra_uart_break_ctl()
258 tup->lcr_shadow = lcr; in tegra_uart_break_ctl()
273 if (tup->current_baud) in tegra_uart_wait_cycle_time()
274 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16)); in tegra_uart_wait_cycle_time()
277 /* Wait for a symbol-time. */
281 if (tup->current_baud) in tegra_uart_wait_sym_time()
282 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000, in tegra_uart_wait_sym_time()
283 tup->current_baud)); in tegra_uart_wait_sym_time()
296 } while (--tmout); in tegra_uart_wait_fifo_mode_enabled()
298 return -ETIMEDOUT; in tegra_uart_wait_fifo_mode_enabled()
303 unsigned long fcr = tup->fcr_shadow; in tegra_uart_fifo_reset()
306 if (tup->rts_active) in tegra_uart_fifo_reset()
309 if (tup->cdata->allow_txfifo_reset_fifo_mode) { in tegra_uart_fifo_reset()
320 if (tup->cdata->fifo_mode_enable_status) in tegra_uart_fifo_reset()
339 } while (--tmout); in tegra_uart_fifo_reset()
341 if (tup->rts_active) in tegra_uart_fifo_reset()
350 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) { in tegra_get_tolerance_rate()
351 if (baud >= tup->baud_tolerance[i].lower_range_baud && in tegra_get_tolerance_rate()
352 baud <= tup->baud_tolerance[i].upper_range_baud) in tegra_get_tolerance_rate()
354 tup->baud_tolerance[i].tolerance) / 10000); in tegra_get_tolerance_rate()
364 diff = ((long)(tup->configured_rate - tup->required_rate) * 10000) in tegra_check_rate_in_range()
365 / tup->required_rate; in tegra_check_rate_in_range()
366 if (diff < (tup->cdata->error_tolerance_low_range * 100) || in tegra_check_rate_in_range()
367 diff > (tup->cdata->error_tolerance_high_range * 100)) { in tegra_check_rate_in_range()
368 dev_err(tup->uport.dev, in tegra_check_rate_in_range()
370 return -EIO; in tegra_check_rate_in_range()
384 if (tup->current_baud == baud) in tegra_set_baudrate()
387 if (tup->cdata->support_clk_src_div) { in tegra_set_baudrate()
389 tup->required_rate = rate; in tegra_set_baudrate()
391 if (tup->n_adjustable_baud_rates) in tegra_set_baudrate()
394 ret = clk_set_rate(tup->uart_clk, rate); in tegra_set_baudrate()
396 dev_err(tup->uport.dev, in tegra_set_baudrate()
400 tup->configured_rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
406 rate = clk_get_rate(tup->uart_clk); in tegra_set_baudrate()
410 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_set_baudrate()
411 lcr = tup->lcr_shadow; in tegra_set_baudrate()
423 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_set_baudrate()
425 tup->current_baud = baud; in tegra_set_baudrate()
441 tup->uport.icount.overrun++; in tegra_uart_decode_rx_error()
442 dev_dbg(tup->uport.dev, "Got overrun errors\n"); in tegra_uart_decode_rx_error()
446 tup->uport.icount.parity++; in tegra_uart_decode_rx_error()
447 dev_dbg(tup->uport.dev, "Got Parity errors\n"); in tegra_uart_decode_rx_error()
450 tup->uport.icount.frame++; in tegra_uart_decode_rx_error()
451 dev_dbg(tup->uport.dev, "Got frame errors\n"); in tegra_uart_decode_rx_error()
455 * If FIFO read error without any data, reset Rx FIFO in tegra_uart_decode_rx_error()
459 if (tup->uport.ignore_status_mask & UART_LSR_BI) in tegra_uart_decode_rx_error()
462 tup->uport.icount.brk++; in tegra_uart_decode_rx_error()
463 dev_dbg(tup->uport.dev, "Got Break\n"); in tegra_uart_decode_rx_error()
465 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag); in tegra_uart_decode_rx_error()
483 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_fill_tx_fifo()
488 if (tup->cdata->tx_fifo_full_status) { in tegra_uart_fill_tx_fifo()
493 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX); in tegra_uart_fill_tx_fifo()
494 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in tegra_uart_fill_tx_fifo()
495 tup->uport.icount.tx++; in tegra_uart_fill_tx_fifo()
505 tup->tx_in_progress = TEGRA_UART_TX_PIO; in tegra_uart_start_pio_tx()
506 tup->tx_bytes = bytes; in tegra_uart_start_pio_tx()
507 tup->ier_shadow |= UART_IER_THRI; in tegra_uart_start_pio_tx()
508 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_start_pio_tx()
514 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_tx_dma_complete()
519 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_tx_dma_complete()
520 count = tup->tx_bytes_requested - state.residue; in tegra_uart_tx_dma_complete()
521 async_tx_ack(tup->tx_dma_desc); in tegra_uart_tx_dma_complete()
522 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_uart_tx_dma_complete()
523 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); in tegra_uart_tx_dma_complete()
524 tup->tx_in_progress = 0; in tegra_uart_tx_dma_complete()
526 uart_write_wakeup(&tup->uport); in tegra_uart_tx_dma_complete()
528 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_uart_tx_dma_complete()
534 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_tx_dma()
537 tup->tx_bytes = count & ~(0xF); in tegra_uart_start_tx_dma()
538 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail; in tegra_uart_start_tx_dma()
540 dma_sync_single_for_device(tup->uport.dev, tx_phys_addr, in tegra_uart_start_tx_dma()
541 tup->tx_bytes, DMA_TO_DEVICE); in tegra_uart_start_tx_dma()
543 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan, in tegra_uart_start_tx_dma()
544 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV, in tegra_uart_start_tx_dma()
546 if (!tup->tx_dma_desc) { in tegra_uart_start_tx_dma()
547 dev_err(tup->uport.dev, "Not able to get desc for Tx\n"); in tegra_uart_start_tx_dma()
548 return -EIO; in tegra_uart_start_tx_dma()
551 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete; in tegra_uart_start_tx_dma()
552 tup->tx_dma_desc->callback_param = tup; in tegra_uart_start_tx_dma()
553 tup->tx_in_progress = TEGRA_UART_TX_DMA; in tegra_uart_start_tx_dma()
554 tup->tx_bytes_requested = tup->tx_bytes; in tegra_uart_start_tx_dma()
555 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc); in tegra_uart_start_tx_dma()
556 dma_async_issue_pending(tup->tx_dma_chan); in tegra_uart_start_tx_dma()
564 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_start_next_tx()
566 if (!tup->current_baud) in tegra_uart_start_next_tx()
569 tail = (unsigned long)&xmit->buf[xmit->tail]; in tegra_uart_start_next_tx()
570 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); in tegra_uart_start_next_tx()
574 if (tup->use_tx_pio || count < TEGRA_UART_MIN_DMA) in tegra_uart_start_next_tx()
582 /* Called by serial core driver with u->lock taken. */
586 struct circ_buf *xmit = &u->state->xmit; in tegra_uart_start_tx()
588 if (!uart_circ_empty(xmit) && !tup->tx_in_progress) in tegra_uart_start_tx()
598 spin_lock_irqsave(&u->lock, flags); in tegra_uart_tx_empty()
599 if (!tup->tx_in_progress) { in tegra_uart_tx_empty()
604 spin_unlock_irqrestore(&u->lock, flags); in tegra_uart_tx_empty()
611 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_stop_tx()
615 if (tup->tx_in_progress != TEGRA_UART_TX_DMA) in tegra_uart_stop_tx()
618 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_stop_tx()
619 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); in tegra_uart_stop_tx()
620 count = tup->tx_bytes_requested - state.residue; in tegra_uart_stop_tx()
621 async_tx_ack(tup->tx_dma_desc); in tegra_uart_stop_tx()
622 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); in tegra_uart_stop_tx()
623 tup->tx_in_progress = 0; in tegra_uart_stop_tx()
628 struct circ_buf *xmit = &tup->uport.state->xmit; in tegra_uart_handle_tx_pio()
630 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes); in tegra_uart_handle_tx_pio()
631 tup->tx_in_progress = 0; in tegra_uart_handle_tx_pio()
633 uart_write_wakeup(&tup->uport); in tegra_uart_handle_tx_pio()
654 tup->uport.icount.rx++; in tegra_uart_handle_rx_pio()
656 if (uart_handle_sysrq_char(&tup->uport, ch)) in tegra_uart_handle_rx_pio()
659 if (tup->uport.ignore_status_mask & UART_LSR_DR) in tegra_uart_handle_rx_pio()
676 tup->uport.icount.rx += count; in tegra_uart_copy_rx_to_tty()
678 if (tup->uport.ignore_status_mask & UART_LSR_DR) in tegra_uart_copy_rx_to_tty()
681 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
684 ((unsigned char *)(tup->rx_dma_buf_virt)), count); in tegra_uart_copy_rx_to_tty()
687 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n"); in tegra_uart_copy_rx_to_tty()
689 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys, in tegra_uart_copy_rx_to_tty()
695 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); in do_handle_rx_pio()
696 struct tty_port *port = &tup->uport.state->port; in do_handle_rx_pio()
708 struct tty_port *port = &tup->uport.state->port; in tegra_uart_rx_buffer_push()
711 async_tx_ack(tup->rx_dma_desc); in tegra_uart_rx_buffer_push()
712 count = tup->rx_bytes_requested - residue; in tegra_uart_rx_buffer_push()
723 struct uart_port *u = &tup->uport; in tegra_uart_rx_dma_complete()
728 spin_lock_irqsave(&u->lock, flags); in tegra_uart_rx_dma_complete()
730 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_rx_dma_complete()
733 dev_dbg(tup->uport.dev, "RX DMA is in progress\n"); in tegra_uart_rx_dma_complete()
738 if (tup->rts_active) in tegra_uart_rx_dma_complete()
741 tup->rx_dma_active = false; in tegra_uart_rx_dma_complete()
746 if (tup->rts_active) in tegra_uart_rx_dma_complete()
750 spin_unlock_irqrestore(&u->lock, flags); in tegra_uart_rx_dma_complete()
757 if (!tup->rx_dma_active) { in tegra_uart_terminate_rx_dma()
762 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_terminate_rx_dma()
763 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); in tegra_uart_terminate_rx_dma()
766 tup->rx_dma_active = false; in tegra_uart_terminate_rx_dma()
772 if (tup->rts_active) in tegra_uart_handle_rx_dma()
777 if (tup->rts_active) in tegra_uart_handle_rx_dma()
785 if (tup->rx_dma_active) in tegra_uart_start_rx_dma()
788 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan, in tegra_uart_start_rx_dma()
789 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM, in tegra_uart_start_rx_dma()
791 if (!tup->rx_dma_desc) { in tegra_uart_start_rx_dma()
792 dev_err(tup->uport.dev, "Not able to get desc for Rx\n"); in tegra_uart_start_rx_dma()
793 return -EIO; in tegra_uart_start_rx_dma()
796 tup->rx_dma_active = true; in tegra_uart_start_rx_dma()
797 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete; in tegra_uart_start_rx_dma()
798 tup->rx_dma_desc->callback_param = tup; in tegra_uart_start_rx_dma()
799 tup->rx_bytes_requested = count; in tegra_uart_start_rx_dma()
800 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc); in tegra_uart_start_rx_dma()
801 dma_async_issue_pending(tup->rx_dma_chan); in tegra_uart_start_rx_dma()
815 tup->uport.icount.rng++; in tegra_uart_handle_modem_signal_change()
817 tup->uport.icount.dsr++; in tegra_uart_handle_modem_signal_change()
820 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD); in tegra_uart_handle_modem_signal_change()
823 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS); in tegra_uart_handle_modem_signal_change()
829 struct uart_port *u = &tup->uport; in tegra_uart_isr()
836 spin_lock_irqsave(&u->lock, flags); in tegra_uart_isr()
840 if (!tup->use_rx_pio && is_rx_int) { in tegra_uart_isr()
842 if (tup->rx_in_progress) { in tegra_uart_isr()
843 ier = tup->ier_shadow; in tegra_uart_isr()
846 tup->ier_shadow = ier; in tegra_uart_isr()
852 spin_unlock_irqrestore(&u->lock, flags); in tegra_uart_isr()
862 tup->ier_shadow &= ~UART_IER_THRI; in tegra_uart_isr()
863 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_isr()
869 if (!tup->use_rx_pio) { in tegra_uart_isr()
870 is_rx_int = tup->rx_in_progress; in tegra_uart_isr()
872 ier = tup->ier_shadow; in tegra_uart_isr()
875 tup->ier_shadow = ier; in tegra_uart_isr()
881 if (!tup->use_rx_pio) { in tegra_uart_isr()
882 is_rx_start = tup->rx_in_progress; in tegra_uart_isr()
883 tup->ier_shadow &= ~UART_IER_RDI; in tegra_uart_isr()
884 tegra_uart_write(tup, tup->ier_shadow, in tegra_uart_isr()
906 struct tty_port *port = &tup->uport.state->port; in tegra_uart_stop_rx()
909 if (tup->rts_active) in tegra_uart_stop_rx()
912 if (!tup->rx_in_progress) in tegra_uart_stop_rx()
917 ier = tup->ier_shadow; in tegra_uart_stop_rx()
920 tup->ier_shadow = ier; in tegra_uart_stop_rx()
922 tup->rx_in_progress = 0; in tegra_uart_stop_rx()
924 if (!tup->use_rx_pio) in tegra_uart_stop_rx()
933 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud); in tegra_uart_hw_deinit()
934 unsigned long fifo_empty_time = tup->uport.fifosize * char_time; in tegra_uart_hw_deinit()
948 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
949 "Tx Fifo not empty, CTS disabled, waiting\n"); in tegra_uart_hw_deinit()
951 /* Wait for Tx fifo to be empty */ in tegra_uart_hw_deinit()
955 fifo_empty_time -= wait_time; in tegra_uart_hw_deinit()
961 dev_err(tup->uport.dev, in tegra_uart_hw_deinit()
969 spin_lock_irqsave(&tup->uport.lock, flags); in tegra_uart_hw_deinit()
972 tup->current_baud = 0; in tegra_uart_hw_deinit()
973 spin_unlock_irqrestore(&tup->uport.lock, flags); in tegra_uart_hw_deinit()
975 tup->rx_in_progress = 0; in tegra_uart_hw_deinit()
976 tup->tx_in_progress = 0; in tegra_uart_hw_deinit()
978 if (!tup->use_rx_pio) in tegra_uart_hw_deinit()
980 if (!tup->use_tx_pio) in tegra_uart_hw_deinit()
983 clk_disable_unprepare(tup->uart_clk); in tegra_uart_hw_deinit()
990 tup->fcr_shadow = 0; in tegra_uart_hw_init()
991 tup->mcr_shadow = 0; in tegra_uart_hw_init()
992 tup->lcr_shadow = 0; in tegra_uart_hw_init()
993 tup->ier_shadow = 0; in tegra_uart_hw_init()
994 tup->current_baud = 0; in tegra_uart_hw_init()
996 clk_prepare_enable(tup->uart_clk); in tegra_uart_hw_init()
999 reset_control_assert(tup->rst); in tegra_uart_hw_init()
1001 reset_control_deassert(tup->rst); in tegra_uart_hw_init()
1003 tup->rx_in_progress = 0; in tegra_uart_hw_init()
1004 tup->tx_in_progress = 0; in tegra_uart_hw_init()
1013 * interrupt is received. Rx high watermark is set to 4. in tegra_uart_hw_init()
1016 * interrupt the CPU when the number of entries in the FIFO reaches the in tegra_uart_hw_init()
1017 * low watermark. Tx low watermark is set to 16 bytes. in tegra_uart_hw_init()
1024 tup->fcr_shadow = UART_FCR_ENABLE_FIFO; in tegra_uart_hw_init()
1026 if (tup->use_rx_pio) { in tegra_uart_hw_init()
1027 tup->fcr_shadow |= UART_FCR_R_TRIG_11; in tegra_uart_hw_init()
1029 if (tup->cdata->max_dma_burst_bytes == 8) in tegra_uart_hw_init()
1030 tup->fcr_shadow |= UART_FCR_R_TRIG_10; in tegra_uart_hw_init()
1032 tup->fcr_shadow |= UART_FCR_R_TRIG_01; in tegra_uart_hw_init()
1035 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; in tegra_uart_hw_init()
1036 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1041 if (tup->cdata->fifo_mode_enable_status) { in tegra_uart_hw_init()
1044 dev_err(tup->uport.dev, in tegra_uart_hw_init()
1045 "Failed to enable FIFO mode: %d\n", ret); in tegra_uart_hw_init()
1052 * periods after enabling the TX fifo, otherwise data could in tegra_uart_hw_init()
1065 dev_err(tup->uport.dev, "Failed to set baud rate\n"); in tegra_uart_hw_init()
1068 if (!tup->use_rx_pio) { in tegra_uart_hw_init()
1069 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; in tegra_uart_hw_init()
1070 tup->fcr_shadow |= UART_FCR_DMA_SELECT; in tegra_uart_hw_init()
1071 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1073 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); in tegra_uart_hw_init()
1075 tup->rx_in_progress = 1; in tegra_uart_hw_init()
1081 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when in tegra_uart_hw_init()
1082 * the DATA is sitting in the FIFO and couldn't be transferred to the in tegra_uart_hw_init()
1087 * For pauses in the data which is not aligned to 4 bytes, we get in tegra_uart_hw_init()
1088 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first in tegra_uart_hw_init()
1091 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | UART_IER_RDI; in tegra_uart_hw_init()
1097 if (!tup->use_rx_pio) in tegra_uart_hw_init()
1098 tup->ier_shadow |= TEGRA_UART_IER_EORD; in tegra_uart_hw_init()
1100 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_hw_init()
1108 dmaengine_terminate_all(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
1109 dma_release_channel(tup->rx_dma_chan); in tegra_uart_dma_channel_free()
1110 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE, in tegra_uart_dma_channel_free()
1111 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys); in tegra_uart_dma_channel_free()
1112 tup->rx_dma_chan = NULL; in tegra_uart_dma_channel_free()
1113 tup->rx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
1114 tup->rx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
1116 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
1117 dma_release_channel(tup->tx_dma_chan); in tegra_uart_dma_channel_free()
1118 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys, in tegra_uart_dma_channel_free()
1120 tup->tx_dma_chan = NULL; in tegra_uart_dma_channel_free()
1121 tup->tx_dma_buf_phys = 0; in tegra_uart_dma_channel_free()
1122 tup->tx_dma_buf_virt = NULL; in tegra_uart_dma_channel_free()
1135 dma_chan = dma_request_chan(tup->uport.dev, dma_to_memory ? "rx" : "tx"); in tegra_uart_dma_channel_allocate()
1138 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1144 dma_buf = dma_alloc_coherent(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1148 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1151 return -ENOMEM; in tegra_uart_dma_channel_allocate()
1153 dma_sync_single_for_device(tup->uport.dev, dma_phys, in tegra_uart_dma_channel_allocate()
1156 dma_sconfig.src_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
1158 dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes; in tegra_uart_dma_channel_allocate()
1159 tup->rx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
1160 tup->rx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
1161 tup->rx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
1163 dma_phys = dma_map_single(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1164 tup->uport.state->xmit.buf, UART_XMIT_SIZE, in tegra_uart_dma_channel_allocate()
1166 if (dma_mapping_error(tup->uport.dev, dma_phys)) { in tegra_uart_dma_channel_allocate()
1167 dev_err(tup->uport.dev, "dma_map_single tx failed\n"); in tegra_uart_dma_channel_allocate()
1169 return -ENOMEM; in tegra_uart_dma_channel_allocate()
1171 dma_buf = tup->uport.state->xmit.buf; in tegra_uart_dma_channel_allocate()
1172 dma_sconfig.dst_addr = tup->uport.mapbase; in tegra_uart_dma_channel_allocate()
1175 tup->tx_dma_chan = dma_chan; in tegra_uart_dma_channel_allocate()
1176 tup->tx_dma_buf_virt = dma_buf; in tegra_uart_dma_channel_allocate()
1177 tup->tx_dma_buf_phys = dma_phys; in tegra_uart_dma_channel_allocate()
1182 dev_err(tup->uport.dev, in tegra_uart_dma_channel_allocate()
1196 if (!tup->use_tx_pio) { in tegra_uart_startup()
1199 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", in tegra_uart_startup()
1205 if (!tup->use_rx_pio) { in tegra_uart_startup()
1208 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", in tegra_uart_startup()
1216 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret); in tegra_uart_startup()
1220 ret = request_irq(u->irq, tegra_uart_isr, 0, in tegra_uart_startup()
1221 dev_name(u->dev), tup); in tegra_uart_startup()
1223 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq); in tegra_uart_startup()
1229 if (!tup->use_rx_pio) in tegra_uart_startup()
1232 if (!tup->use_tx_pio) in tegra_uart_startup()
1245 tup->tx_bytes = 0; in tegra_uart_flush_buffer()
1246 if (tup->tx_dma_chan) in tegra_uart_flush_buffer()
1247 dmaengine_terminate_all(tup->tx_dma_chan); in tegra_uart_flush_buffer()
1255 free_irq(u->irq, tup); in tegra_uart_shutdown()
1262 if (tup->enable_modem_interrupt) { in tegra_uart_enable_ms()
1263 tup->ier_shadow |= UART_IER_MSI; in tegra_uart_enable_ms()
1264 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_enable_ms()
1276 struct clk *parent_clk = clk_get_parent(tup->uart_clk); in tegra_uart_set_termios()
1278 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF; in tegra_uart_set_termios()
1282 spin_lock_irqsave(&u->lock, flags); in tegra_uart_set_termios()
1285 if (tup->rts_active) in tegra_uart_set_termios()
1289 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER); in tegra_uart_set_termios()
1295 lcr = tup->lcr_shadow; in tegra_uart_set_termios()
1299 termios->c_cflag &= ~CMSPAR; in tegra_uart_set_termios()
1301 if ((termios->c_cflag & PARENB) == PARENB) { in tegra_uart_set_termios()
1303 if (termios->c_cflag & PARODD) { in tegra_uart_set_termios()
1315 switch (termios->c_cflag & CSIZE) { in tegra_uart_set_termios()
1335 if (termios->c_cflag & CSTOPB) { in tegra_uart_set_termios()
1344 tup->lcr_shadow = lcr; in tegra_uart_set_termios()
1345 tup->symb_bit = symb_bit; in tegra_uart_set_termios()
1351 spin_unlock_irqrestore(&u->lock, flags); in tegra_uart_set_termios()
1354 dev_err(tup->uport.dev, "Failed to set baud rate\n"); in tegra_uart_set_termios()
1359 spin_lock_irqsave(&u->lock, flags); in tegra_uart_set_termios()
1362 if (termios->c_cflag & CRTSCTS) { in tegra_uart_set_termios()
1363 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1364 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1365 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1367 if (tup->rts_active) in tegra_uart_set_termios()
1370 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN; in tegra_uart_set_termios()
1371 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN; in tegra_uart_set_termios()
1372 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR); in tegra_uart_set_termios()
1376 uart_update_timeout(u, termios->c_cflag, baud); in tegra_uart_set_termios()
1381 /* Re-enable interrupt */ in tegra_uart_set_termios()
1382 tegra_uart_write(tup, tup->ier_shadow, UART_IER); in tegra_uart_set_termios()
1385 tup->uport.ignore_status_mask = 0; in tegra_uart_set_termios()
1387 if ((termios->c_cflag & CREAD) == 0) in tegra_uart_set_termios()
1388 tup->uport.ignore_status_mask |= UART_LSR_DR; in tegra_uart_set_termios()
1389 if (termios->c_iflag & IGNBRK) in tegra_uart_set_termios()
1390 tup->uport.ignore_status_mask |= UART_LSR_BI; in tegra_uart_set_termios()
1392 spin_unlock_irqrestore(&u->lock, flags); in tegra_uart_set_termios()
1429 struct device_node *np = pdev->dev.of_node; in tegra_uart_parse_dt()
1439 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port); in tegra_uart_parse_dt()
1442 tup->uport.line = port; in tegra_uart_parse_dt()
1444 tup->enable_modem_interrupt = of_property_read_bool(np, in tegra_uart_parse_dt()
1445 "nvidia,enable-modem-interrupt"); in tegra_uart_parse_dt()
1447 index = of_property_match_string(np, "dma-names", "rx"); in tegra_uart_parse_dt()
1449 tup->use_rx_pio = true; in tegra_uart_parse_dt()
1450 dev_info(&pdev->dev, "RX in PIO mode\n"); in tegra_uart_parse_dt()
1452 index = of_property_match_string(np, "dma-names", "tx"); in tegra_uart_parse_dt()
1454 tup->use_tx_pio = true; in tegra_uart_parse_dt()
1455 dev_info(&pdev->dev, "TX in PIO mode\n"); in tegra_uart_parse_dt()
1458 n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates"); in tegra_uart_parse_dt()
1460 tup->n_adjustable_baud_rates = n_entries / 3; in tegra_uart_parse_dt()
1461 tup->baud_tolerance = in tegra_uart_parse_dt()
1462 devm_kzalloc(&pdev->dev, (tup->n_adjustable_baud_rates) * in tegra_uart_parse_dt()
1463 sizeof(*tup->baud_tolerance), GFP_KERNEL); in tegra_uart_parse_dt()
1464 if (!tup->baud_tolerance) in tegra_uart_parse_dt()
1465 return -ENOMEM; in tegra_uart_parse_dt()
1470 "nvidia,adjust-baud-rates", in tegra_uart_parse_dt()
1473 tup->baud_tolerance[index].lower_range_baud = in tegra_uart_parse_dt()
1477 "nvidia,adjust-baud-rates", in tegra_uart_parse_dt()
1480 tup->baud_tolerance[index].upper_range_baud = in tegra_uart_parse_dt()
1484 "nvidia,adjust-baud-rates", in tegra_uart_parse_dt()
1487 tup->baud_tolerance[index].tolerance = in tegra_uart_parse_dt()
1491 tup->n_adjustable_baud_rates = 0; in tegra_uart_parse_dt()
1504 .error_tolerance_low_range = -4,
1515 .error_tolerance_low_range = -4,
1537 .error_tolerance_low_range = -2,
1543 .compatible = "nvidia,tegra30-hsuart",
1546 .compatible = "nvidia,tegra20-hsuart",
1549 .compatible = "nvidia,tegra186-hsuart",
1552 .compatible = "nvidia,tegra194-hsuart",
1568 match = of_match_device(tegra_uart_of_match, &pdev->dev); in tegra_uart_probe()
1570 dev_err(&pdev->dev, "Error: No device match found\n"); in tegra_uart_probe()
1571 return -ENODEV; in tegra_uart_probe()
1573 cdata = match->data; in tegra_uart_probe()
1575 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL); in tegra_uart_probe()
1577 dev_err(&pdev->dev, "Failed to allocate memory for tup\n"); in tegra_uart_probe()
1578 return -ENOMEM; in tegra_uart_probe()
1585 u = &tup->uport; in tegra_uart_probe()
1586 u->dev = &pdev->dev; in tegra_uart_probe()
1587 u->ops = &tegra_uart_ops; in tegra_uart_probe()
1588 u->type = PORT_TEGRA; in tegra_uart_probe()
1589 u->fifosize = 32; in tegra_uart_probe()
1590 tup->cdata = cdata; in tegra_uart_probe()
1595 dev_err(&pdev->dev, "No IO memory resource\n"); in tegra_uart_probe()
1596 return -ENODEV; in tegra_uart_probe()
1599 u->mapbase = resource->start; in tegra_uart_probe()
1600 u->membase = devm_ioremap_resource(&pdev->dev, resource); in tegra_uart_probe()
1601 if (IS_ERR(u->membase)) in tegra_uart_probe()
1602 return PTR_ERR(u->membase); in tegra_uart_probe()
1604 tup->uart_clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
1605 if (IS_ERR(tup->uart_clk)) { in tegra_uart_probe()
1606 dev_err(&pdev->dev, "Couldn't get the clock\n"); in tegra_uart_probe()
1607 return PTR_ERR(tup->uart_clk); in tegra_uart_probe()
1610 tup->rst = devm_reset_control_get_exclusive(&pdev->dev, "serial"); in tegra_uart_probe()
1611 if (IS_ERR(tup->rst)) { in tegra_uart_probe()
1612 dev_err(&pdev->dev, "Couldn't get the reset\n"); in tegra_uart_probe()
1613 return PTR_ERR(tup->rst); in tegra_uart_probe()
1616 u->iotype = UPIO_MEM32; in tegra_uart_probe()
1620 u->irq = ret; in tegra_uart_probe()
1621 u->regshift = 2; in tegra_uart_probe()
1624 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret); in tegra_uart_probe()
1633 struct uart_port *u = &tup->uport; in tegra_uart_remove()
1643 struct uart_port *u = &tup->uport; in tegra_uart_suspend()
1651 struct uart_port *u = &tup->uport; in tegra_uart_resume()
1665 .name = "serial-tegra",
1682 cdata = match->data; in tegra_uart_init()
1684 tegra_uart_driver.nr = cdata->uart_max_port; in tegra_uart_init()
1712 MODULE_ALIAS("platform:serial-tegra");