Lines Matching +full:reserved +full:- +full:channels
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
6 * Copyright(c) 2018 Intel Corporation. All rights reserved.
52 /* DMIC max. four controllers for eight microphone channels */
55 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
87 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
92 uint32_t channels; member
95 /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */
100 uint32_t channels; member
102 /* reserved for future use */
103 uint32_t reserved[13]; member
106 /* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */
138 uint16_t reserved[3]; /**< Make sure the total size is 4 bytes aligned */ member
149 * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are
150 * multi-mode capable and there may be denied mic clock frequencies between
154 * The duty cycle could be set to 48-52% if not known. Generally these
158 * The microphone clock needs to be usually about 50-80 times the used audio
178 uint32_t reserved_1; /**< Reserved */
192 /* reserved for future use */
193 uint32_t reserved[5]; member