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4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
38 * fourcc code, a Format Modifier may optionally be provided, in order to
39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
44 * Format modifiers are used in conjunction with a fourcc code, forming a
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
69 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ argument
78 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
80 /* 8 bpp Red */
81 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
87 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
88 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
94 /* 8 bpp RGB */
95 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
96 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
104 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian…
105 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian…
106 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian…
107 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian…
114 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian…
115 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian…
116 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian…
117 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian…
127 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian…
128 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian…
129 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian…
130 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian…
132 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian…
133 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian…
134 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian…
135 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian…
142 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little …
143 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little …
144 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little …
145 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little …
149 * IEEE 754-2008 binary16 half-precision float
155 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 litt…
156 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 litt…
159 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little end…
160 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little end…
161 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little end…
162 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little end…
164 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian …
165 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endi…
166 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
167 …010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only …
171 * 16-xx padding occupy lsb
179 * 16-xx padding occupy lsb except Y410
181 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 litt…
182 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12…
183 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 lit…
187 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 lit…
191 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
193 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
195 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
204 * 1-plane YUV 4:2:0
207 * These formats can only be used with a non-Linear modifier.
209 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
213 * 2 plane RGB + A
215 * index 1 = A plane, [7:0] A
217 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
218 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
219 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
220 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
221 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
222 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
223 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
224 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
237 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
238 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
274 /* 3 plane non-subsampled (444) YCbCr
282 /* 3 plane non-subsampled (444) YCrCb
307 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) plane…
308 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) plane…
314 * Format modifiers describe, typically, a re-ordering or modification
315 * of the data in a plane of an FB. This can be used to express tiled/
316 * swizzled formats, or compression, or a combination of the two.
318 * The upper 8 bits of the format modifier are a vendor-id as assigned
338 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
346 * When adding a new token please document the layout with a code comment,
352 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
354 * compatibility, in cases where a vendor-specific definition already exists and
355 * a generic name for it is desired, the common name is a purely symbolic alias
359 * generic layouts (such as pixel re-ordering), which may have
360 * independently-developed support across multiple vendors.
362 * In future cases where a generic layout is identified before merging with a
363 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
366 * apply to a single vendor.
379 * This modifier can be used as a sentinel to terminate the format modifiers
380 * list, or to initialize a variable with an invalid modifier. It might also be
390 * which tells the driver to also take driver-internal information into account
391 * and so might actually result in a tiled framebuffer.
398 * Intel X-tiling layout
400 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
401 * in row-major layout. Within the tile bytes are laid out row-major, with
402 * a platform-dependent stride. On top of that the memory can apply
403 * platform-depending swizzling of some higher address bits into bit6.
405 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
407 * cross-driver sharing. It exists since on a given platform it does uniquely
408 * identify the layout in a simple way for i915-specific userspace, which
415 * Intel Y-tiling layout
417 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
418 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
419 * chunks column-major, with a platform-dependent height. On top of that the
420 * memory can apply platform-depending swizzling of some higher address bits
423 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
425 * cross-driver sharing. It exists since on a given platform it does uniquely
426 * identify the layout in a simple way for i915-specific userspace, which
433 * Intel Yf-tiling layout
435 * This is a tiled layout using 4Kb tiles in row-major layout.
436 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
437 * are arranged in four groups (two wide, two high) with column-major layout.
439 * out as 2x2 column-major.
441 * either a square block or a 2:1 unit.
450 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
451 * The main surface will be plane index 0 and must be Y/Yf-tiled,
454 * Each CCS tile matches a 1024x512 pixel area of the main surface.
459 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
460 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
468 * Intel color control surfaces (CCS) for Gen-12 render compression.
470 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
471 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
472 * main surface. In other words, 4 bits in CCS map to a main surface cache
473 * line pair. The main surface pitch is required to be a multiple of four
474 * Y-tile widths.
479 * Intel color control surfaces (CCS) for Gen-12 media compression
481 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
482 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
483 * main surface. In other words, 4 bits in CCS map to a main surface cache
484 * line pair. The main surface pitch is required to be a multiple of four
485 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
492 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
494 * Macroblocks are laid in a Z-shape, and each pixel data is following the
499 * - multiple of 128 pixels for the width
500 * - multiple of 32 pixels for the height
502 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
507 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
509 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
510 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
518 * Refers to a compressed variant of the base format that is compressed.
519 * Implementation may be platform and base-format specific.
533 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
539 * Vivante 64x64 super-tiling layout
541 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
542 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
546 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
551 * Vivante 4x4 tiling layout for dual-pipe
553 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
555 * compared to the non-split tiled layout.
560 * Vivante 64x64 super-tiling layout for dual-pipe
562 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
563 * starts at a different base address. Offsets from the base addresses are
564 * therefore halved compared to the non-split super-tiled layout.
583 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
585 * a block depth or height of "4").
592 * ---- ----- -----------------------------------------------------------------
596 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
598 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
600 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
602 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
606 * hardware support a block width of two gobs, but it is impractical
610 * 11:9 - Reserved (To support 2D-array textures with variable array stride
614 * 19:12 k Page Kind. This value directly maps to a field in the page
627 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
631 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
632 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
633 * 2 = Gob Height 8, Turing+ Page Kind mapping
636 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
642 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
658 * 55:25 - Reserved for future use. Must be zero.
670 * with block-linear layouts, is remapped within drivers to the value 0xfe,
671 * which corresponds to the "generic" kind used for simple single-sample
672 * uncompressed color formats on Fermi - Volta GPUs.
687 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
689 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
723 * type, and the next 24 bits for parameters. Top 8 bits are the
726 #define __fourcc_mod_broadcom_param_shift 8
732 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
734 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
743 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
746 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
749 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
753 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
754 * tiles) or right-to-left (odd rows of 4k tiles).
777 * and UV. Some SAND-using hardware stores UV in a separate tiled
816 * necessary to reduce the padding. If a hardware block can't do XOR,
817 * the assumption is that a no-XOR tiling modifier will be created.
824 * AFBC is a proprietary lossless image compression protocol and format.
825 * It provides fine-grained random access and minimizes the amount of data
830 * and different devices or use-cases may support different combinations.
839 * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
855 * size (in pixels) must be aligned to a multiple of the superblock size.
862 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
879 * AFBC block-split
882 * half of the payload is positioned at a predefined offset from the start
890 * This flag indicates that the payload of each superblock must be stored at a
900 * AFBC copy-block restrict
902 * Buffers with this flag must obey the copy-block restriction. The restriction
903 * is such that there are no copy-blocks referring across the border of 8x8
904 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
911 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
912 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
918 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
923 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
924 * can be reduced if a whole superblock is a single color.
929 * AFBC double-buffer
931 * Indicates that the buffer is allocated in a layout safe for front-buffer
939 * Indicates that the buffer includes per-superblock content hints.
949 * affects the storage mode of the individual superblocks. Note that even a
956 * Arm 16x16 Block U-Interleaved modifier
969 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
975 * both in row-major order.
982 * Amlogic uses a proprietary lossless image compression protocol and format
989 * The underlying storage is considered to be 3 components, 8bit or 10-bit
991 * - DRM_FORMAT_YUV420_8BIT
992 * - DRM_FORMAT_YUV420_10BIT
994 * The first 8 bits of the mode defines the layout, then the following 8 bits
1001 #define __fourcc_mod_amlogic_options_shift 8
1016 * - a body content organized in 64x32 superblocks with 4096 bytes per
1018 * - a 32 bytes per 128x64 header block
1036 * be accessible by the user-space clients, but only accessible by the
1039 * The user-space clients should expect a failure while trying to mmap
1040 * the DMA-BUF handle returned by the producer.
1050 * boudaries, i.e. 8bit should be stored in this mode to save allocation