Lines Matching full:dmic
719 * DMIC CLK = 256 * fs / 12 in rt5677_set_vad_source()
1078 * set_dmic_clk - Set parameter of dmic.
1084 * Choose dmic clock between 1MHz and 3MHz.
1098 dev_err(component->dev, "Failed to set DMIC clock\n"); in set_dmic_clk()
1883 "DD MIX1", "DMIC", "Stereo DAC MIX"
1907 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1917 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1924 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1931 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1938 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1945 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1952 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1994 "DD MIX1L", "DMIC", "MONO DAC MIXL"
2018 "DD MIX1R", "DMIC", "MONO DAC MIXR"
2042 "DD MIX1", "DMIC", "DD MIX2"
2801 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2803 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2805 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2807 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2809 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2811 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2829 SND_SOC_DAPM_INPUT("DMIC L1"),
2830 SND_SOC_DAPM_INPUT("DMIC R1"),
2831 SND_SOC_DAPM_INPUT("DMIC L2"),
2832 SND_SOC_DAPM_INPUT("DMIC R2"),
2833 SND_SOC_DAPM_INPUT("DMIC L3"),
2834 SND_SOC_DAPM_INPUT("DMIC R3"),
2835 SND_SOC_DAPM_INPUT("DMIC L4"),
2836 SND_SOC_DAPM_INPUT("DMIC R4"),
2859 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2887 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2893 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2901 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2907 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2913 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2915 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
3344 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3345 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3346 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3347 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3348 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3349 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
3369 { "DMIC1", NULL, "DMIC L1" },
3370 { "DMIC1", NULL, "DMIC R1" },
3371 { "DMIC2", NULL, "DMIC L2" },
3372 { "DMIC2", NULL, "DMIC R2" },
3373 { "DMIC3", NULL, "DMIC L3" },
3374 { "DMIC3", NULL, "DMIC R3" },
3375 { "DMIC4", NULL, "DMIC L4" },
3376 { "DMIC4", NULL, "DMIC R4" },
3378 { "DMIC L1", NULL, "DMIC CLK" },
3379 { "DMIC R1", NULL, "DMIC CLK" },
3380 { "DMIC L2", NULL, "DMIC CLK" },
3381 { "DMIC R2", NULL, "DMIC CLK" },
3382 { "DMIC L3", NULL, "DMIC CLK" },
3383 { "DMIC R3", NULL, "DMIC CLK" },
3384 { "DMIC L4", NULL, "DMIC CLK" },
3385 { "DMIC R4", NULL, "DMIC CLK" },
3387 { "DMIC L1", NULL, "DMIC1 power" },
3388 { "DMIC R1", NULL, "DMIC1 power" },
3389 { "DMIC L3", NULL, "DMIC3 power" },
3390 { "DMIC R3", NULL, "DMIC3 power" },
3391 { "DMIC L4", NULL, "DMIC4 power" },
3392 { "DMIC R4", NULL, "DMIC4 power" },
3411 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3412 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3413 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3414 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3416 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3417 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3418 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3419 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3421 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3422 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3423 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3424 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3426 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3427 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3428 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3429 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3431 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3432 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3433 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3434 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3436 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3437 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3438 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3439 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3449 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3457 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3465 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3473 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3477 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3489 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
4158 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
4159 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
4160 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
4161 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
4280 { "DMIC L2", NULL, "DMIC1 power" },
4281 { "DMIC R2", NULL, "DMIC1 power" },
4285 { "DMIC L2", NULL, "DMIC2 power" },
4286 { "DMIC R2", NULL, "DMIC2 power" },