Lines Matching +full:asrc +full:- +full:format
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/dma-mapping.h>
32 #include "imx-pcm.h"
51 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_iec958_put_bits()
53 (struct soc_mreg_control *)kcontrol->private_value; in fsl_easrc_iec958_put_bits()
54 unsigned int regval = ucontrol->value.integer.value[0]; in fsl_easrc_iec958_put_bits()
56 easrc_priv->bps_iec958[mc->regbase] = regval; in fsl_easrc_iec958_put_bits()
66 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_iec958_get_bits()
68 (struct soc_mreg_control *)kcontrol->private_value; in fsl_easrc_iec958_get_bits()
70 ucontrol->value.enumerated.item[0] = easrc_priv->bps_iec958[mc->regbase]; in fsl_easrc_iec958_get_bits()
80 (struct soc_mreg_control *)kcontrol->private_value; in fsl_easrc_get_reg()
83 regval = snd_soc_component_read(component, mc->regbase); in fsl_easrc_get_reg()
85 ucontrol->value.integer.value[0] = regval; in fsl_easrc_get_reg()
95 (struct soc_mreg_control *)kcontrol->private_value; in fsl_easrc_set_reg()
96 unsigned int regval = ucontrol->value.integer.value[0]; in fsl_easrc_set_reg()
99 ret = snd_soc_component_write(component, mc->regbase, regval); in fsl_easrc_set_reg()
174 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_set_rs_ratio()
175 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_set_rs_ratio()
176 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; in fsl_easrc_set_rs_ratio()
177 unsigned int in_rate = ctx_priv->in_params.norm_rate; in fsl_easrc_set_rs_ratio()
178 unsigned int out_rate = ctx_priv->out_params.norm_rate; in fsl_easrc_set_rs_ratio()
183 switch (easrc_priv->rs_num_taps) { in fsl_easrc_set_rs_ratio()
197 return -EINVAL; in fsl_easrc_set_rs_ratio()
205 dev_err(&easrc->pdev->dev, "ratio exceed range\n"); in fsl_easrc_set_rs_ratio()
206 return -EINVAL; in fsl_easrc_set_rs_ratio()
209 regmap_write(easrc->regmap, REG_EASRC_RRL(ctx->index), in fsl_easrc_set_rs_ratio()
211 regmap_write(easrc->regmap, REG_EASRC_RRH(ctx->index), in fsl_easrc_set_rs_ratio()
226 ctx_priv = ctx->private; in fsl_easrc_normalize_rates()
228 a = ctx_priv->in_params.sample_rate; in fsl_easrc_normalize_rates()
229 b = ctx_priv->out_params.sample_rate; in fsl_easrc_normalize_rates()
234 ctx_priv->in_params.norm_rate = ctx_priv->in_params.sample_rate / a; in fsl_easrc_normalize_rates()
235 ctx_priv->out_params.norm_rate = ctx_priv->out_params.sample_rate / a; in fsl_easrc_normalize_rates()
246 return -ENODEV; in fsl_easrc_coeff_mem_ptr_reset()
248 dev = &easrc->pdev->dev; in fsl_easrc_coeff_mem_ptr_reset()
255 return -EINVAL; in fsl_easrc_coeff_mem_ptr_reset()
270 return -EINVAL; in fsl_easrc_coeff_mem_ptr_reset()
278 regmap_update_bits(easrc->regmap, reg, mask, 0); in fsl_easrc_coeff_mem_ptr_reset()
279 regmap_update_bits(easrc->regmap, reg, mask, val); in fsl_easrc_coeff_mem_ptr_reset()
280 regmap_update_bits(easrc->regmap, reg, mask, 0); in fsl_easrc_coeff_mem_ptr_reset()
301 struct device *dev = &easrc->pdev->dev; in fsl_easrc_resampler_config()
302 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_resampler_config()
303 struct asrc_firmware_hdr *hdr = easrc_priv->firmware_hdr; in fsl_easrc_resampler_config()
304 struct interp_params *interp = easrc_priv->interp; in fsl_easrc_resampler_config()
314 return -ENODEV; in fsl_easrc_resampler_config()
317 for (i = 0; i < hdr->interp_scen; i++) { in fsl_easrc_resampler_config()
318 if ((interp[i].num_taps - 1) != in fsl_easrc_resampler_config()
319 bits_taps_to_val(easrc_priv->rs_num_taps)) in fsl_easrc_resampler_config()
324 dev_dbg(dev, "Selected interp_filter: %u taps - %u phases\n", in fsl_easrc_resampler_config()
325 selected_interp->num_taps, in fsl_easrc_resampler_config()
326 selected_interp->num_phases); in fsl_easrc_resampler_config()
332 return -EINVAL; in fsl_easrc_resampler_config()
336 * RS_LOW - first half of center tap of the sinc function in fsl_easrc_resampler_config()
337 * RS_HIGH - second half of center tap of the sinc function in fsl_easrc_resampler_config()
339 * symetrical - i.e. odd number of taps in fsl_easrc_resampler_config()
341 r = (uint32_t *)&selected_interp->center_tap; in fsl_easrc_resampler_config()
342 regmap_write(easrc->regmap, REG_EASRC_RCTCL, EASRC_RCTCL_RS_CL(r[0])); in fsl_easrc_resampler_config()
343 regmap_write(easrc->regmap, REG_EASRC_RCTCH, EASRC_RCTCH_RS_CH(r[1])); in fsl_easrc_resampler_config()
347 * 00b - 32-Tap Resampling Filter in fsl_easrc_resampler_config()
348 * 01b - 64-Tap Resampling Filter in fsl_easrc_resampler_config()
349 * 10b - 128-Tap Resampling Filter in fsl_easrc_resampler_config()
350 * 11b - N/A in fsl_easrc_resampler_config()
352 regmap_update_bits(easrc->regmap, REG_EASRC_CRCC, in fsl_easrc_resampler_config()
354 EASRC_CRCC_RS_TAPS(easrc_priv->rs_num_taps)); in fsl_easrc_resampler_config()
363 * 32-tap mode, 16-taps, 128-phases 4-coefficients per phase in fsl_easrc_resampler_config()
364 * 64-tap mode, 32-taps, 64-phases 4-coefficients per phase in fsl_easrc_resampler_config()
365 * 128-tap mode, 64-taps, 32-phases 4-coefficients per phase in fsl_easrc_resampler_config()
373 regmap_write(easrc->regmap, REG_EASRC_CRCM, in fsl_easrc_resampler_config()
375 regmap_write(easrc->regmap, REG_EASRC_CRCM, in fsl_easrc_resampler_config()
384 * For input float32 normalized range (1.0,-1.0) -> output int[16,24,32]:
386 * For input int[16, 24, 32] -> output float32
387 * scale it by multiplying filter coefficients by 2^-15, 2^-23, 2^-31
390 * @infilter : Pointer to non-scaled input filter
400 struct device *dev = &easrc->pdev->dev; in fsl_easrc_normalize_filter()
419 return -EINVAL; in fsl_easrc_normalize_filter()
431 struct device *dev = &easrc->pdev->dev; in fsl_easrc_write_pf_coeff_mem()
443 return -EINVAL; in fsl_easrc_write_pf_coeff_mem()
460 regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id), in fsl_easrc_write_pf_coeff_mem()
462 regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id), in fsl_easrc_write_pf_coeff_mem()
483 return -ENODEV; in fsl_easrc_prefilter_config()
485 dev = &easrc->pdev->dev; in fsl_easrc_prefilter_config()
489 return -EINVAL; in fsl_easrc_prefilter_config()
492 easrc_priv = easrc->private; in fsl_easrc_prefilter_config()
494 ctx = easrc->pair[ctx_id]; in fsl_easrc_prefilter_config()
495 ctx_priv = ctx->private; in fsl_easrc_prefilter_config()
497 in_s_rate = ctx_priv->in_params.sample_rate; in fsl_easrc_prefilter_config()
498 out_s_rate = ctx_priv->out_params.sample_rate; in fsl_easrc_prefilter_config()
499 in_s_fmt = ctx_priv->in_params.sample_format; in fsl_easrc_prefilter_config()
500 out_s_fmt = ctx_priv->out_params.sample_format; in fsl_easrc_prefilter_config()
502 ctx_priv->in_filled_sample = bits_taps_to_val(easrc_priv->rs_num_taps) / 2; in fsl_easrc_prefilter_config()
503 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate; in fsl_easrc_prefilter_config()
505 ctx_priv->st1_num_taps = 0; in fsl_easrc_prefilter_config()
506 ctx_priv->st2_num_taps = 0; in fsl_easrc_prefilter_config()
508 regmap_write(easrc->regmap, REG_EASRC_CCE1(ctx_id), 0); in fsl_easrc_prefilter_config()
509 regmap_write(easrc->regmap, REG_EASRC_CCE2(ctx_id), 0); in fsl_easrc_prefilter_config()
512 * The audio float point data range is (-1, 1), the asrc would output in fsl_easrc_prefilter_config()
537 * 1. Create a 1 tap filter with center tap (only tap) of 2^-31 in fsl_easrc_prefilter_config()
552 regmap_update_bits(easrc->regmap, in fsl_easrc_prefilter_config()
557 ctx_priv->st1_num_taps = 1; in fsl_easrc_prefilter_config()
558 ctx_priv->st1_coeff = &easrc_priv->const_coeff; in fsl_easrc_prefilter_config()
559 ctx_priv->st1_num_exp = 1; in fsl_easrc_prefilter_config()
560 ctx_priv->st2_num_taps = 0; in fsl_easrc_prefilter_config()
564 ctx_priv->st1_addexp = 31; in fsl_easrc_prefilter_config()
567 ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp; in fsl_easrc_prefilter_config()
569 inrate = ctx_priv->in_params.norm_rate; in fsl_easrc_prefilter_config()
570 outrate = ctx_priv->out_params.norm_rate; in fsl_easrc_prefilter_config()
572 hdr = easrc_priv->firmware_hdr; in fsl_easrc_prefilter_config()
573 prefil = easrc_priv->prefil; in fsl_easrc_prefilter_config()
575 for (i = 0; i < hdr->prefil_scen; i++) { in fsl_easrc_prefilter_config()
580 selected_prefil->insr, in fsl_easrc_prefilter_config()
581 selected_prefil->outsr, in fsl_easrc_prefilter_config()
582 selected_prefil->st1_taps, in fsl_easrc_prefilter_config()
583 selected_prefil->st2_taps); in fsl_easrc_prefilter_config()
592 return -EINVAL; in fsl_easrc_prefilter_config()
600 ctx_priv->st1_num_taps = selected_prefil->st1_taps; in fsl_easrc_prefilter_config()
601 ctx_priv->st1_coeff = selected_prefil->coeff; in fsl_easrc_prefilter_config()
602 ctx_priv->st1_num_exp = selected_prefil->st1_exp; in fsl_easrc_prefilter_config()
604 offset = ((selected_prefil->st1_taps + 1) / 2); in fsl_easrc_prefilter_config()
605 ctx_priv->st2_num_taps = selected_prefil->st2_taps; in fsl_easrc_prefilter_config()
606 ctx_priv->st2_coeff = selected_prefil->coeff + offset; in fsl_easrc_prefilter_config()
611 if (ctx_priv->st2_num_taps > 0) in fsl_easrc_prefilter_config()
612 ctx_priv->st2_addexp = 31; in fsl_easrc_prefilter_config()
614 ctx_priv->st1_addexp = 31; in fsl_easrc_prefilter_config()
617 if (ctx_priv->st2_num_taps > 0) in fsl_easrc_prefilter_config()
618 ctx_priv->st2_addexp -= ctx_priv->in_params.fmt.addexp; in fsl_easrc_prefilter_config()
620 ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp; in fsl_easrc_prefilter_config()
624 ctx_priv->in_filled_sample += (ctx_priv->st1_num_taps / 2) * ctx_priv->st1_num_exp + in fsl_easrc_prefilter_config()
625 ctx_priv->st2_num_taps / 2; in fsl_easrc_prefilter_config()
626 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate; in fsl_easrc_prefilter_config()
628 if (ctx_priv->in_filled_sample * out_s_rate % in_s_rate != 0) in fsl_easrc_prefilter_config()
629 ctx_priv->out_missed_sample += 1; in fsl_easrc_prefilter_config()
635 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id), in fsl_easrc_prefilter_config()
638 if (ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) { in fsl_easrc_prefilter_config()
640 ctx_priv->st1_num_taps, EASRC_MAX_PF_TAPS); in fsl_easrc_prefilter_config()
641 ret = -EINVAL; in fsl_easrc_prefilter_config()
646 regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id), in fsl_easrc_prefilter_config()
648 EASRC_CCE2_ST1_TAPS(ctx_priv->st1_num_taps - 1)); in fsl_easrc_prefilter_config()
651 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), in fsl_easrc_prefilter_config()
656 ctx_priv->st1_coeff, in fsl_easrc_prefilter_config()
657 ctx_priv->st1_num_taps, in fsl_easrc_prefilter_config()
658 ctx_priv->st1_addexp); in fsl_easrc_prefilter_config()
662 if (ctx_priv->st2_num_taps > 0) { in fsl_easrc_prefilter_config()
663 if (ctx_priv->st2_num_taps + ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) { in fsl_easrc_prefilter_config()
665 ctx_priv->st2_num_taps, EASRC_MAX_PF_TAPS); in fsl_easrc_prefilter_config()
666 ret = -EINVAL; in fsl_easrc_prefilter_config()
670 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), in fsl_easrc_prefilter_config()
677 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), in fsl_easrc_prefilter_config()
681 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), in fsl_easrc_prefilter_config()
683 EASRC_CCE1_PF_EXP(ctx_priv->st1_num_exp - 1)); in fsl_easrc_prefilter_config()
686 regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id), in fsl_easrc_prefilter_config()
688 EASRC_CCE2_ST2_TAPS(ctx_priv->st2_num_taps - 1)); in fsl_easrc_prefilter_config()
691 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), in fsl_easrc_prefilter_config()
696 ctx_priv->st2_coeff, in fsl_easrc_prefilter_config()
697 ctx_priv->st2_num_taps, in fsl_easrc_prefilter_config()
698 ctx_priv->st2_addexp); in fsl_easrc_prefilter_config()
712 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; in fsl_easrc_max_ch_for_slot()
715 int max_channels = 8 - slot->num_channel; in fsl_easrc_max_ch_for_slot()
718 if (ctx_priv->st1_num_taps > 0) { in fsl_easrc_max_ch_for_slot()
719 if (ctx_priv->st2_num_taps > 0) in fsl_easrc_max_ch_for_slot()
721 (ctx_priv->st1_num_taps - 1) * ctx_priv->st1_num_exp + 1; in fsl_easrc_max_ch_for_slot()
723 st1_mem_alloc = ctx_priv->st1_num_taps; in fsl_easrc_max_ch_for_slot()
726 if (ctx_priv->st2_num_taps > 0) in fsl_easrc_max_ch_for_slot()
727 st2_mem_alloc = ctx_priv->st2_num_taps; in fsl_easrc_max_ch_for_slot()
732 channels = (6144 - slot->pf_mem_used) / pf_mem_alloc; in fsl_easrc_max_ch_for_slot()
749 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_config_one_slot()
750 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; in fsl_easrc_config_one_slot()
755 if (slot->slot_index == 0) { in fsl_easrc_config_one_slot()
768 slot->num_channel = *req_channels; in fsl_easrc_config_one_slot()
771 slot->num_channel = *avail_channel; in fsl_easrc_config_one_slot()
772 *req_channels -= *avail_channel; in fsl_easrc_config_one_slot()
775 slot->min_channel = *start_channel; in fsl_easrc_config_one_slot()
776 slot->max_channel = *start_channel + slot->num_channel - 1; in fsl_easrc_config_one_slot()
777 slot->ctx_index = ctx->index; in fsl_easrc_config_one_slot()
778 slot->busy = true; in fsl_easrc_config_one_slot()
779 *start_channel += slot->num_channel; in fsl_easrc_config_one_slot()
781 regmap_update_bits(easrc->regmap, reg0, in fsl_easrc_config_one_slot()
783 EASRC_DPCS0R0_MAXCH(slot->max_channel)); in fsl_easrc_config_one_slot()
785 regmap_update_bits(easrc->regmap, reg0, in fsl_easrc_config_one_slot()
787 EASRC_DPCS0R0_MINCH(slot->min_channel)); in fsl_easrc_config_one_slot()
789 regmap_update_bits(easrc->regmap, reg0, in fsl_easrc_config_one_slot()
791 EASRC_DPCS0R0_NUMCH(slot->num_channel - 1)); in fsl_easrc_config_one_slot()
793 regmap_update_bits(easrc->regmap, reg0, in fsl_easrc_config_one_slot()
795 EASRC_DPCS0R0_CTXNUM(slot->ctx_index)); in fsl_easrc_config_one_slot()
797 if (ctx_priv->st1_num_taps > 0) { in fsl_easrc_config_one_slot()
798 if (ctx_priv->st2_num_taps > 0) in fsl_easrc_config_one_slot()
800 (ctx_priv->st1_num_taps - 1) * slot->num_channel * in fsl_easrc_config_one_slot()
801 ctx_priv->st1_num_exp + slot->num_channel; in fsl_easrc_config_one_slot()
803 st1_mem_alloc = ctx_priv->st1_num_taps * slot->num_channel; in fsl_easrc_config_one_slot()
805 slot->pf_mem_used = st1_mem_alloc; in fsl_easrc_config_one_slot()
806 regmap_update_bits(easrc->regmap, reg2, in fsl_easrc_config_one_slot()
810 if (slot->slot_index == 1) in fsl_easrc_config_one_slot()
811 addr = PREFILTER_MEM_LEN - st1_mem_alloc; in fsl_easrc_config_one_slot()
815 regmap_update_bits(easrc->regmap, reg2, in fsl_easrc_config_one_slot()
820 if (ctx_priv->st2_num_taps > 0) { in fsl_easrc_config_one_slot()
821 st1_chanxexp = slot->num_channel * (ctx_priv->st1_num_exp - 1); in fsl_easrc_config_one_slot()
823 regmap_update_bits(easrc->regmap, reg1, in fsl_easrc_config_one_slot()
827 st2_mem_alloc = slot->num_channel * ctx_priv->st2_num_taps; in fsl_easrc_config_one_slot()
828 slot->pf_mem_used += st2_mem_alloc; in fsl_easrc_config_one_slot()
829 regmap_update_bits(easrc->regmap, reg3, in fsl_easrc_config_one_slot()
833 if (slot->slot_index == 1) in fsl_easrc_config_one_slot()
834 addr = PREFILTER_MEM_LEN - st1_mem_alloc - st2_mem_alloc; in fsl_easrc_config_one_slot()
838 regmap_update_bits(easrc->regmap, reg3, in fsl_easrc_config_one_slot()
843 regmap_update_bits(easrc->regmap, reg0, in fsl_easrc_config_one_slot()
862 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_config_slot()
863 struct fsl_asrc_pair *ctx = easrc->pair[ctx_id]; in fsl_easrc_config_slot()
864 int req_channels = ctx->channels; in fsl_easrc_config_slot()
871 return -EINVAL; in fsl_easrc_config_slot()
874 slot0 = &easrc_priv->slot[i][0]; in fsl_easrc_config_slot()
875 slot1 = &easrc_priv->slot[i][1]; in fsl_easrc_config_slot()
877 if (slot0->busy && slot1->busy) { in fsl_easrc_config_slot()
879 } else if ((slot0->busy && slot0->ctx_index == ctx->index) || in fsl_easrc_config_slot()
880 (slot1->busy && slot1->ctx_index == ctx->index)) { in fsl_easrc_config_slot()
882 } else if (!slot0->busy) { in fsl_easrc_config_slot()
885 slota->slot_index = 0; in fsl_easrc_config_slot()
886 } else if (!slot1->busy) { in fsl_easrc_config_slot()
889 slota->slot_index = 1; in fsl_easrc_config_slot()
911 dev_err(&easrc->pdev->dev, "no avail slot.\n"); in fsl_easrc_config_slot()
912 return -EINVAL; in fsl_easrc_config_slot()
925 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_release_slot()
926 struct fsl_asrc_pair *ctx = easrc->pair[ctx_id]; in fsl_easrc_release_slot()
930 if (easrc_priv->slot[i][0].busy && in fsl_easrc_release_slot()
931 easrc_priv->slot[i][0].ctx_index == ctx->index) { in fsl_easrc_release_slot()
932 easrc_priv->slot[i][0].busy = false; in fsl_easrc_release_slot()
933 easrc_priv->slot[i][0].num_channel = 0; in fsl_easrc_release_slot()
934 easrc_priv->slot[i][0].pf_mem_used = 0; in fsl_easrc_release_slot()
936 regmap_write(easrc->regmap, REG_EASRC_DPCS0R0(i), 0); in fsl_easrc_release_slot()
937 regmap_write(easrc->regmap, REG_EASRC_DPCS0R1(i), 0); in fsl_easrc_release_slot()
938 regmap_write(easrc->regmap, REG_EASRC_DPCS0R2(i), 0); in fsl_easrc_release_slot()
939 regmap_write(easrc->regmap, REG_EASRC_DPCS0R3(i), 0); in fsl_easrc_release_slot()
942 if (easrc_priv->slot[i][1].busy && in fsl_easrc_release_slot()
943 easrc_priv->slot[i][1].ctx_index == ctx->index) { in fsl_easrc_release_slot()
944 easrc_priv->slot[i][1].busy = false; in fsl_easrc_release_slot()
945 easrc_priv->slot[i][1].num_channel = 0; in fsl_easrc_release_slot()
946 easrc_priv->slot[i][1].pf_mem_used = 0; in fsl_easrc_release_slot()
948 regmap_write(easrc->regmap, REG_EASRC_DPCS1R0(i), 0); in fsl_easrc_release_slot()
949 regmap_write(easrc->regmap, REG_EASRC_DPCS1R1(i), 0); in fsl_easrc_release_slot()
950 regmap_write(easrc->regmap, REG_EASRC_DPCS1R2(i), 0); in fsl_easrc_release_slot()
951 regmap_write(easrc->regmap, REG_EASRC_DPCS1R3(i), 0); in fsl_easrc_release_slot()
972 return -ENODEV; in fsl_easrc_config_context()
974 dev = &easrc->pdev->dev; in fsl_easrc_config_context()
978 return -EINVAL; in fsl_easrc_config_context()
981 ctx = easrc->pair[ctx_id]; in fsl_easrc_config_context()
983 ctx_priv = ctx->private; in fsl_easrc_config_context()
992 ret = fsl_easrc_prefilter_config(easrc, ctx->index); in fsl_easrc_config_context()
996 spin_lock_irqsave(&easrc->lock, lock_flags); in fsl_easrc_config_context()
997 ret = fsl_easrc_config_slot(easrc, ctx->index); in fsl_easrc_config_context()
998 spin_unlock_irqrestore(&easrc->lock, lock_flags); in fsl_easrc_config_context()
1005 * 2 - zero-fil mode in fsl_easrc_config_context()
1006 * 1 - replication mode in fsl_easrc_config_context()
1007 * 0 - software control in fsl_easrc_config_context()
1009 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), in fsl_easrc_config_context()
1011 EASRC_CCE1_RS_INIT(ctx_priv->rs_init_mode)); in fsl_easrc_config_context()
1013 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), in fsl_easrc_config_context()
1015 EASRC_CCE1_PF_INIT(ctx_priv->pf_init_mode)); in fsl_easrc_config_context()
1021 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id), in fsl_easrc_config_context()
1023 EASRC_CC_FIFO_WTMK(ctx_priv->in_params.fifo_wtmk)); in fsl_easrc_config_context()
1028 * So we set fifo_wtmk -1 to register. in fsl_easrc_config_context()
1030 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx_id), in fsl_easrc_config_context()
1032 EASRC_COC_FIFO_WTMK(ctx_priv->out_params.fifo_wtmk - 1)); in fsl_easrc_config_context()
1035 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id), in fsl_easrc_config_context()
1037 EASRC_CC_CHEN(ctx->channels - 1)); in fsl_easrc_config_context()
1045 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_process_format()
1046 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_process_format()
1050 return -EINVAL; in fsl_easrc_process_format()
1053 * Context Input Floating Point Format in fsl_easrc_process_format()
1054 * 0 - Integer Format in fsl_easrc_process_format()
1055 * 1 - Single Precision FP Format in fsl_easrc_process_format()
1057 fmt->floating_point = !snd_pcm_format_linear(raw_fmt); in fsl_easrc_process_format()
1058 fmt->sample_pos = 0; in fsl_easrc_process_format()
1059 fmt->iec958 = 0; in fsl_easrc_process_format()
1064 fmt->width = EASRC_WIDTH_16_BIT; in fsl_easrc_process_format()
1065 fmt->addexp = 15; in fsl_easrc_process_format()
1068 fmt->width = EASRC_WIDTH_20_BIT; in fsl_easrc_process_format()
1069 fmt->addexp = 19; in fsl_easrc_process_format()
1072 fmt->width = EASRC_WIDTH_24_BIT; in fsl_easrc_process_format()
1073 fmt->addexp = 23; in fsl_easrc_process_format()
1076 fmt->width = EASRC_WIDTH_32_BIT; in fsl_easrc_process_format()
1077 fmt->addexp = 31; in fsl_easrc_process_format()
1080 return -EINVAL; in fsl_easrc_process_format()
1085 fmt->width = easrc_priv->bps_iec958[ctx->index]; in fsl_easrc_process_format()
1086 fmt->iec958 = 1; in fsl_easrc_process_format()
1087 fmt->floating_point = 0; in fsl_easrc_process_format()
1088 if (fmt->width == EASRC_WIDTH_16_BIT) { in fsl_easrc_process_format()
1089 fmt->sample_pos = 12; in fsl_easrc_process_format()
1090 fmt->addexp = 15; in fsl_easrc_process_format()
1091 } else if (fmt->width == EASRC_WIDTH_20_BIT) { in fsl_easrc_process_format()
1092 fmt->sample_pos = 8; in fsl_easrc_process_format()
1093 fmt->addexp = 19; in fsl_easrc_process_format()
1094 } else if (fmt->width == EASRC_WIDTH_24_BIT) { in fsl_easrc_process_format()
1095 fmt->sample_pos = 4; in fsl_easrc_process_format()
1096 fmt->addexp = 23; in fsl_easrc_process_format()
1105 * 0 - Little-Endian in fsl_easrc_process_format()
1106 * 1 - Big-Endian in fsl_easrc_process_format()
1112 fmt->endianness = ret; in fsl_easrc_process_format()
1116 * 0b - Signed Format in fsl_easrc_process_format()
1117 * 1b - Unsigned Format in fsl_easrc_process_format()
1119 fmt->unsign = snd_pcm_format_unsigned(raw_fmt) > 0 ? 1 : 0; in fsl_easrc_process_format()
1128 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_set_ctx_format()
1129 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; in fsl_easrc_set_ctx_format()
1130 struct fsl_easrc_data_fmt *in_fmt = &ctx_priv->in_params.fmt; in fsl_easrc_set_ctx_format()
1131 struct fsl_easrc_data_fmt *out_fmt = &ctx_priv->out_params.fmt; in fsl_easrc_set_ctx_format()
1134 /* Get the bitfield values for input data format */ in fsl_easrc_set_ctx_format()
1141 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_set_ctx_format()
1143 EASRC_CC_BPS(in_fmt->width)); in fsl_easrc_set_ctx_format()
1144 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_set_ctx_format()
1146 in_fmt->endianness << EASRC_CC_ENDIANNESS_SHIFT); in fsl_easrc_set_ctx_format()
1147 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_set_ctx_format()
1149 in_fmt->floating_point << EASRC_CC_FMT_SHIFT); in fsl_easrc_set_ctx_format()
1150 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_set_ctx_format()
1152 in_fmt->unsign << EASRC_CC_INSIGN_SHIFT); in fsl_easrc_set_ctx_format()
1155 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_set_ctx_format()
1157 EASRC_CC_SAMPLE_POS(in_fmt->sample_pos)); in fsl_easrc_set_ctx_format()
1159 /* Get the bitfield values for input data format */ in fsl_easrc_set_ctx_format()
1166 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_set_ctx_format()
1168 EASRC_COC_BPS(out_fmt->width)); in fsl_easrc_set_ctx_format()
1169 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_set_ctx_format()
1171 out_fmt->endianness << EASRC_COC_ENDIANNESS_SHIFT); in fsl_easrc_set_ctx_format()
1172 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_set_ctx_format()
1174 out_fmt->floating_point << EASRC_COC_FMT_SHIFT); in fsl_easrc_set_ctx_format()
1175 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_set_ctx_format()
1177 out_fmt->unsign << EASRC_COC_OUTSIGN_SHIFT); in fsl_easrc_set_ctx_format()
1180 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_set_ctx_format()
1182 EASRC_COC_SAMPLE_POS(out_fmt->sample_pos)); in fsl_easrc_set_ctx_format()
1184 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_set_ctx_format()
1186 out_fmt->iec958 << EASRC_COC_IEC_EN_SHIFT); in fsl_easrc_set_ctx_format()
1192 * The ASRC provides interleaving support in hardware to ensure that a
1194 * to conform with this format. Interleaving parameters are accessed
1203 return -ENODEV; in fsl_easrc_set_ctx_organziation()
1205 easrc = ctx->asrc; in fsl_easrc_set_ctx_organziation()
1206 ctx_priv = ctx->private; in fsl_easrc_set_ctx_organziation()
1209 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index), in fsl_easrc_set_ctx_organziation()
1211 EASRC_CIA_ITER(ctx_priv->in_params.iterations)); in fsl_easrc_set_ctx_organziation()
1212 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index), in fsl_easrc_set_ctx_organziation()
1214 EASRC_CIA_GRLEN(ctx_priv->in_params.group_len)); in fsl_easrc_set_ctx_organziation()
1215 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index), in fsl_easrc_set_ctx_organziation()
1217 EASRC_CIA_ACCLEN(ctx_priv->in_params.access_len)); in fsl_easrc_set_ctx_organziation()
1220 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index), in fsl_easrc_set_ctx_organziation()
1222 EASRC_COA_ITER(ctx_priv->out_params.iterations)); in fsl_easrc_set_ctx_organziation()
1223 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index), in fsl_easrc_set_ctx_organziation()
1225 EASRC_COA_GRLEN(ctx_priv->out_params.group_len)); in fsl_easrc_set_ctx_organziation()
1226 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index), in fsl_easrc_set_ctx_organziation()
1228 EASRC_COA_ACCLEN(ctx_priv->out_params.access_len)); in fsl_easrc_set_ctx_organziation()
1242 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_request_context()
1248 dev = &easrc->pdev->dev; in fsl_easrc_request_context()
1250 spin_lock_irqsave(&easrc->lock, lock_flags); in fsl_easrc_request_context()
1253 if (easrc->pair[i]) in fsl_easrc_request_context()
1262 ret = -EBUSY; in fsl_easrc_request_context()
1263 } else if (channels > easrc->channel_avail) { in fsl_easrc_request_context()
1266 ret = -EINVAL; in fsl_easrc_request_context()
1268 ctx->index = index; in fsl_easrc_request_context()
1269 ctx->channels = channels; in fsl_easrc_request_context()
1270 easrc->pair[index] = ctx; in fsl_easrc_request_context()
1271 easrc->channel_avail -= channels; in fsl_easrc_request_context()
1274 spin_unlock_irqrestore(&easrc->lock, lock_flags); in fsl_easrc_request_context()
1292 easrc = ctx->asrc; in fsl_easrc_release_context()
1294 spin_lock_irqsave(&easrc->lock, lock_flags); in fsl_easrc_release_context()
1296 fsl_easrc_release_slot(easrc, ctx->index); in fsl_easrc_release_context()
1298 easrc->channel_avail += ctx->channels; in fsl_easrc_release_context()
1299 easrc->pair[ctx->index] = NULL; in fsl_easrc_release_context()
1301 spin_unlock_irqrestore(&easrc->lock, lock_flags); in fsl_easrc_release_context()
1311 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_start_context()
1313 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_start_context()
1315 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_start_context()
1317 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_start_context()
1329 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_stop_context()
1334 regmap_read(easrc->regmap, REG_EASRC_CC(ctx->index), &val); in fsl_easrc_stop_context()
1337 regmap_update_bits(easrc->regmap, in fsl_easrc_stop_context()
1338 REG_EASRC_CC(ctx->index), in fsl_easrc_stop_context()
1341 regmap_read(easrc->regmap, REG_EASRC_SFS(ctx->index), &val); in fsl_easrc_stop_context()
1346 for (i = 0; i < size * ctx->channels; i++) in fsl_easrc_stop_context()
1347 regmap_read(easrc->regmap, REG_EASRC_RDFIFO(ctx->index), &val); in fsl_easrc_stop_context()
1349 regmap_read(easrc->regmap, REG_EASRC_IRQF, &val); in fsl_easrc_stop_context()
1350 if (val & EASRC_IRQF_RSD(1 << ctx->index)) { in fsl_easrc_stop_context()
1352 regmap_write_bits(easrc->regmap, in fsl_easrc_stop_context()
1354 EASRC_IRQF_RSD(1 << ctx->index), in fsl_easrc_stop_context()
1355 EASRC_IRQF_RSD(1 << ctx->index)); in fsl_easrc_stop_context()
1359 } while (--retry); in fsl_easrc_stop_context()
1362 dev_warn(&easrc->pdev->dev, "RUN STOP fail\n"); in fsl_easrc_stop_context()
1365 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_stop_context()
1367 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), in fsl_easrc_stop_context()
1369 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), in fsl_easrc_stop_context()
1377 struct fsl_asrc *easrc = ctx->asrc; in fsl_easrc_get_dma_channel()
1378 enum asrc_pair_index index = ctx->index; in fsl_easrc_get_dma_channel()
1384 return dma_request_slave_channel(&easrc->pdev->dev, name); in fsl_easrc_get_dma_channel()
1403 return snd_pcm_hw_constraint_list(substream->runtime, 0, in fsl_easrc_startup()
1411 struct snd_pcm_runtime *runtime = substream->runtime; in fsl_easrc_trigger()
1412 struct fsl_asrc_pair *ctx = runtime->private_data; in fsl_easrc_trigger()
1431 return -EINVAL; in fsl_easrc_trigger()
1442 struct snd_pcm_runtime *runtime = substream->runtime; in fsl_easrc_hw_params()
1443 struct device *dev = &easrc->pdev->dev; in fsl_easrc_hw_params()
1444 struct fsl_asrc_pair *ctx = runtime->private_data; in fsl_easrc_hw_params()
1445 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; in fsl_easrc_hw_params()
1448 snd_pcm_format_t format = params_format(params); in fsl_easrc_hw_params() local
1457 ctx_priv->ctx_streams |= BIT(substream->stream); in fsl_easrc_hw_params()
1463 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_easrc_hw_params()
1464 ctx_priv->in_params.sample_rate = rate; in fsl_easrc_hw_params()
1465 ctx_priv->in_params.sample_format = format; in fsl_easrc_hw_params()
1466 ctx_priv->out_params.sample_rate = easrc->asrc_rate; in fsl_easrc_hw_params()
1467 ctx_priv->out_params.sample_format = easrc->asrc_format; in fsl_easrc_hw_params()
1469 ctx_priv->out_params.sample_rate = rate; in fsl_easrc_hw_params()
1470 ctx_priv->out_params.sample_format = format; in fsl_easrc_hw_params()
1471 ctx_priv->in_params.sample_rate = easrc->asrc_rate; in fsl_easrc_hw_params()
1472 ctx_priv->in_params.sample_format = easrc->asrc_format; in fsl_easrc_hw_params()
1475 ctx->channels = channels; in fsl_easrc_hw_params()
1476 ctx_priv->in_params.fifo_wtmk = 0x20; in fsl_easrc_hw_params()
1477 ctx_priv->out_params.fifo_wtmk = 0x20; in fsl_easrc_hw_params()
1480 * Do only rate conversion and keep the same format for input in fsl_easrc_hw_params()
1484 &ctx_priv->in_params.sample_format, in fsl_easrc_hw_params()
1485 &ctx_priv->out_params.sample_format); in fsl_easrc_hw_params()
1487 dev_err(dev, "failed to set format %d", ret); in fsl_easrc_hw_params()
1491 ret = fsl_easrc_config_context(easrc, ctx->index); in fsl_easrc_hw_params()
1497 ctx_priv->in_params.iterations = 1; in fsl_easrc_hw_params()
1498 ctx_priv->in_params.group_len = ctx->channels; in fsl_easrc_hw_params()
1499 ctx_priv->in_params.access_len = ctx->channels; in fsl_easrc_hw_params()
1500 ctx_priv->out_params.iterations = 1; in fsl_easrc_hw_params()
1501 ctx_priv->out_params.group_len = ctx->channels; in fsl_easrc_hw_params()
1502 ctx_priv->out_params.access_len = ctx->channels; in fsl_easrc_hw_params()
1516 struct snd_pcm_runtime *runtime = substream->runtime; in fsl_easrc_hw_free()
1517 struct fsl_asrc_pair *ctx = runtime->private_data; in fsl_easrc_hw_free()
1521 return -EINVAL; in fsl_easrc_hw_free()
1523 ctx_priv = ctx->private; in fsl_easrc_hw_free()
1525 if (ctx_priv->ctx_streams & BIT(substream->stream)) { in fsl_easrc_hw_free()
1526 ctx_priv->ctx_streams &= ~BIT(substream->stream); in fsl_easrc_hw_free()
1542 struct fsl_asrc *easrc = dev_get_drvdata(cpu_dai->dev); in fsl_easrc_dai_probe()
1545 &easrc->dma_params_tx, in fsl_easrc_dai_probe()
1546 &easrc->dma_params_rx); in fsl_easrc_dai_probe()
1553 .stream_name = "ASRC-Playback",
1562 .stream_name = "ASRC-Capture",
1575 .name = "fsl-easrc-dai",
1755 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_dump_firmware()
1756 struct asrc_firmware_hdr *firm = easrc_priv->firmware_hdr; in fsl_easrc_dump_firmware()
1757 struct interp_params *interp = easrc_priv->interp; in fsl_easrc_dump_firmware()
1758 struct prefil_params *prefil = easrc_priv->prefil; in fsl_easrc_dump_firmware()
1759 struct device *dev = &easrc->pdev->dev; in fsl_easrc_dump_firmware()
1762 if (firm->magic != FIRMWARE_MAGIC) { in fsl_easrc_dump_firmware()
1767 dev_dbg(dev, "Firmware v%u dump:\n", firm->firmware_version); in fsl_easrc_dump_firmware()
1768 dev_dbg(dev, "Num prefilter scenarios: %u\n", firm->prefil_scen); in fsl_easrc_dump_firmware()
1769 dev_dbg(dev, "Num interpolation scenarios: %u\n", firm->interp_scen); in fsl_easrc_dump_firmware()
1772 for (i = 0; i < firm->interp_scen; i++) { in fsl_easrc_dump_firmware()
1783 for (i = 0; i < firm->prefil_scen; i++) { in fsl_easrc_dump_firmware()
1807 return -EINVAL; in fsl_easrc_get_firmware()
1809 easrc_priv = easrc->private; in fsl_easrc_get_firmware()
1810 fw_p = &easrc_priv->fw; in fsl_easrc_get_firmware()
1812 ret = request_firmware(fw_p, easrc_priv->fw_name, &easrc->pdev->dev); in fsl_easrc_get_firmware()
1816 data = easrc_priv->fw->data; in fsl_easrc_get_firmware()
1818 easrc_priv->firmware_hdr = (struct asrc_firmware_hdr *)data; in fsl_easrc_get_firmware()
1819 pnum = easrc_priv->firmware_hdr->prefil_scen; in fsl_easrc_get_firmware()
1820 inum = easrc_priv->firmware_hdr->interp_scen; in fsl_easrc_get_firmware()
1824 easrc_priv->interp = (struct interp_params *)(data + offset); in fsl_easrc_get_firmware()
1830 easrc_priv->prefil = (struct prefil_params *)(data + offset); in fsl_easrc_get_firmware()
1843 struct device *dev = &easrc->pdev->dev; in fsl_easrc_isr()
1846 regmap_read(easrc->regmap, REG_EASRC_IRQF, &val); in fsl_easrc_isr()
1863 { .compatible = "fsl,imx8mn-easrc",},
1871 struct device *dev = &pdev->dev; in fsl_easrc_probe()
1880 return -ENOMEM; in fsl_easrc_probe()
1884 return -ENOMEM; in fsl_easrc_probe()
1886 easrc->pdev = pdev; in fsl_easrc_probe()
1887 easrc->private = easrc_priv; in fsl_easrc_probe()
1888 np = dev->of_node; in fsl_easrc_probe()
1893 dev_err(&pdev->dev, "failed ioremap\n"); in fsl_easrc_probe()
1897 easrc->paddr = res->start; in fsl_easrc_probe()
1899 easrc->regmap = devm_regmap_init_mmio_clk(dev, "mem", regs, in fsl_easrc_probe()
1901 if (IS_ERR(easrc->regmap)) { in fsl_easrc_probe()
1903 return PTR_ERR(easrc->regmap); in fsl_easrc_probe()
1912 ret = devm_request_irq(&pdev->dev, irq, fsl_easrc_isr, 0, in fsl_easrc_probe()
1919 easrc->mem_clk = devm_clk_get(dev, "mem"); in fsl_easrc_probe()
1920 if (IS_ERR(easrc->mem_clk)) { in fsl_easrc_probe()
1922 return PTR_ERR(easrc->mem_clk); in fsl_easrc_probe()
1926 easrc->channel_avail = 32; in fsl_easrc_probe()
1927 easrc->get_dma_channel = fsl_easrc_get_dma_channel; in fsl_easrc_probe()
1928 easrc->request_pair = fsl_easrc_request_context; in fsl_easrc_probe()
1929 easrc->release_pair = fsl_easrc_release_context; in fsl_easrc_probe()
1930 easrc->get_fifo_addr = fsl_easrc_get_fifo_addr; in fsl_easrc_probe()
1931 easrc->pair_priv_size = sizeof(struct fsl_easrc_ctx_priv); in fsl_easrc_probe()
1933 easrc_priv->rs_num_taps = EASRC_RS_32_TAPS; in fsl_easrc_probe()
1934 easrc_priv->const_coeff = 0x3FF0000000000000; in fsl_easrc_probe()
1936 ret = of_property_read_u32(np, "fsl,asrc-rate", &easrc->asrc_rate); in fsl_easrc_probe()
1938 dev_err(dev, "failed to asrc rate\n"); in fsl_easrc_probe()
1942 ret = of_property_read_u32(np, "fsl,asrc-format", &easrc->asrc_format); in fsl_easrc_probe()
1944 dev_err(dev, "failed to asrc format\n"); in fsl_easrc_probe()
1948 if (!(FSL_EASRC_FORMATS & (1ULL << easrc->asrc_format))) { in fsl_easrc_probe()
1949 dev_warn(dev, "unsupported format, switching to S24_LE\n"); in fsl_easrc_probe()
1950 easrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE; in fsl_easrc_probe()
1953 ret = of_property_read_string(np, "firmware-name", in fsl_easrc_probe()
1954 &easrc_priv->fw_name); in fsl_easrc_probe()
1963 spin_lock_init(&easrc->lock); in fsl_easrc_probe()
1965 regcache_cache_only(easrc->regmap, true); in fsl_easrc_probe()
1977 dev_err(&pdev->dev, "failed to register ASoC platform\n"); in fsl_easrc_probe()
1986 pm_runtime_disable(&pdev->dev); in fsl_easrc_remove()
1994 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_runtime_suspend()
1997 regcache_cache_only(easrc->regmap, true); in fsl_easrc_runtime_suspend()
1999 clk_disable_unprepare(easrc->mem_clk); in fsl_easrc_runtime_suspend()
2001 spin_lock_irqsave(&easrc->lock, lock_flags); in fsl_easrc_runtime_suspend()
2002 easrc_priv->firmware_loaded = 0; in fsl_easrc_runtime_suspend()
2003 spin_unlock_irqrestore(&easrc->lock, lock_flags); in fsl_easrc_runtime_suspend()
2011 struct fsl_easrc_priv *easrc_priv = easrc->private; in fsl_easrc_runtime_resume()
2018 ret = clk_prepare_enable(easrc->mem_clk); in fsl_easrc_runtime_resume()
2022 regcache_cache_only(easrc->regmap, false); in fsl_easrc_runtime_resume()
2023 regcache_mark_dirty(easrc->regmap); in fsl_easrc_runtime_resume()
2024 regcache_sync(easrc->regmap); in fsl_easrc_runtime_resume()
2026 spin_lock_irqsave(&easrc->lock, lock_flags); in fsl_easrc_runtime_resume()
2027 if (easrc_priv->firmware_loaded) { in fsl_easrc_runtime_resume()
2028 spin_unlock_irqrestore(&easrc->lock, lock_flags); in fsl_easrc_runtime_resume()
2031 easrc_priv->firmware_loaded = 1; in fsl_easrc_runtime_resume()
2032 spin_unlock_irqrestore(&easrc->lock, lock_flags); in fsl_easrc_runtime_resume()
2043 * any context processing within the ASRC in fsl_easrc_runtime_resume()
2052 ctx = easrc->pair[i]; in fsl_easrc_runtime_resume()
2056 ctx_priv = ctx->private; in fsl_easrc_runtime_resume()
2058 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * in fsl_easrc_runtime_resume()
2059 ctx_priv->out_params.sample_rate / in fsl_easrc_runtime_resume()
2060 ctx_priv->in_params.sample_rate; in fsl_easrc_runtime_resume()
2061 if (ctx_priv->in_filled_sample * ctx_priv->out_params.sample_rate in fsl_easrc_runtime_resume()
2062 % ctx_priv->in_params.sample_rate != 0) in fsl_easrc_runtime_resume()
2063 ctx_priv->out_missed_sample += 1; in fsl_easrc_runtime_resume()
2066 ctx_priv->st1_coeff, in fsl_easrc_runtime_resume()
2067 ctx_priv->st1_num_taps, in fsl_easrc_runtime_resume()
2068 ctx_priv->st1_addexp); in fsl_easrc_runtime_resume()
2073 ctx_priv->st2_coeff, in fsl_easrc_runtime_resume()
2074 ctx_priv->st2_num_taps, in fsl_easrc_runtime_resume()
2075 ctx_priv->st2_addexp); in fsl_easrc_runtime_resume()
2084 clk_disable_unprepare(easrc->mem_clk); in fsl_easrc_runtime_resume()
2100 .name = "fsl-easrc",