Lines Matching refs:devid
55 #define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM) argument
56 #define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G) argument
57 #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) argument
171 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ argument
172 (devid) == PCI_CHIP_I915_GM || \
173 (devid) == PCI_CHIP_I945_GM || \
174 (devid) == PCI_CHIP_I945_GME || \
175 (devid) == PCI_CHIP_I965_GM || \
176 (devid) == PCI_CHIP_I965_GME || \
177 (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
178 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
179 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
181 #define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \ argument
182 (devid) == PCI_CHIP_Q45_G || \
183 (devid) == PCI_CHIP_G45_G || \
184 (devid) == PCI_CHIP_G41_G)
185 #define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM) argument
186 #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) argument
188 #define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G) argument
189 #define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G) argument
191 #define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \ argument
192 (devid) == PCI_CHIP_E7221_G || \
193 (devid) == PCI_CHIP_I915_GM)
195 #define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \ argument
196 (devid) == PCI_CHIP_I945_GME)
198 #define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \ argument
199 (devid) == PCI_CHIP_I945_GM || \
200 (devid) == PCI_CHIP_I945_GME || \
201 IS_G33(devid))
203 #define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \ argument
204 (devid) == PCI_CHIP_Q33_G || \
205 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
207 #define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \ argument
208 (devid) == PCI_CHIP_845_G || \
209 (devid) == PCI_CHIP_I855_GM || \
210 (devid) == PCI_CHIP_I865_G)
212 #define IS_GEN3(devid) (IS_945(devid) || IS_915(devid)) argument
214 #define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \ argument
215 (devid) == PCI_CHIP_I965_Q || \
216 (devid) == PCI_CHIP_I965_G_1 || \
217 (devid) == PCI_CHIP_I965_GM || \
218 (devid) == PCI_CHIP_I965_GME || \
219 (devid) == PCI_CHIP_I946_GZ || \
220 IS_G4X(devid))
222 #define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid)) argument
224 #define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \ argument
225 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
226 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
227 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
228 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
229 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
230 (devid) == PCI_CHIP_SANDYBRIDGE_S)
232 #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ argument
233 IS_HASWELL(devid) || \
234 IS_VALLEYVIEW(devid))
236 #define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \ argument
237 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
238 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
239 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
240 (devid) == PCI_CHIP_IVYBRIDGE_S || \
241 (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
243 #define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \ argument
244 (devid) == PCI_CHIP_VALLEYVIEW_1 || \
245 (devid) == PCI_CHIP_VALLEYVIEW_2 || \
246 (devid) == PCI_CHIP_VALLEYVIEW_3)
248 #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \ argument
249 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
250 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
251 (devid) == PCI_CHIP_HASWELL_B_GT1 || \
252 (devid) == PCI_CHIP_HASWELL_E_GT1 || \
253 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
254 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
255 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
256 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
257 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
258 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
259 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
260 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
261 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
262 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
263 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
264 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
265 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
266 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
267 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
268 #define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \ argument
269 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
270 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
271 (devid) == PCI_CHIP_HASWELL_B_GT2 || \
272 (devid) == PCI_CHIP_HASWELL_E_GT2 || \
273 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
274 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
275 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
276 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
277 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
278 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
279 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
280 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
281 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
282 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
283 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
284 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
285 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
286 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
287 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
288 #define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \ argument
289 (devid) == PCI_CHIP_HASWELL_M_GT3 || \
290 (devid) == PCI_CHIP_HASWELL_S_GT3 || \
291 (devid) == PCI_CHIP_HASWELL_B_GT3 || \
292 (devid) == PCI_CHIP_HASWELL_E_GT3 || \
293 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
294 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
295 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
296 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
297 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
298 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
299 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
300 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
301 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
302 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
303 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
304 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
305 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
306 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
307 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
309 #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ argument
310 IS_HSW_GT2(devid) || \
311 IS_HSW_GT3(devid))
313 #define IS_BROADWELL(devid) (((devid & 0xff00) != 0x1600) ? 0 : \ argument
314 (((devid & 0x00f0) >> 4) > 3) ? 0 : \
315 ((devid & 0x000f) == BDW_SPARE) ? 1 : \
316 ((devid & 0x000f) == BDW_ULT) ? 1 : \
317 ((devid & 0x000f) == BDW_IRIS) ? 1 : \
318 ((devid & 0x000f) == BDW_SERVER) ? 1 : \
319 ((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \
320 ((devid & 0x000f) == BDW_ULX) ? 1 : 0)
322 #define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \ argument
323 (devid) == PCI_CHIP_CHERRYVIEW_1 || \
324 (devid) == PCI_CHIP_CHERRYVIEW_2 || \
325 (devid) == PCI_CHIP_CHERRYVIEW_3)
327 #define IS_GEN8(devid) (IS_BROADWELL(devid) || \ argument
328 IS_CHERRYVIEW(devid))
334 drm_private bool intel_is_genx(unsigned int devid, int gen);
335 drm_private bool intel_get_genx(unsigned int devid, int *gen);
337 #define IS_GEN9(devid) intel_is_genx(devid, 9) argument
338 #define IS_GEN10(devid) intel_is_genx(devid, 10) argument
339 #define IS_GEN11(devid) intel_is_genx(devid, 11) argument
340 #define IS_GEN12(devid) intel_is_genx(devid, 12) argument