151       RegClass rc = RegClass(mask.regClass().type(), 1);  in emit_mbcnt()
173       dst = bld.tmp(src.regClass());  in emit_wqm()
193    if (index.regClass() == s1)  in emit_bpermute()
341    if (src.regClass() == dst_rc) {  in emit_extract_vector()
349    if (it != ctx->allocated_vec.end() && dst_rc.bytes() == it->second[idx].regClass().bytes()) {  in emit_extract_vector()
350       if (it->second[idx].regClass() == dst_rc) {  in emit_extract_vector()
527    if (vec.regClass() == dst.regClass()) {  in byte_align_vector()
572    assert(val.regClass() == s1);  in bool_to_vector_condition()
573    assert(dst.regClass() == bld.lm);  in bool_to_vector_condition()
586    assert(val.regClass() == bld.lm);  in bool_to_scalar_condition()
587    assert(dst.regClass() == s1);  in bool_to_scalar_condition()
634    } else if (src.regClass() == s1) {  in convert_int()
645       if (sign_extend && dst.regClass() == s2) {  in convert_int()
649       } else if (sign_extend && dst.regClass() == v2) {  in convert_int()
680    Temp tmp = dst.regClass() == s2 ? bld.tmp(s1) : dst;  in extract_8_16_bit_sgpr_element()
689    if (dst.regClass() == s2)  in extract_8_16_bit_sgpr_element()
769       assert(tmp.regClass() == v6b && dword == 1);  in get_alu_src_vop3p()
911          tmp = bld.vop3(op, bld.def(dst.regClass()), src[0], src[1], src[2]);  in emit_vop3a_instruction()
913          tmp = bld.vop3(op, bld.def(dst.regClass()), src[0], src[1]);  in emit_vop3a_instruction()
1029    assert(dst.regClass() == bld.lm);  in emit_sopc_instruction()
1032    assert(src0.regClass() == src1.regClass());  in emit_sopc_instruction()
1056    assert(dst.regClass() == ctx->program->lane_mask);  in emit_comparison()
1072    assert(dst.regClass() == bld.lm);  in emit_boolean_logic()
1073    assert(src0.regClass() == bld.lm);  in emit_boolean_logic()
1074    assert(src1.regClass() == bld.lm);  in emit_boolean_logic()
1087    assert(cond.regClass() == bld.lm);  in emit_bcsel()
1113       assert(dst.regClass() == bld.lm);  in emit_bcsel()
1114       assert(then.regClass() == bld.lm);  in emit_bcsel()
1115       assert(els.regClass() == bld.lm);  in emit_bcsel()
1119       if (dst.regClass() == s1 || dst.regClass() == s2) {  in emit_bcsel()
1120          assert((then.regClass() == s1 || then.regClass() == s2) &&  in emit_bcsel()
1121                 els.regClass() == then.regClass());  in emit_bcsel()
1124             dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;  in emit_bcsel()
1428       if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {  in visit_alu_instr()
1430       } else if (dst.regClass() == v2) {  in visit_alu_instr()
1446       if (dst.regClass() == s1) {  in visit_alu_instr()
1448       } else if (dst.regClass() == v1) {  in visit_alu_instr()
1458       if (dst.regClass() == s1) {  in visit_alu_instr()
1462       } else if (dst.regClass() == s2) {  in visit_alu_instr()
1475       } else if (dst.regClass() == v1) {  in visit_alu_instr()
1477       } else if (dst.regClass() == v2) {  in visit_alu_instr()
1491       if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) {  in visit_alu_instr()
1493       } else if (dst.regClass() == v2b) {  in visit_alu_instr()
1495       } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
1497       } else if (dst.regClass() == v1) {  in visit_alu_instr()
1499       } else if (dst.regClass() == s1) {  in visit_alu_instr()
1507       if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) {  in visit_alu_instr()
1509       } else if (dst.regClass() == v2b) {  in visit_alu_instr()
1511       } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
1513       } else if (dst.regClass() == v1) {  in visit_alu_instr()
1515       } else if (dst.regClass() == s1) {  in visit_alu_instr()
1523       if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) {  in visit_alu_instr()
1525       } else if (dst.regClass() == v2b) {  in visit_alu_instr()
1527       } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
1529       } else if (dst.regClass() == v1) {  in visit_alu_instr()
1531       } else if (dst.regClass() == s1) {  in visit_alu_instr()
1539       if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) {  in visit_alu_instr()
1541       } else if (dst.regClass() == v2b) {  in visit_alu_instr()
1543       } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
1545       } else if (dst.regClass() == v1) {  in visit_alu_instr()
1547       } else if (dst.regClass() == s1) {  in visit_alu_instr()
1557       } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {  in visit_alu_instr()
1559       } else if (dst.regClass() == v2) {  in visit_alu_instr()
1561       } else if (dst.regClass() == s1) {  in visit_alu_instr()
1563       } else if (dst.regClass() == s2) {  in visit_alu_instr()
1573       } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {  in visit_alu_instr()
1575       } else if (dst.regClass() == v2) {  in visit_alu_instr()
1577       } else if (dst.regClass() == s1) {  in visit_alu_instr()
1579       } else if (dst.regClass() == s2) {  in visit_alu_instr()
1589       } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {  in visit_alu_instr()
1591       } else if (dst.regClass() == v2) {  in visit_alu_instr()
1593       } else if (dst.regClass() == s1) {  in visit_alu_instr()
1595       } else if (dst.regClass() == s2) {  in visit_alu_instr()
1603       if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) {  in visit_alu_instr()
1605       } else if (dst.regClass() == v2b) {  in visit_alu_instr()
1607       } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
1609       } else if (dst.regClass() == v1) {  in visit_alu_instr()
1611       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {  in visit_alu_instr()
1614       } else if (dst.regClass() == v2) {  in visit_alu_instr()
1616       } else if (dst.regClass() == s2) {  in visit_alu_instr()
1618       } else if (dst.regClass() == s1) {  in visit_alu_instr()
1626       if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) {  in visit_alu_instr()
1628       } else if (dst.regClass() == v2b) {  in visit_alu_instr()
1630       } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
1632       } else if (dst.regClass() == v1) {  in visit_alu_instr()
1635       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {  in visit_alu_instr()
1638       } else if (dst.regClass() == v2) {  in visit_alu_instr()
1640       } else if (dst.regClass() == s1) {  in visit_alu_instr()
1642       } else if (dst.regClass() == s2) {  in visit_alu_instr()
1650       if (dst.regClass() == v2b && ctx->program->chip_class >= GFX10) {  in visit_alu_instr()
1652       } else if (dst.regClass() == v2b) {  in visit_alu_instr()
1654       } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
1656       } else if (dst.regClass() == v1) {  in visit_alu_instr()
1658       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {  in visit_alu_instr()
1661       } else if (dst.regClass() == v2) {  in visit_alu_instr()
1663       } else if (dst.regClass() == s1) {  in visit_alu_instr()
1665       } else if (dst.regClass() == s2) {  in visit_alu_instr()
1674       if (src.regClass() == s1) {  in visit_alu_instr()
1676       } else if (src.regClass() == v1) {  in visit_alu_instr()
1678       } else if (src.regClass() == s2) {  in visit_alu_instr()
1688       if (src.regClass() == s1 || src.regClass() == s2) {  in visit_alu_instr()
1689          aco_opcode op = src.regClass() == s2  in visit_alu_instr()
1703       } else if (src.regClass() == v1) {  in visit_alu_instr()
1712       } else if (src.regClass() == v2) {  in visit_alu_instr()
1736       if (dst.regClass() == s1) {  in visit_alu_instr()
1738       } else if (dst.regClass() == v1) {  in visit_alu_instr()
1746       if (dst.regClass() == s1) {  in visit_alu_instr()
1755       } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
1775       if (dst.regClass() == s2) {  in visit_alu_instr()
1782       } else if (dst.regClass() == v2) {  in visit_alu_instr()
1795       if (dst.regClass() == s1) {  in visit_alu_instr()
1800       } else if (dst.regClass() == v2b) {  in visit_alu_instr()
1811       } else if (dst.regClass() == v1) {  in visit_alu_instr()
1821       if (dst.regClass() == v2b) {  in visit_alu_instr()
1825       } else if (dst.regClass() == v1) {  in visit_alu_instr()
1837       if (dst.regClass() == s1) {  in visit_alu_instr()
1841       if (dst.regClass() == v1) {  in visit_alu_instr()
1854       if (dst.regClass() == s2) {  in visit_alu_instr()
1862       } else if (dst.regClass() == v2) {  in visit_alu_instr()
1874       if (dst.regClass() == s1) {  in visit_alu_instr()
1877       } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
1884       if (dst.regClass() == v1) {  in visit_alu_instr()
1905       if (dst.regClass() == s2) {  in visit_alu_instr()
1912       } else if (dst.regClass() == v2) {  in visit_alu_instr()
1925       if (dst.regClass() == s1) {  in visit_alu_instr()
1928       } else if (dst.regClass() == v1) {  in visit_alu_instr()
1941       if (dst.regClass() == s2) {  in visit_alu_instr()
1949       } else if (dst.regClass() == v2) {  in visit_alu_instr()
1965       } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
1984       } else if (dst.regClass() == s1) {  in visit_alu_instr()
1992       if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {  in visit_alu_instr()
1998          Temp tmp = dst.regClass() == s1 ? bld.tmp(v1) : dst;  in visit_alu_instr()
2005          if (dst.regClass() == s1)  in visit_alu_instr()
2013       if (dst.regClass() == v1) {  in visit_alu_instr()
2015       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {  in visit_alu_instr()
2017       } else if (dst.regClass() == s1) {  in visit_alu_instr()
2027       if (dst.regClass() == v2b) {  in visit_alu_instr()
2029       } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
2031       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2033       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2041       if (dst.regClass() == v2b) {  in visit_alu_instr()
2043       } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
2045       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2047       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2055       if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
2065       if (dst.regClass() == v2b) {  in visit_alu_instr()
2070       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2075       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2085       if (dst.regClass() == v2b) {  in visit_alu_instr()
2088       } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
2090       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2093       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2102       if (dst.regClass() == v2b) {  in visit_alu_instr()
2105       } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
2107       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2110       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2177       if (dst.regClass() == v2b) {  in visit_alu_instr()
2179       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2182       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2191       if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
2199       if (dst.regClass() == v2b) {  in visit_alu_instr()
2201       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2204       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2219       if (dst.regClass() == v2b) {  in visit_alu_instr()
2224       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2229       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2243       if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
2253       if (dst.regClass() == v2b) {  in visit_alu_instr()
2256       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2262       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2271       if (dst.regClass() == v2b) {  in visit_alu_instr()
2273       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2282       if (dst.regClass() == v2b) {  in visit_alu_instr()
2284       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2287       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2296       if (dst.regClass() == v2b) {  in visit_alu_instr()
2298       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2306       if (dst.regClass() == v2b) {  in visit_alu_instr()
2308       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2311       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2320       if (dst.regClass() == v2b) {  in visit_alu_instr()
2322       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2324       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2332       if (dst.regClass() == v2b) {  in visit_alu_instr()
2334       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2336       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2345       if (dst.regClass() == v2b) {  in visit_alu_instr()
2347       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2349       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2379       if (dst.regClass() == v2b) {  in visit_alu_instr()
2381       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2383       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2392       if (dst.regClass() == v2b) {  in visit_alu_instr()
2394       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2396       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2444       if (dst.regClass() == v2b) {  in visit_alu_instr()
2450       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2467       if (dst.regClass() == v2b) {  in visit_alu_instr()
2469       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2471       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2479       if (dst.regClass() == v2b) {  in visit_alu_instr()
2481       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2483       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2507       if (dst.regClass() == v2b) {  in visit_alu_instr()
2514       } else if (dst.regClass() == v1) {  in visit_alu_instr()
2519       } else if (dst.regClass() == v2) {  in visit_alu_instr()
2581       assert(dst.regClass() == v2b);  in visit_alu_instr()
2661       assert(dst.regClass() == v2b);  in visit_alu_instr()
3004       assert(src.regClass() == bld.lm);  in visit_alu_instr()
3006       if (dst.regClass() == s1) {  in visit_alu_instr()
3009       } else if (dst.regClass() == v2b) {  in visit_alu_instr()
3019       assert(src.regClass() == bld.lm);  in visit_alu_instr()
3021       if (dst.regClass() == s1) {  in visit_alu_instr()
3024       } else if (dst.regClass() == v1) {  in visit_alu_instr()
3034       assert(src.regClass() == bld.lm);  in visit_alu_instr()
3036       if (dst.regClass() == s2) {  in visit_alu_instr()
3040       } else if (dst.regClass() == v2) {  in visit_alu_instr()
3090       assert(src.regClass() == bld.lm);  in visit_alu_instr()
3093       if (tmp.regClass() == s1) {  in visit_alu_instr()
3109       assert(dst.regClass() == bld.lm);  in visit_alu_instr()
3112          assert(src.regClass() == v1 || src.regClass() == v2);  in visit_alu_instr()
3113          assert(dst.regClass() == bld.lm);  in visit_alu_instr()
3119          assert(src.regClass() == s1 || src.regClass() == s2);  in visit_alu_instr()
3121          if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) {  in visit_alu_instr()
3148       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()),  in visit_alu_instr()
3152       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst),  in visit_alu_instr()
3157          bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()),  in visit_alu_instr()
3165          bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst),  in visit_alu_instr()
3176       if (dst.regClass() == v1) {  in visit_alu_instr()
3191       if (dst.regClass() == v1) {  in visit_alu_instr()
3217       if (src.regClass() == v1)  in visit_alu_instr()
3219       if (dst.regClass() == v1) {  in visit_alu_instr()
3231       if (src.regClass() == s1)  in visit_alu_instr()
3237       if (dst.regClass() == v1) {  in visit_alu_instr()
3247       assert(dst.regClass() == v1);  in visit_alu_instr()
3289       if (dst.regClass() == s1) {  in visit_alu_instr()
3291       } else if (dst.regClass() == v1) {  in visit_alu_instr()
3301       if (dst.regClass() == s1) {  in visit_alu_instr()
3328       } else if (dst.regClass() == v1) {  in visit_alu_instr()
3392       } else if (dst.regClass() == s1 && instr->dest.dest.ssa.bit_size == 16) {  in visit_alu_instr()
3411          if (def.regClass() == s1) {  in visit_alu_instr()
3415             src = emit_extract_vector(ctx, src, 0, def.regClass());  in visit_alu_instr()
3443          if (def.regClass() == s1) {  in visit_alu_instr()
3447             src = emit_extract_vector(ctx, src, 0, def.regClass());  in visit_alu_instr()
3462       if (src.regClass() == s1) {  in visit_alu_instr()
3464       } else if (src.regClass() == v1) {  in visit_alu_instr()
3466       } else if (src.regClass() == v2) {  in visit_alu_instr()
3470       } else if (src.regClass() == s2) {  in visit_alu_instr()
3597       assert(dst.regClass() == bld.lm);  in visit_load_const()
3728          } else if (offset_tmp.regClass() == s1) {  in emit_load()
3731          } else if (offset_tmp.regClass() == v1) {  in emit_load()
3738             if (offset_tmp.regClass() == s2) {  in emit_load()
3762          } else if (offset_tmp.regClass() == s1) {  in emit_load()
3765          } else if (offset_tmp.regClass() == s2) {  in emit_load()
3768          } else if (offset_tmp.regClass() == v1) {  in emit_load()
3771          } else if (offset_tmp.regClass() == v2) {  in emit_load()
3925    offset = offset.regClass() == s1 ? bld.copy(bld.def(v1), offset) : offset;  in lds_load_callback()
3975    Temp val = rc == info.dst.regClass() && dst_hint.id() ? dst_hint : bld.tmp(rc);  in lds_load_callback()
4022    Temp val = dst_hint.id() && dst_hint.regClass() == rc ? dst_hint : bld.tmp(rc);  in smem_load_callback()
4079    Temp val = dst_hint.id() && rc == dst_hint.regClass() ? dst_hint : bld.tmp(rc);  in mubuf_load_callback()
4140    Temp val = dst_hint.id() && rc == dst_hint.regClass() ? dst_hint : bld.tmp(rc);  in global_load_callback()
4156       offset = offset.regClass() == s2 ? bld.copy(bld.def(v2), offset) : offset;  in global_load_callback()
4544       else if (unlikely(voffset.regClass() == s1))  in resolve_excess_vmem_const_offset()
4547       else if (likely(voffset.regClass() == v1))  in resolve_excess_vmem_const_offset()
4720    create_vec_from_array(ctx, src, dst.size(), dst.regClass().type(), 4u, 0, dst);  in load_input_from_temps()
4760    if (dst.regClass() == v2b) {  in emit_interp_instr()
5658    assert(src.regClass() == bld.lm);  in visit_discard_if()
5975          coord = emit_wqm(bld, coord, bld.tmp(coord.regClass()), true);  in emit_mimg()
5983             coords[i] = emit_wqm(bld, coords[i], bld.tmp(coords[i].regClass()), true);  in emit_mimg()
6105    Temp tmp = bld.tmp(dst.regClass());  in emit_tfe_init()
7562    assert(src.regClass() == bld.lm);  in emit_boolean_exclusive_scan()
7646    assert(dst.regClass().type() != RegType::vgpr);  in emit_uniform_subgroup()
7647    if (src.regClass().type() == RegType::vgpr)  in emit_uniform_subgroup()
7661       Temp tmp = dst.regClass() == s1 ? bld.tmp(src_tmp.regClass()) : dst.getTemp();  in emit_addition_uniform_reduce()
7678    if (dst.regClass() == s1)  in emit_addition_uniform_reduce()
8259          assert(src.regClass() == bld.lm);  in visit_intrinsic()
8260       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {  in visit_intrinsic()
8262       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {  in visit_intrinsic()
8274             bld.pseudo(aco_opcode::p_create_vector, bld.def(dst.regClass()), src, Operand::zero());  in visit_intrinsic()
8295          if (src.regClass() == v1b || src.regClass() == v2b) {  in visit_intrinsic()
8300                           bld.def(src.regClass() == v1b ? v3b : v2b), tmp);  in visit_intrinsic()
8303          } else if (src.regClass() == v1) {  in visit_intrinsic()
8305          } else if (src.regClass() == v2) {  in visit_intrinsic()
8312          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == s1) {  in visit_intrinsic()
8313             assert(src.regClass() == bld.lm);  in visit_intrinsic()
8316          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) {  in visit_intrinsic()
8317             assert(src.regClass() == bld.lm);  in visit_intrinsic()
8347       if (src.regClass() == v1b || src.regClass() == v2b || src.regClass() == v1) {  in visit_intrinsic()
8349       } else if (src.regClass() == v2) {  in visit_intrinsic()
8357          assert(src.regClass() == bld.lm);  in visit_intrinsic()
8369       assert(src.regClass() == bld.lm);  in visit_intrinsic()
8370       assert(dst.regClass() == bld.lm);  in visit_intrinsic()
8383       assert(src.regClass() == bld.lm);  in visit_intrinsic()
8384       assert(dst.regClass() == bld.lm);  in visit_intrinsic()
8457                                              bld.def(dst.regClass()), src);  in visit_intrinsic()
8508          tmp = bld.tmp(dst.regClass());  in visit_intrinsic()
8512          assert(src.regClass() == bld.lm && tmp.regClass() == bld.lm);  in visit_intrinsic()
8577          assert(src.regClass() == bld.lm);  in visit_intrinsic()
8583       } else if (dst.regClass() == v1b) {  in visit_intrinsic()
8586       } else if (dst.regClass() == v2b) {  in visit_intrinsic()
8589       } else if (dst.regClass() == v1) {  in visit_intrinsic()
8591       } else if (dst.regClass() == v2) {  in visit_intrinsic()
8608       if (dst.regClass() == v1) {  in visit_intrinsic()
8611       } else if (dst.regClass() == v2) {  in visit_intrinsic()
8637       assert(dst.regClass() == v1);  in visit_intrinsic()
8649       if (src.regClass() == s1) {  in visit_intrinsic()
8651       } else if (dst.regClass() == v1 && src.regClass() == v1) {  in visit_intrinsic()
8680       assert(src.regClass() == bld.lm);  in visit_intrinsic()
9554          resource = bld.tmp(resource.regClass());  in visit_tex()
9644          if (dst.regClass() == s1) {  in visit_tex()
9804       Temp tmp = dst.regClass() == tmp_dst.regClass() ? dst : bld.tmp(tmp_dst.regClass());  in visit_tex()
9840    assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == ctx->program->lane_mask);  in visit_phi()
9867                operands[num_operands++] = Operand(dst.regClass());  in visit_phi()
9878       Operand op = get_phi_operand(ctx, src.second, dst.regClass(), logical);  in visit_phi()
9884       operands[num_operands++] = Operand(dst.regClass());  in visit_phi()
9918       phi->operands[1] = Operand(dst.regClass());  in visit_phi()
10182    RegClass rc = vals[0].regClass();  in create_continue_phis()
10299    assert(cond.regClass() == ctx->program->lane_mask);  in begin_divergent_if_then()
10457    assert(cond.regClass() == s1);  in begin_uniform_if_then()
10576       assert(cond.regClass() == ctx->program->lane_mask);  in visit_if()
10893    bool is_16bit = values[0].regClass() == v2b;  in export_fs_mrt_color()
11315       if (startpgm->definitions[i].regClass().size() > 1) {  in split_arguments()
11317                            startpgm->definitions[i].regClass().size());  in split_arguments()
11446    assert(count.regClass() == s1);  in lanecount_to_mask()