Lines Matching full:v1
30 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm
31 if (!setup_cs("v1 v1 s1 s1", (chip_class)i))
37 writeout(0, bld.v_mul_imm(bld.def(v1), inputs[0], 0));
40 writeout(1, bld.v_mul_imm(bld.def(v1), inputs[0], 1));
42 //! v1: %res2 = v_lshlrev_b32 2, %a
44 writeout(2, bld.v_mul_imm(bld.def(v1), inputs[0], 4));
46 //! v1: %res3 = v_lshlrev_b32 31, %a
48 writeout(3, bld.v_mul_imm(bld.def(v1), inputs[0], 2147483648u));
52 //~gfx8! v1: %res4_tmp = v_lshlrev_b32 3, %a
53 //~gfx8! v1: %res4, s2: %_ = v_add_co_u32 %res4_tmp, %a
54 //~gfx(9|10)! v1: %res4 = v_lshl_add_u32 %a, 3, %a
56 writeout(4, bld.v_mul_imm(bld.def(v1), inputs[0], 9));
58 //~gfx[89]! v1: %res5_tmp = v_lshlrev_b32 3, %a
59 //~gfx8! v1: %res5, s2: %_ = v_sub_co_u32 %res5_tmp, %a
60 //~gfx9! v1: %res5 = v_sub_u32 %res5_tmp, %a
61 //~gfx10! v1: %res5 = v_mul_lo_u32 7, %a
63 writeout(5, bld.v_mul_imm(bld.def(v1), inputs[0], 7));
67 //~gfx8! v1: %res6_tmp0 = v_lshlrev_b32 2, %a
68 //~gfx8! v1: %res6_tmp1 = v_lshlrev_b32 6, %a
69 //~gfx8! v1: %res6, s2: %_ = v_add_co_u32 %res6_tmp1, %res6_tmp0
70 //~gfx9! v1: %res6_tmp = v_lshlrev_b32 2, %a
71 //~gfx9! v1: %res6 = v_lshl_add_u32 %a, 6, %res6_tmp
72 //~gfx10! v1: %res6 = v_mul_lo_u32 0x44, %a
74 writeout(6, bld.v_mul_imm(bld.def(v1), inputs[0], 4 | 64));
77 //~gfx8! v1: %res7 = v_mul_lo_u32 %res7_tmp, %a
78 //~gfx9! v1: %res7_tmp0 = v_lshlrev_b32 2, %a
79 //~gfx9! v1: %res7_tmp1 = v_lshl_add_u32 %a, 6, %res7_tmp0
80 //~gfx9! v1: %res7 = v_lshl_add_u32 %a, 8, %res7_tmp1
81 //~gfx10! v1: %res7 = v_mul_lo_u32 0x144, %a
83 writeout(7, bld.v_mul_imm(bld.def(v1), inputs[0], 4 | 64 | 256));
86 //~gfx8! v1: %res8 = v_mul_lo_u32 %res8_tmp, %a
87 //~gfx9! v1: %res8_tmp0 = v_lshlrev_b32 2, %a
88 //~gfx9! v1: %res8_tmp1 = v_lshl_add_u32 %a, 6, %res8_tmp0
89 //~gfx9! v1: %res8_tmp2 = v_lshl_add_u32 %a, 8, %res8_tmp1
90 //~gfx9! v1: %res8 = v_lshl_add_u32 %a, 11, %res8_tmp2
91 //~gfx10! v1: %res8 = v_mul_lo_u32 0x944, %a
93 writeout(8, bld.v_mul_imm(bld.def(v1), inputs[0], 4 | 64 | 256 | 2048));
97 //~gfx8! v1: %res9_tmp0 = v_lshlrev_b32 1, %a
98 //~gfx8! v1: %res9_tmp1 = v_lshlrev_b32 2, %a
99 //~gfx8! v1: %res9, s2: %_ = v_add_co_u32 %res9_tmp1, %res9_tmp0
100 //~gfx9! v1: %res9_tmp0 = v_lshlrev_b32 1, %a
101 //~gfx9! v1: %res9 = v_lshl_add_u32 %a, 2, %res9_tmp0
102 //~gfx10! v1: %res9 = v_mul_lo_u32 6, %a
104 writeout(9, bld.v_mul_imm(bld.def(v1), inputs[0], 2 | 4));
106 //~gfx(8|10)! v1: %res10 = v_mul_lo_u32 14, %a
107 //~gfx9! v1: %res10_tmp0 = v_lshlrev_b32 1, %a
108 //~gfx9! v1: %res10_tmp1 = v_lshl_add_u32 %a, 2, %res10_tmp0
109 //~gfx9! v1: %res10 = v_lshl_add_u32 %a, 3, %res10_tmp1
111 writeout(10, bld.v_mul_imm(bld.def(v1), inputs[0], 2 | 4 | 8));
113 //! v1: %res11 = v_mul_lo_u32 30, %a
115 writeout(11, bld.v_mul_imm(bld.def(v1), inputs[0], 2 | 4 | 8 | 16));