Lines Matching refs:qpu
158 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_a], n); in process_mux_deps()
161 if (!n->inst->qpu.sig.small_imm) { in process_mux_deps()
163 state->last_rf[n->inst->qpu.raddr_b], n); in process_mux_deps()
282 struct v3d_qpu_instr *inst = &qinst->qpu; in calculate_deps()
526 const struct v3d_qpu_instr *inst = &qinst->qpu; in reads_too_soon_after_write()
566 const struct v3d_qpu_instr *inst = &qinst->qpu; in writes_too_soon_after_write()
1030 if (prev_inst->inst->qpu.sig.thrsw) in choose_instruction_to_schedule()
1040 const struct v3d_qpu_instr *inst = &n->inst->qpu; in choose_instruction_to_schedule()
1145 if ((prev_inst->inst->qpu.sig.ldunifa || in choose_instruction_to_schedule()
1146 prev_inst->inst->qpu.sig.ldunifarf) && in choose_instruction_to_schedule()
1172 &prev_inst->inst->qpu, inst)) { in choose_instruction_to_schedule()
1224 if (chosen && chosen->inst->qpu.sig.ldvary) { in choose_instruction_to_schedule()
1298 v3d_qpu_dump(devinfo, &n->inst->qpu); in dump_state()
1308 v3d_qpu_dump(devinfo, &child->inst->qpu); in dump_state()
1359 const struct v3d_qpu_instr *before_inst = &before->inst->qpu; in instruction_latency()
1360 const struct v3d_qpu_instr *after_inst = &after->inst->qpu; in instruction_latency()
1452 update_scoreboard_for_chosen(scoreboard, &inst->qpu, c->devinfo); in insert_scheduled_instruction()
1477 const struct v3d_qpu_instr *inst = &qinst->qpu; in qpu_inst_valid_in_thrend_slot()
1554 qinst->qpu.type == V3D_QPU_INSTR_TYPE_ALU && in qpu_inst_before_thrsw_valid_in_delay_slot()
1555 (v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.add.waddr) || in qpu_inst_before_thrsw_valid_in_delay_slot()
1556 v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.mul.waddr))) { in qpu_inst_before_thrsw_valid_in_delay_slot()
1560 if (slot > 0 && qinst->qpu.sig.ldvary) in qpu_inst_before_thrsw_valid_in_delay_slot()
1577 if (v3d_qpu_writes_unifa(c->devinfo, &qinst->qpu)) in qpu_inst_before_thrsw_valid_in_delay_slot()
1605 if (qinst->qpu.sig.thrsw) in qpu_inst_after_thrsw_valid_in_delay_slot()
1618 if (qpu_inst_is_tlb(&qinst->qpu)) in qpu_inst_after_thrsw_valid_in_delay_slot()
1624 if (qinst->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH) in qpu_inst_after_thrsw_valid_in_delay_slot()
1637 if (v3d_qpu_writes_tmu(c->devinfo, &qinst->qpu) || in qpu_inst_after_thrsw_valid_in_delay_slot()
1638 qinst->qpu.sig.wrtmuc) { in qpu_inst_after_thrsw_valid_in_delay_slot()
1647 if (v3d_qpu_waits_on_tmu(&qinst->qpu)) in qpu_inst_after_thrsw_valid_in_delay_slot()
1653 if (v3d_qpu_writes_accum(c->devinfo, &qinst->qpu)) in qpu_inst_after_thrsw_valid_in_delay_slot()
1659 if (qinst->qpu.alu.mul.op == V3D_QPU_M_MULTOP) in qpu_inst_after_thrsw_valid_in_delay_slot()
1665 if (v3d_qpu_writes_flags(&qinst->qpu)) in qpu_inst_after_thrsw_valid_in_delay_slot()
1716 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU); in emit_thrsw()
1717 assert(inst->qpu.alu.add.op == V3D_QPU_A_NOP); in emit_thrsw()
1718 assert(inst->qpu.alu.mul.op == V3D_QPU_M_NOP); in emit_thrsw()
1736 struct v3d_qpu_sig sig = prev_inst->qpu.sig; in emit_thrsw()
1756 merge_inst->qpu.sig.thrsw = true; in emit_thrsw()
1779 second_inst->qpu.sig.thrsw = true; in emit_thrsw()
1803 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH) in qpu_inst_valid_in_branch_delay_slot()
1806 if (inst->qpu.sig.thrsw) in qpu_inst_valid_in_branch_delay_slot()
1809 if (v3d_qpu_writes_unifa(c->devinfo, &inst->qpu)) in qpu_inst_valid_in_branch_delay_slot()
1824 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH); in emit_branch()
1838 inst->qpu.branch.msfign == V3D_QPU_MSFIGN_NONE || in emit_branch()
1839 inst->qpu.branch.cond == V3D_QPU_BRANCH_COND_ALWAYS || in emit_branch()
1840 inst->qpu.branch.cond == V3D_QPU_BRANCH_COND_A0 || in emit_branch()
1841 inst->qpu.branch.cond == V3D_QPU_BRANCH_COND_NA0; in emit_branch()
1854 assert(prev_inst->qpu.type != V3D_QPU_INSTR_TYPE_BRANCH); in emit_branch()
1877 if (v3d_qpu_writes_flags(&prev_inst->qpu) && in emit_branch()
1878 inst->qpu.branch.cond != V3D_QPU_BRANCH_COND_ALWAYS) { in emit_branch()
1888 if (prev_prev_inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU && in emit_branch()
1889 prev_prev_inst->qpu.alu.add.op == V3D_QPU_A_SETMSF) { in emit_branch()
2019 if (!prev || prev->qpu.type != V3D_QPU_INSTR_TYPE_ALU) in fixup_pipelined_ldvary()
2022 if (prev->qpu.alu.add.op != V3D_QPU_A_NOP) { in fixup_pipelined_ldvary()
2023 if (prev->qpu.alu.add.magic_write == ldvary_magic && in fixup_pipelined_ldvary()
2024 prev->qpu.alu.add.waddr == ldvary_index) { in fixup_pipelined_ldvary()
2029 if (prev->qpu.alu.mul.op != V3D_QPU_M_NOP) { in fixup_pipelined_ldvary()
2030 if (prev->qpu.alu.mul.magic_write == ldvary_magic && in fixup_pipelined_ldvary()
2031 prev->qpu.alu.mul.waddr == ldvary_index) { in fixup_pipelined_ldvary()
2037 if (v3d_qpu_sig_writes_address(c->devinfo, &prev->qpu.sig)) in fixup_pipelined_ldvary()
2043 if (v3d_qpu_writes_flags(&prev->qpu)) in fixup_pipelined_ldvary()
2045 if (v3d_qpu_reads_flags(&prev->qpu)) in fixup_pipelined_ldvary()
2057 prev->qpu.sig.ldvary = true; in fixup_pipelined_ldvary()
2058 prev->qpu.sig_magic = ldvary_magic; in fixup_pipelined_ldvary()
2059 prev->qpu.sig_addr = ldvary_index; in fixup_pipelined_ldvary()
2098 struct v3d_qpu_instr *inst = &qinst->qpu; in schedule_instructions()
2130 inst, &merge->inst->qpu); in schedule_instructions()
2139 v3d_qpu_dump(devinfo, &merge->inst->qpu); in schedule_instructions()
2287 if (!v3d_qpu_is_nop(&inst->qpu)) in qpu_set_branch_targets()
2293 if (inst->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH) { in qpu_set_branch_targets()
2298 assert(branch && branch->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH); in qpu_set_branch_targets()
2310 branch->qpu.branch.offset = in qpu_set_branch_targets()
2334 if (branch->qpu.branch.cond == V3D_QPU_BRANCH_COND_ALWAYS) { in qpu_set_branch_targets()
2345 memcpy(&slot->qpu, &s_inst->qpu, in qpu_set_branch_targets()
2346 sizeof(slot->qpu)); in qpu_set_branch_targets()
2351 branch->qpu.branch.offset += in qpu_set_branch_targets()
2392 v3d_qpu_dump(devinfo, &qinst->qpu); in v3d_qpu_schedule_instructions()
2417 thrsw->qpu.sig.thrsw = true; in v3d_qpu_schedule_instructions()