1097                 midgard_instruction **vadd,  in mir_schedule_zs_write()  argument
1108         midgard_instruction **units[] = { smul, vadd, vlut };  in mir_schedule_zs_write()
1175         midgard_instruction *vadd = NULL;  in mir_schedule_alu()  local
1189                         vadd = cond;  in mir_schedule_alu()
1228                 vadd = ralloc(ctx, midgard_instruction);  in mir_schedule_alu()
1229                 *vadd = v_mov(~0, make_compiler_temp(ctx));  in mir_schedule_alu()
1232                         vadd->op = midgard_alu_op_iadd;  in mir_schedule_alu()
1233                         vadd->src[0] = SSA_FIXED_REGISTER(31);  in mir_schedule_alu()
1234                         vadd->src_types[0] = nir_type_uint32;  in mir_schedule_alu()
1237                                 vadd->swizzle[0][c] = COMPONENT_X;  in mir_schedule_alu()
1239                         vadd->has_inline_constant = true;  in mir_schedule_alu()
1240                         vadd->inline_constant = 0;  in mir_schedule_alu()
1242                         vadd->src[1] = SSA_FIXED_REGISTER(1);  in mir_schedule_alu()
1243                         vadd->src_types[0] = nir_type_uint32;  in mir_schedule_alu()
1246                                 vadd->swizzle[1][c] = COMPONENT_W;  in mir_schedule_alu()
1249                 vadd->unit = UNIT_VADD;  in mir_schedule_alu()
1250                 vadd->mask = 0x1;  in mir_schedule_alu()
1251                 branch->dest = vadd->dest;  in mir_schedule_alu()
1252                 branch->dest_type = vadd->dest_type;  in mir_schedule_alu()
1256 …_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, false);  in mir_schedule_alu()
1259 …s_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, true);  in mir_schedule_alu()
1268                 mir_choose_alu(&vadd, instructions, liveness, worklist, len, &predicate, UNIT_VADD);  in mir_schedule_alu()
1275         mir_update_worklist(worklist, len, instructions, vadd);  in mir_schedule_alu()
1278         bool vadd_csel = vadd && OP_IS_CSEL(vadd->op);  in mir_schedule_alu()
1282                 midgard_instruction *ins = vadd_csel ? vadd : smul;  in mir_schedule_alu()
1299                 midgard_instruction *stages[] = { sadd, vadd, smul, vlut };  in mir_schedule_alu()
1372         midgard_instruction *stages[] = { vmul, sadd, vadd, smul, vlut, branch };  in mir_schedule_alu()