1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
35
36 #include <stdbool.h>
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "main/errors.h"
40 #include "brw_structs.h"
41 #include "brw_pipe_control.h"
42 #include "compiler/brw_compiler.h"
43
44 #include "isl/isl.h"
45 #include "blorp/blorp.h"
46
47 #include <brw_bufmgr.h>
48
49 #include "dev/intel_debug.h"
50 #include "common/intel_decoder.h"
51 #include "brw_screen.h"
52 #include "brw_tex_obj.h"
53 #include "perf/intel_perf.h"
54 #include "perf/intel_perf_query.h"
55
56 #ifdef __cplusplus
57 extern "C" {
58 #endif
59 /* Glossary:
60 *
61 * URB - uniform resource buffer. A mid-sized buffer which is
62 * partitioned between the fixed function units and used for passing
63 * values (vertices, primitives, constants) between them.
64 *
65 * CURBE - constant URB entry. An urb region (entry) used to hold
66 * constant values which the fixed function units can be instructed to
67 * preload into the GRF when spawning a thread.
68 *
69 * VUE - vertex URB entry. An urb entry holding a vertex and usually
70 * a vertex header. The header contains control information and
71 * things like primitive type, Begin/end flags and clip codes.
72 *
73 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
74 * unit holding rasterization and interpolation parameters.
75 *
76 * GRF - general register file. One of several register files
77 * addressable by programmed threads. The inputs (r0, payload, curbe,
78 * urb) of the thread are preloaded to this area before the thread is
79 * spawned. The registers are individually 8 dwords wide and suitable
80 * for general usage. Registers holding thread input values are not
81 * special and may be overwritten.
82 *
83 * MRF - message register file. Threads communicate (and terminate)
84 * by sending messages. Message parameters are placed in contiguous
85 * MRF registers. All program output is via these messages. URB
86 * entries are populated by sending a message to the shared URB
87 * function containing the new data, together with a control word,
88 * often an unmodified copy of R0.
89 *
90 * R0 - GRF register 0. Typically holds control information used when
91 * sending messages to other threads.
92 *
93 * EU or GFX4 EU: The name of the programmable subsystem of the
94 * i965 hardware. Threads are executed by the EU, the registers
95 * described above are part of the EU architecture.
96 *
97 * Fixed function units:
98 *
99 * CS - Command streamer. Notional first unit, little software
100 * interaction. Holds the URB entries used for constant data, ie the
101 * CURBEs.
102 *
103 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
104 * this unit is responsible for pulling vertices out of vertex buffers
105 * in vram and injecting them into the processing pipe as VUEs. If
106 * enabled, it first passes them to a VS thread which is a good place
107 * for the driver to implement any active vertex shader.
108 *
109 * HS - Hull Shader (Tessellation Control Shader)
110 *
111 * TE - Tessellation Engine (Tessellation Primitive Generation)
112 *
113 * DS - Domain Shader (Tessellation Evaluation Shader)
114 *
115 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
116 * enabled, incoming strips etc are passed to GS threads in individual
117 * line/triangle/point units. The GS thread may perform arbitary
118 * computation and emit whatever primtives with whatever vertices it
119 * chooses. This makes GS an excellent place to implement GL's
120 * unfilled polygon modes, though of course it is capable of much
121 * more. Additionally, GS is used to translate away primitives not
122 * handled by latter units, including Quads and Lineloops.
123 *
124 * CS - Clipper. Mesa's clipping algorithms are imported to run on
125 * this unit. The fixed function part performs cliptesting against
126 * the 6 fixed clipplanes and makes descisions on whether or not the
127 * incoming primitive needs to be passed to a thread for clipping.
128 * User clip planes are handled via cooperation with the VS thread.
129 *
130 * SF - Strips Fans or Setup: Triangles are prepared for
131 * rasterization. Interpolation coefficients are calculated.
132 * Flatshading and two-side lighting usually performed here.
133 *
134 * WM - Windower. Interpolation of vertex attributes performed here.
135 * Fragment shader implemented here. SIMD aspects of EU taken full
136 * advantage of, as pixels are processed in blocks of 16.
137 *
138 * CC - Color Calculator. No EU threads associated with this unit.
139 * Handles blending and (presumably) depth and stencil testing.
140 */
141
142 struct brw_context;
143 struct brw_inst;
144 struct brw_vs_prog_key;
145 struct brw_vue_prog_key;
146 struct brw_wm_prog_key;
147 struct brw_wm_prog_data;
148 struct brw_cs_prog_key;
149 struct brw_cs_prog_data;
150 struct brw_label;
151
152 enum brw_pipeline {
153 BRW_RENDER_PIPELINE,
154 BRW_COMPUTE_PIPELINE,
155
156 BRW_NUM_PIPELINES
157 };
158
159 enum brw_cache_id {
160 BRW_CACHE_FS_PROG,
161 BRW_CACHE_BLORP_PROG,
162 BRW_CACHE_SF_PROG,
163 BRW_CACHE_VS_PROG,
164 BRW_CACHE_FF_GS_PROG,
165 BRW_CACHE_GS_PROG,
166 BRW_CACHE_TCS_PROG,
167 BRW_CACHE_TES_PROG,
168 BRW_CACHE_CLIP_PROG,
169 BRW_CACHE_CS_PROG,
170
171 BRW_MAX_CACHE
172 };
173
174 enum gfx9_astc5x5_wa_tex_type {
175 GFX9_ASTC5X5_WA_TEX_TYPE_ASTC5x5 = 1 << 0,
176 GFX9_ASTC5X5_WA_TEX_TYPE_AUX = 1 << 1,
177 };
178
179 enum brw_state_id {
180 /* brw_cache_ids must come first - see brw_program_cache.c */
181 BRW_STATE_URB_FENCE = BRW_MAX_CACHE,
182 BRW_STATE_FRAGMENT_PROGRAM,
183 BRW_STATE_GEOMETRY_PROGRAM,
184 BRW_STATE_TESS_PROGRAMS,
185 BRW_STATE_VERTEX_PROGRAM,
186 BRW_STATE_REDUCED_PRIMITIVE,
187 BRW_STATE_PATCH_PRIMITIVE,
188 BRW_STATE_PRIMITIVE,
189 BRW_STATE_CONTEXT,
190 BRW_STATE_PSP,
191 BRW_STATE_SURFACES,
192 BRW_STATE_BINDING_TABLE_POINTERS,
193 BRW_STATE_INDICES,
194 BRW_STATE_VERTICES,
195 BRW_STATE_DEFAULT_TESS_LEVELS,
196 BRW_STATE_BATCH,
197 BRW_STATE_INDEX_BUFFER,
198 BRW_STATE_VS_CONSTBUF,
199 BRW_STATE_TCS_CONSTBUF,
200 BRW_STATE_TES_CONSTBUF,
201 BRW_STATE_GS_CONSTBUF,
202 BRW_STATE_PROGRAM_CACHE,
203 BRW_STATE_STATE_BASE_ADDRESS,
204 BRW_STATE_VUE_MAP_GEOM_OUT,
205 BRW_STATE_TRANSFORM_FEEDBACK,
206 BRW_STATE_RASTERIZER_DISCARD,
207 BRW_STATE_STATS_WM,
208 BRW_STATE_UNIFORM_BUFFER,
209 BRW_STATE_IMAGE_UNITS,
210 BRW_STATE_META_IN_PROGRESS,
211 BRW_STATE_PUSH_CONSTANT_ALLOCATION,
212 BRW_STATE_NUM_SAMPLES,
213 BRW_STATE_TEXTURE_BUFFER,
214 BRW_STATE_GFX4_UNIT_STATE,
215 BRW_STATE_CC_VP,
216 BRW_STATE_SF_VP,
217 BRW_STATE_CLIP_VP,
218 BRW_STATE_SAMPLER_STATE_TABLE,
219 BRW_STATE_VS_ATTRIB_WORKAROUNDS,
220 BRW_STATE_COMPUTE_PROGRAM,
221 BRW_STATE_CS_WORK_GROUPS,
222 BRW_STATE_URB_SIZE,
223 BRW_STATE_CC_STATE,
224 BRW_STATE_BLORP,
225 BRW_STATE_VIEWPORT_COUNT,
226 BRW_STATE_CONSERVATIVE_RASTERIZATION,
227 BRW_STATE_DRAW_CALL,
228 BRW_STATE_AUX,
229 BRW_NUM_STATE_BITS
230 };
231
232 /**
233 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
234 *
235 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
236 * When the currently bound shader program differs from the previous draw
237 * call, these will be flagged. They cover brw->{stage}_program and
238 * ctx->{Stage}Program->_Current.
239 *
240 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
241 * driver perspective. Even if the same shader is bound at the API level,
242 * we may need to switch between multiple versions of that shader to handle
243 * changes in non-orthagonal state.
244 *
245 * Additionally, multiple shader programs may have identical vertex shaders
246 * (for example), or compile down to the same code in the backend. We combine
247 * those into a single program cache entry.
248 *
249 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
250 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
251 */
252 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
253 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
254 * use the normal state upload paths), but the cache is still used. To avoid
255 * polluting the brw_program_cache code with special cases, we retain the
256 * dirty bit for now. It should eventually be removed.
257 */
258 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
259 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
260 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
261 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
262 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
263 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
264 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
265 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
266 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
267 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
268 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
269 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
270 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
271 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
272 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
273 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
274 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
275 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
276 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
277 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
278 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
279 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
280 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
281 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
282 /**
283 * Used for any batch entry with a relocated pointer that will be used
284 * by any 3D rendering.
285 */
286 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
287 /** \see brw.state.depth_region */
288 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
289 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
290 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
291 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
292 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
293 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
294 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
295 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
296 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
297 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
298 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
299 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
300 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
301 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
302 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
303 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
304 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
305 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
306 #define BRW_NEW_GFX4_UNIT_STATE (1ull << BRW_STATE_GFX4_UNIT_STATE)
307 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
308 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
309 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
310 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
311 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
312 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
313 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
314 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
315 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
316 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
317 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
318 #define BRW_NEW_DRAW_CALL (1ull << BRW_STATE_DRAW_CALL)
319 #define BRW_NEW_AUX_STATE (1ull << BRW_STATE_AUX)
320
321 struct brw_state_flags {
322 /** State update flags signalled by mesa internals */
323 GLuint mesa;
324 /**
325 * State update flags signalled as the result of brw_tracked_state updates
326 */
327 uint64_t brw;
328 };
329
330
331 /** Subclass of Mesa program */
332 struct brw_program {
333 struct gl_program program;
334 GLuint id;
335
336 bool compiled_once;
337 };
338
339 /** Number of texture sampler units */
340 #define BRW_MAX_TEX_UNIT 32
341
342 /** Max number of UBOs in a shader */
343 #define BRW_MAX_UBO 14
344
345 /** Max number of SSBOs in a shader */
346 #define BRW_MAX_SSBO 12
347
348 /** Max number of atomic counter buffer objects in a shader */
349 #define BRW_MAX_ABO 16
350
351 /** Max number of image uniforms in a shader */
352 #define BRW_MAX_IMAGES 32
353
354 /** Maximum number of actual buffers used for stream output */
355 #define BRW_MAX_SOL_BUFFERS 4
356
357 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
358 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
359 BRW_MAX_UBO + \
360 BRW_MAX_SSBO + \
361 BRW_MAX_ABO + \
362 BRW_MAX_IMAGES + \
363 2 + /* shader time, pull constants */ \
364 1 /* cs num work groups */)
365
366 struct brw_cache {
367 struct brw_context *brw;
368
369 struct brw_cache_item **items;
370 struct brw_bo *bo;
371 void *map;
372 GLuint size, n_items;
373
374 uint32_t next_offset;
375 };
376
377 #define perf_debug(...) do { \
378 static GLuint msg_id = 0; \
379 if (INTEL_DEBUG(DEBUG_PERF)) \
380 dbg_printf(__VA_ARGS__); \
381 if (brw->perf_debug) \
382 _mesa_gl_debugf(&brw->ctx, &msg_id, \
383 MESA_DEBUG_SOURCE_API, \
384 MESA_DEBUG_TYPE_PERFORMANCE, \
385 MESA_DEBUG_SEVERITY_MEDIUM, \
386 __VA_ARGS__); \
387 } while(0)
388
389 #define WARN_ONCE(cond, fmt...) do { \
390 if (unlikely(cond)) { \
391 static bool _warned = false; \
392 static GLuint msg_id = 0; \
393 if (!_warned) { \
394 fprintf(stderr, "WARNING: "); \
395 fprintf(stderr, fmt); \
396 _warned = true; \
397 \
398 _mesa_gl_debugf(ctx, &msg_id, \
399 MESA_DEBUG_SOURCE_API, \
400 MESA_DEBUG_TYPE_OTHER, \
401 MESA_DEBUG_SEVERITY_HIGH, fmt); \
402 } \
403 } \
404 } while (0)
405
406 /* Considered adding a member to this struct to document which flags
407 * an update might raise so that ordering of the state atoms can be
408 * checked or derived at runtime. Dropped the idea in favor of having
409 * a debug mode where the state is monitored for flags which are
410 * raised that have already been tested against.
411 */
412 struct brw_tracked_state {
413 struct brw_state_flags dirty;
414 void (*emit)( struct brw_context *brw );
415 };
416
417 enum shader_time_shader_type {
418 ST_NONE,
419 ST_VS,
420 ST_TCS,
421 ST_TES,
422 ST_GS,
423 ST_FS8,
424 ST_FS16,
425 ST_FS32,
426 ST_CS,
427 };
428
429 struct brw_vertex_buffer {
430 /** Buffer object containing the uploaded vertex data */
431 struct brw_bo *bo;
432 uint32_t offset;
433 uint32_t size;
434 /** Byte stride between elements in the uploaded array */
435 GLuint stride;
436 GLuint step_rate;
437 };
438 struct brw_vertex_element {
439 const struct gl_vertex_format *glformat;
440
441 int buffer;
442 bool is_dual_slot;
443 /** Offset of the first element within the buffer object */
444 unsigned int offset;
445 };
446
447 struct brw_query_object {
448 struct gl_query_object Base;
449
450 /** Last query BO associated with this query. */
451 struct brw_bo *bo;
452
453 /** Last index in bo with query data for this object. */
454 int last_index;
455
456 /** True if we know the batch has been flushed since we ended the query. */
457 bool flushed;
458 };
459
460 struct brw_reloc_list {
461 struct drm_i915_gem_relocation_entry *relocs;
462 int reloc_count;
463 int reloc_array_size;
464 };
465
466 struct brw_growing_bo {
467 struct brw_bo *bo;
468 uint32_t *map;
469 struct brw_bo *partial_bo;
470 uint32_t *partial_bo_map;
471 unsigned partial_bytes;
472 enum brw_memory_zone memzone;
473 };
474
475 struct brw_batch {
476 /** Current batchbuffer being queued up. */
477 struct brw_growing_bo batch;
478 /** Current statebuffer being queued up. */
479 struct brw_growing_bo state;
480
481 /** Last batchbuffer submitted to the hardware. Used for glFinish(). */
482 struct brw_bo *last_bo;
483
484 #ifdef DEBUG
485 uint16_t emit, total;
486 #endif
487 uint32_t *map_next;
488 uint32_t state_used;
489
490 bool use_shadow_copy;
491 bool use_batch_first;
492 bool needs_sol_reset;
493 bool state_base_address_emitted;
494 bool no_wrap;
495 bool contains_fence_signal;
496
497 struct brw_reloc_list batch_relocs;
498 struct brw_reloc_list state_relocs;
499 unsigned int valid_reloc_flags;
500
501 /** The validation list */
502 struct drm_i915_gem_exec_object2 *validation_list;
503 struct brw_bo **exec_bos;
504 int exec_count;
505 int exec_array_size;
506
507 /** The amount of aperture space (in bytes) used by all exec_bos */
508 uint64_t aperture_space;
509
510 struct {
511 uint32_t *map_next;
512 int batch_reloc_count;
513 int state_reloc_count;
514 int exec_count;
515 } saved;
516
517 /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */
518 struct hash_table_u64 *state_batch_sizes;
519
520 struct intel_batch_decode_ctx decoder;
521
522 /** A list of drm_i915_exec_fences to have execbuf signal or wait on */
523 struct util_dynarray exec_fences;
524 };
525
526 #define BRW_MAX_XFB_STREAMS 4
527
528 struct brw_transform_feedback_counter {
529 /**
530 * Index of the first entry of this counter within the primitive count BO.
531 * An entry is considered to be an N-tuple of 64bit values, where N is the
532 * number of vertex streams supported by the platform.
533 */
534 unsigned bo_start;
535
536 /**
537 * Index one past the last entry of this counter within the primitive
538 * count BO.
539 */
540 unsigned bo_end;
541
542 /**
543 * Primitive count values accumulated while this counter was active,
544 * excluding any entries buffered between \c bo_start and \c bo_end, which
545 * haven't been accounted for yet.
546 */
547 uint64_t accum[BRW_MAX_XFB_STREAMS];
548 };
549
550 static inline void
brw_reset_transform_feedback_counter(struct brw_transform_feedback_counter * counter)551 brw_reset_transform_feedback_counter(
552 struct brw_transform_feedback_counter *counter)
553 {
554 counter->bo_start = counter->bo_end;
555 memset(&counter->accum, 0, sizeof(counter->accum));
556 }
557
558 struct brw_transform_feedback_object {
559 struct gl_transform_feedback_object base;
560
561 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
562 struct brw_bo *offset_bo;
563
564 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
565 bool zero_offsets;
566
567 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
568 GLenum primitive_mode;
569
570 /**
571 * The maximum number of vertices that we can write without overflowing
572 * any of the buffers currently being used for transform feedback.
573 */
574 unsigned max_index;
575
576 struct brw_bo *prim_count_bo;
577
578 /**
579 * Count of primitives generated during this transform feedback operation.
580 */
581 struct brw_transform_feedback_counter counter;
582
583 /**
584 * Count of primitives generated during the previous transform feedback
585 * operation. Used to implement DrawTransformFeedback().
586 */
587 struct brw_transform_feedback_counter previous_counter;
588
589 /**
590 * Number of vertices written between last Begin/EndTransformFeedback().
591 *
592 * Used to implement DrawTransformFeedback().
593 */
594 uint64_t vertices_written[BRW_MAX_XFB_STREAMS];
595 bool vertices_written_valid;
596 };
597
598 /**
599 * Data shared between each programmable stage in the pipeline (vs, gs, and
600 * wm).
601 */
602 struct brw_stage_state
603 {
604 gl_shader_stage stage;
605 struct brw_stage_prog_data *prog_data;
606
607 /**
608 * Optional scratch buffer used to store spilled register values and
609 * variably-indexed GRF arrays.
610 *
611 * The contents of this buffer are short-lived so the same memory can be
612 * re-used at will for multiple shader programs (executed by the same fixed
613 * function). However reusing a scratch BO for which shader invocations
614 * are still in flight with a per-thread scratch slot size other than the
615 * original can cause threads with different scratch slot size and FFTID
616 * (which may be executed in parallel depending on the shader stage and
617 * hardware generation) to map to an overlapping region of the scratch
618 * space, which can potentially lead to mutual scratch space corruption.
619 * For that reason if you borrow this scratch buffer you should only be
620 * using the slot size given by the \c per_thread_scratch member below,
621 * unless you're taking additional measures to synchronize thread execution
622 * across slot size changes.
623 */
624 struct brw_bo *scratch_bo;
625
626 /**
627 * Scratch slot size allocated for each thread in the buffer object given
628 * by \c scratch_bo.
629 */
630 uint32_t per_thread_scratch;
631
632 /** Offset in the program cache to the program */
633 uint32_t prog_offset;
634
635 /** Offset in the batchbuffer to Gfx4-5 pipelined state (VS/WM/GS_STATE). */
636 uint32_t state_offset;
637
638 struct brw_bo *push_const_bo; /* NULL if using the batchbuffer */
639 uint32_t push_const_offset; /* Offset in the push constant BO or batch */
640 int push_const_size; /* in 256-bit register increments */
641
642 /* Binding table: pointers to SURFACE_STATE entries. */
643 uint32_t bind_bo_offset;
644 uint32_t surf_offset[BRW_MAX_SURFACES];
645
646 /** SAMPLER_STATE count and table offset */
647 uint32_t sampler_count;
648 uint32_t sampler_offset;
649
650 struct brw_image_param image_param[BRW_MAX_IMAGES];
651
652 /** Need to re-emit 3DSTATE_CONSTANT_XS? */
653 bool push_constants_dirty;
654 };
655
656 enum brw_predicate_state {
657 /* The first two states are used if we can determine whether to draw
658 * without having to look at the values in the query object buffer. This
659 * will happen if there is no conditional render in progress, if the query
660 * object is already completed or if something else has already added
661 * samples to the preliminary result such as via a BLT command.
662 */
663 BRW_PREDICATE_STATE_RENDER,
664 BRW_PREDICATE_STATE_DONT_RENDER,
665 /* In this case whether to draw or not depends on the result of an
666 * MI_PREDICATE command so the predicate enable bit needs to be checked.
667 */
668 BRW_PREDICATE_STATE_USE_BIT,
669 /* In this case, either MI_PREDICATE doesn't exist or we lack the
670 * necessary kernel features to use it. Stall for the query result.
671 */
672 BRW_PREDICATE_STATE_STALL_FOR_QUERY,
673 };
674
675 struct shader_times;
676
677 struct intel_l3_config;
678 struct intel_perf;
679
680 struct brw_uploader {
681 struct brw_bufmgr *bufmgr;
682 struct brw_bo *bo;
683 void *map;
684 uint32_t next_offset;
685 unsigned default_size;
686 };
687
688 /**
689 * brw_context is derived from gl_context.
690 */
691 struct brw_context
692 {
693 struct gl_context ctx; /**< base class, must be first field */
694
695 struct
696 {
697 /**
698 * Emit an MI_REPORT_PERF_COUNT command packet.
699 *
700 * This asks the GPU to write a report of the current OA counter values
701 * into @bo at the given offset and containing the given @report_id
702 * which we can cross-reference when parsing the report (gfx7+ only).
703 */
704 void (*emit_mi_report_perf_count)(struct brw_context *brw,
705 struct brw_bo *bo,
706 uint32_t offset_in_bytes,
707 uint32_t report_id);
708
709 void (*emit_compute_walker)(struct brw_context *brw);
710 void (*emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
711 struct brw_bo *bo, uint32_t offset,
712 uint64_t imm);
713 } vtbl;
714
715 struct brw_bufmgr *bufmgr;
716
717 uint32_t hw_ctx;
718
719 /**
720 * BO for post-sync nonzero writes for gfx6 workaround.
721 *
722 * This buffer also contains a marker + description of the driver. This
723 * buffer is added to all execbufs syscalls so that we can identify the
724 * driver that generated a hang by looking at the content of the buffer in
725 * the error state.
726 *
727 * Read/write should go at workaround_bo_offset in that buffer to avoid
728 * overriding the debug data.
729 */
730 struct brw_bo *workaround_bo;
731 uint32_t workaround_bo_offset;
732 uint8_t pipe_controls_since_last_cs_stall;
733
734 /**
735 * Set of struct brw_bo * that have been rendered to within this batchbuffer
736 * and would need flushing before being used from another cache domain that
737 * isn't coherent with it (i.e. the sampler).
738 */
739 struct hash_table *render_cache;
740
741 /**
742 * Set of struct brw_bo * that have been used as a depth buffer within this
743 * batchbuffer and would need flushing before being used from another cache
744 * domain that isn't coherent with it (i.e. the sampler).
745 */
746 struct set *depth_cache;
747
748 /**
749 * Number of resets observed in the system at context creation.
750 *
751 * This is tracked in the context so that we can determine that another
752 * reset has occurred.
753 */
754 uint32_t reset_count;
755
756 struct brw_batch batch;
757
758 struct brw_uploader upload;
759
760 /**
761 * Set if rendering has occurred to the drawable's front buffer.
762 *
763 * This is used in the DRI2 case to detect that glFlush should also copy
764 * the contents of the fake front buffer to the real front buffer.
765 */
766 bool front_buffer_dirty;
767
768 /**
769 * True if the __DRIdrawable's current __DRIimageBufferMask is
770 * __DRI_IMAGE_BUFFER_SHARED.
771 */
772 bool is_shared_buffer_bound;
773
774 /**
775 * True if a shared buffer is bound and it has received any rendering since
776 * the previous __DRImutableRenderBufferLoaderExtension::displaySharedBuffer().
777 */
778 bool is_shared_buffer_dirty;
779
780 /** Framerate throttling: @{ */
781 struct brw_bo *throttle_batch[2];
782
783 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
784 * frame of rendering to complete. This gives a very precise cap to the
785 * latency between input and output such that rendering never gets more
786 * than a frame behind the user. (With the caveat that we technically are
787 * not using the SwapBuffers itself as a barrier but the first batch
788 * submitted afterwards, which may be immediately prior to the next
789 * SwapBuffers.)
790 */
791 bool need_swap_throttle;
792
793 /** General throttling, not caught by throttling between SwapBuffers */
794 bool need_flush_throttle;
795 /** @} */
796
797 GLuint stats_wm;
798
799 /**
800 * drirc options:
801 * @{
802 */
803 bool always_flush_batch;
804 bool always_flush_cache;
805 bool disable_throttling;
806 bool precompile;
807 bool dual_color_blend_by_location;
808 /** @} */
809
810 GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
811
812 bool object_preemption; /**< Object level preemption enabled. */
813
814 GLenum reduced_primitive;
815
816 /**
817 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
818 * variable is set, this is the flag indicating to do expensive work that
819 * might lead to a perf_debug() call.
820 */
821 bool perf_debug;
822
823 uint64_t max_gtt_map_object_size;
824
825 bool has_hiz;
826 bool has_separate_stencil;
827 bool has_swizzling;
828
829 bool can_push_ubos;
830
831 /** Derived stencil states. */
832 bool stencil_enabled;
833 bool stencil_two_sided;
834 bool stencil_write_enabled;
835 /** Derived polygon state. */
836 bool polygon_front_bit; /**< 0=GL_CCW, 1=GL_CW */
837
838 struct isl_device isl_dev;
839
840 struct blorp_context blorp;
841
842 GLuint NewGLState;
843 struct {
844 struct brw_state_flags pipelines[BRW_NUM_PIPELINES];
845 } state;
846
847 enum brw_pipeline last_pipeline;
848
849 struct brw_cache cache;
850
851 /* Whether a meta-operation is in progress. */
852 bool meta_in_progress;
853
854 /* Whether the last depth/stencil packets were both NULL. */
855 bool no_depth_or_stencil;
856
857 /* The last PMA stall bits programmed. */
858 uint32_t pma_stall_bits;
859
860 /* Whether INTEL_black_render is active. */
861 bool frontend_noop;
862
863 struct {
864 struct {
865 /**
866 * Either the value of gl_BaseVertex for indexed draw calls or the
867 * value of the argument <first> for non-indexed draw calls for the
868 * current _mesa_prim.
869 */
870 int firstvertex;
871
872 /** The value of gl_BaseInstance for the current _mesa_prim. */
873 int gl_baseinstance;
874 } params;
875
876 /**
877 * Buffer and offset used for GL_ARB_shader_draw_parameters which will
878 * point to the indirect buffer for indirect draw calls.
879 */
880 struct brw_bo *draw_params_bo;
881 uint32_t draw_params_offset;
882
883 struct {
884 /**
885 * The value of gl_DrawID for the current _mesa_prim. This always comes
886 * in from it's own vertex buffer since it's not part of the indirect
887 * draw parameters.
888 */
889 int gl_drawid;
890
891 /**
892 * Stores if the current _mesa_prim is an indexed or non-indexed draw
893 * (~0/0). Useful to calculate gl_BaseVertex as an AND of firstvertex
894 * and is_indexed_draw.
895 */
896 int is_indexed_draw;
897 } derived_params;
898
899 /**
900 * Buffer and offset used for GL_ARB_shader_draw_parameters which contains
901 * parameters that are not present in the indirect buffer. They will go in
902 * their own vertex element.
903 */
904 struct brw_bo *derived_draw_params_bo;
905 uint32_t derived_draw_params_offset;
906
907 /**
908 * Pointer to the the buffer storing the indirect draw parameters. It
909 * currently only stores the number of requested draw calls but more
910 * parameters could potentially be added.
911 */
912 struct brw_bo *draw_params_count_bo;
913 uint32_t draw_params_count_offset;
914
915 /**
916 * Draw indirect buffer.
917 */
918 unsigned draw_indirect_stride;
919 GLsizeiptr draw_indirect_offset;
920 struct gl_buffer_object *draw_indirect_data;
921 } draw;
922
923 struct {
924 /**
925 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
926 * an indirect call, and num_work_groups_offset is valid. Otherwise,
927 * num_work_groups is set based on glDispatchCompute.
928 */
929 struct brw_bo *num_work_groups_bo;
930 GLintptr num_work_groups_offset;
931 const GLuint *num_work_groups;
932 /**
933 * This is only used alongside ARB_compute_variable_group_size when the
934 * local work group size is variable, otherwise it's NULL.
935 */
936 const GLuint *group_size;
937 } compute;
938
939 struct {
940 struct brw_vertex_element inputs[VERT_ATTRIB_MAX];
941 struct brw_vertex_buffer buffers[VERT_ATTRIB_MAX];
942
943 struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
944 GLuint nr_enabled;
945 GLuint nr_buffers;
946
947 /* Summary of size and varying of active arrays, so we can check
948 * for changes to this state:
949 */
950 bool index_bounds_valid;
951 unsigned int min_index, max_index;
952
953 /* Offset from start of vertex buffer so we can avoid redefining
954 * the same VB packed over and over again.
955 */
956 unsigned int start_vertex_bias;
957
958 /**
959 * Certain vertex attribute formats aren't natively handled by the
960 * hardware and require special VS code to fix up their values.
961 *
962 * These bitfields indicate which workarounds are needed.
963 */
964 uint8_t attrib_wa_flags[VERT_ATTRIB_MAX];
965
966 /* High bits of the last seen vertex buffer address (for workarounds). */
967 uint16_t last_bo_high_bits[33];
968 } vb;
969
970 struct {
971 /**
972 * Index buffer for this draw_prims call.
973 *
974 * Updates are signaled by BRW_NEW_INDICES.
975 */
976 const struct _mesa_index_buffer *ib;
977
978 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
979 struct brw_bo *bo;
980 uint32_t size;
981 unsigned index_size;
982
983 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
984 * avoid re-uploading the IB packet over and over if we're actually
985 * referencing the same index buffer.
986 */
987 unsigned int start_vertex_offset;
988
989 /* High bits of the last seen index buffer address (for workarounds). */
990 uint16_t last_bo_high_bits;
991
992 /* Used to understand is GPU state of primitive restart is up to date */
993 bool enable_cut_index;
994 } ib;
995
996 /* Active vertex program:
997 */
998 struct gl_program *programs[MESA_SHADER_STAGES];
999
1000 /**
1001 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1002 * that we don't have to reemit that state every time we change FBOs.
1003 */
1004 unsigned int num_samples;
1005
1006 /* BRW_NEW_URB_ALLOCATIONS:
1007 */
1008 struct {
1009 GLuint vsize; /* vertex size plus header in urb registers */
1010 GLuint gsize; /* GS output size in urb registers */
1011 GLuint hsize; /* Tessellation control output size in urb registers */
1012 GLuint dsize; /* Tessellation evaluation output size in urb registers */
1013 GLuint csize; /* constant buffer size in urb registers */
1014 GLuint sfsize; /* setup data size in urb registers */
1015
1016 bool constrained;
1017
1018 GLuint nr_vs_entries;
1019 GLuint nr_hs_entries;
1020 GLuint nr_ds_entries;
1021 GLuint nr_gs_entries;
1022 GLuint nr_clip_entries;
1023 GLuint nr_sf_entries;
1024 GLuint nr_cs_entries;
1025
1026 GLuint vs_start;
1027 GLuint hs_start;
1028 GLuint ds_start;
1029 GLuint gs_start;
1030 GLuint clip_start;
1031 GLuint sf_start;
1032 GLuint cs_start;
1033 /**
1034 * URB size in the current configuration. The units this is expressed
1035 * in are somewhat inconsistent, see intel_device_info::urb::size.
1036 *
1037 * FINISHME: Represent the URB size consistently in KB on all platforms.
1038 */
1039 GLuint size;
1040
1041 /* True if the most recently sent _3DSTATE_URB message allocated
1042 * URB space for the GS.
1043 */
1044 bool gs_present;
1045
1046 /* True if the most recently sent _3DSTATE_URB message allocated
1047 * URB space for the HS and DS.
1048 */
1049 bool tess_present;
1050 } urb;
1051
1052
1053 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1054 struct {
1055 GLuint wm_start; /**< pos of first wm const in CURBE buffer */
1056 GLuint wm_size; /**< number of float[4] consts, multiple of 16 */
1057 GLuint clip_start;
1058 GLuint clip_size;
1059 GLuint vs_start;
1060 GLuint vs_size;
1061 GLuint total_size;
1062
1063 /**
1064 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1065 * for upload to the CURBE.
1066 */
1067 struct brw_bo *curbe_bo;
1068 /** Offset within curbe_bo of space for current curbe entry */
1069 GLuint curbe_offset;
1070 } curbe;
1071
1072 /**
1073 * Layout of vertex data exiting the geometry portion of the pipleine.
1074 * This comes from the last enabled shader stage (GS, DS, or VS).
1075 *
1076 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1077 */
1078 struct brw_vue_map vue_map_geom_out;
1079
1080 struct {
1081 struct brw_stage_state base;
1082 } vs;
1083
1084 struct {
1085 struct brw_stage_state base;
1086 } tcs;
1087
1088 struct {
1089 struct brw_stage_state base;
1090 } tes;
1091
1092 struct {
1093 struct brw_stage_state base;
1094
1095 /**
1096 * True if the 3DSTATE_GS command most recently emitted to the 3D
1097 * pipeline enabled the GS; false otherwise.
1098 */
1099 bool enabled;
1100 } gs;
1101
1102 struct {
1103 struct brw_ff_gs_prog_data *prog_data;
1104
1105 bool prog_active;
1106 /** Offset in the program cache to the CLIP program pre-gfx6 */
1107 uint32_t prog_offset;
1108 uint32_t state_offset;
1109
1110 uint32_t bind_bo_offset;
1111 /**
1112 * Surface offsets for the binding table. We only need surfaces to
1113 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1114 * need in this case.
1115 */
1116 uint32_t surf_offset[BRW_MAX_SOL_BINDINGS];
1117 } ff_gs;
1118
1119 struct {
1120 struct brw_clip_prog_data *prog_data;
1121
1122 /** Offset in the program cache to the CLIP program pre-gfx6 */
1123 uint32_t prog_offset;
1124
1125 /* Offset in the batch to the CLIP state on pre-gfx6. */
1126 uint32_t state_offset;
1127
1128 /* As of gfx6, this is the offset in the batch to the CLIP VP,
1129 * instead of vp_bo.
1130 */
1131 uint32_t vp_offset;
1132
1133 /**
1134 * The number of viewports to use. If gl_ViewportIndex is written,
1135 * we can have up to ctx->Const.MaxViewports viewports. If not,
1136 * the viewport index is always 0, so we can only emit one.
1137 */
1138 uint8_t viewport_count;
1139 } clip;
1140
1141
1142 struct {
1143 struct brw_sf_prog_data *prog_data;
1144
1145 /** Offset in the program cache to the CLIP program pre-gfx6 */
1146 uint32_t prog_offset;
1147 uint32_t state_offset;
1148 uint32_t vp_offset;
1149 } sf;
1150
1151 struct {
1152 struct brw_stage_state base;
1153
1154 /**
1155 * Buffer object used in place of multisampled null render targets on
1156 * Gfx6. See brw_emit_null_surface_state().
1157 */
1158 struct brw_bo *multisampled_null_render_target_bo;
1159
1160 float offset_clamp;
1161 } wm;
1162
1163 struct {
1164 struct brw_stage_state base;
1165 } cs;
1166
1167 struct {
1168 uint32_t state_offset;
1169 uint32_t blend_state_offset;
1170 uint32_t depth_stencil_state_offset;
1171 uint32_t vp_offset;
1172 } cc;
1173
1174 struct {
1175 struct brw_query_object *obj;
1176 bool begin_emitted;
1177 } query;
1178
1179 struct {
1180 enum brw_predicate_state state;
1181 bool supported;
1182 } predicate;
1183
1184 struct intel_perf_context *perf_ctx;
1185
1186 int num_atoms[BRW_NUM_PIPELINES];
1187 const struct brw_tracked_state render_atoms[76];
1188 const struct brw_tracked_state compute_atoms[11];
1189
1190 const enum isl_format *mesa_to_isl_render_format;
1191 const bool *mesa_format_supports_render;
1192
1193 /* PrimitiveRestart */
1194 struct {
1195 bool in_progress;
1196 bool enable_cut_index;
1197 unsigned restart_index;
1198 } prim_restart;
1199
1200 /** Computed depth/stencil/hiz state from the current attached
1201 * renderbuffers, valid only during the drawing state upload loop after
1202 * brw_workaround_depthstencil_alignment().
1203 */
1204 struct {
1205 /* Inter-tile (page-aligned) byte offsets. */
1206 uint32_t depth_offset;
1207 /* Intra-tile x,y offsets for drawing to combined depth-stencil. Only
1208 * used for Gen < 6.
1209 */
1210 uint32_t tile_x, tile_y;
1211 } depthstencil;
1212
1213 uint32_t num_instances;
1214 int basevertex;
1215 int baseinstance;
1216
1217 struct {
1218 const struct intel_l3_config *config;
1219 } l3;
1220
1221 struct {
1222 struct brw_bo *bo;
1223 const char **names;
1224 int *ids;
1225 enum shader_time_shader_type *types;
1226 struct shader_times *cumulative;
1227 int num_entries;
1228 int max_entries;
1229 double report_time;
1230 } shader_time;
1231
1232 struct brw_fast_clear_state *fast_clear_state;
1233
1234 /* Array of aux usages to use for drawing. Aux usage for render targets is
1235 * a bit more complex than simply calling a single function so we need some
1236 * way of passing it form brw_draw.c to surface state setup.
1237 */
1238 enum isl_aux_usage draw_aux_usage[MAX_DRAW_BUFFERS];
1239
1240 enum gfx9_astc5x5_wa_tex_type gfx9_astc5x5_wa_tex_mask;
1241
1242 /** Last rendering scale argument provided to brw_emit_hashing_mode(). */
1243 unsigned current_hash_scale;
1244
1245 __DRIcontext *driContext;
1246 struct brw_screen *screen;
1247 void *mem_ctx;
1248 };
1249
1250 /* brw_clear.c */
1251 extern void brw_init_clear_functions(struct dd_function_table *functions);
1252
1253 /*======================================================================
1254 * brw_context.c
1255 */
1256 extern const char *const brw_vendor_string;
1257
1258 extern const char *
1259 brw_get_renderer_string(const struct brw_screen *screen);
1260
1261 enum {
1262 DRI_CONF_BO_REUSE_DISABLED,
1263 DRI_CONF_BO_REUSE_ALL
1264 };
1265
1266 void brw_update_renderbuffers(__DRIcontext *context,
1267 __DRIdrawable *drawable);
1268 void brw_prepare_render(struct brw_context *brw);
1269
1270 void gfx9_apply_single_tex_astc5x5_wa(struct brw_context *brw,
1271 mesa_format format,
1272 enum isl_aux_usage aux_usage);
1273
1274 void brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
1275 bool *draw_aux_buffer_disabled);
1276
1277 void brw_resolve_for_dri2_flush(struct brw_context *brw,
1278 __DRIdrawable *drawable);
1279
1280 GLboolean brw_create_context(gl_api api,
1281 const struct gl_config *mesaVis,
1282 __DRIcontext *driContextPriv,
1283 const struct __DriverContextConfig *ctx_config,
1284 unsigned *error,
1285 void *sharedContextPrivate);
1286
1287 /*======================================================================
1288 * brw_misc_state.c
1289 */
1290 void brw_workaround_depthstencil_alignment(struct brw_context *brw,
1291 GLbitfield clear_mask);
1292 void brw_emit_hashing_mode(struct brw_context *brw, unsigned width,
1293 unsigned height, unsigned scale);
1294
1295 /* brw_object_purgeable.c */
1296 void brw_init_object_purgeable_functions(struct dd_function_table *functions);
1297
1298 /*======================================================================
1299 * brw_queryobj.c
1300 */
1301 void brw_init_common_queryobj_functions(struct dd_function_table *functions);
1302 void gfx4_init_queryobj_functions(struct dd_function_table *functions);
1303 void brw_emit_query_begin(struct brw_context *brw);
1304 void brw_emit_query_end(struct brw_context *brw);
1305 void brw_query_counter(struct gl_context *ctx, struct gl_query_object *q);
1306 bool brw_is_query_pipelined(struct brw_query_object *query);
1307 uint64_t brw_raw_timestamp_delta(struct brw_context *brw,
1308 uint64_t time0, uint64_t time1);
1309
1310 /** gfx6_queryobj.c */
1311 void gfx6_init_queryobj_functions(struct dd_function_table *functions);
1312 void brw_write_timestamp(struct brw_context *brw, struct brw_bo *bo, int idx);
1313 void brw_write_depth_count(struct brw_context *brw, struct brw_bo *bo, int idx);
1314
1315 /** hsw_queryobj.c */
1316 void hsw_overflow_result_to_gpr0(struct brw_context *brw,
1317 struct brw_query_object *query,
1318 int count);
1319 void hsw_init_queryobj_functions(struct dd_function_table *functions);
1320
1321 /** brw_conditional_render.c */
1322 void brw_init_conditional_render_functions(struct dd_function_table *functions);
1323 bool brw_check_conditional_render(struct brw_context *brw);
1324
1325 /** brw_batch.c */
1326 void brw_load_register_mem(struct brw_context *brw,
1327 uint32_t reg,
1328 struct brw_bo *bo,
1329 uint32_t offset);
1330 void brw_load_register_mem64(struct brw_context *brw,
1331 uint32_t reg,
1332 struct brw_bo *bo,
1333 uint32_t offset);
1334 void brw_store_register_mem32(struct brw_context *brw,
1335 struct brw_bo *bo, uint32_t reg, uint32_t offset);
1336 void brw_store_register_mem64(struct brw_context *brw,
1337 struct brw_bo *bo, uint32_t reg, uint32_t offset);
1338 void brw_load_register_imm32(struct brw_context *brw,
1339 uint32_t reg, uint32_t imm);
1340 void brw_load_register_imm64(struct brw_context *brw,
1341 uint32_t reg, uint64_t imm);
1342 void brw_load_register_reg(struct brw_context *brw, uint32_t dst,
1343 uint32_t src);
1344 void brw_load_register_reg64(struct brw_context *brw, uint32_t dst,
1345 uint32_t src);
1346 void brw_store_data_imm32(struct brw_context *brw, struct brw_bo *bo,
1347 uint32_t offset, uint32_t imm);
1348 void brw_store_data_imm64(struct brw_context *brw, struct brw_bo *bo,
1349 uint32_t offset, uint64_t imm);
1350
1351 /*======================================================================
1352 * intel_tex_validate.c
1353 */
1354 void brw_validate_textures( struct brw_context *brw );
1355
1356
1357 /*======================================================================
1358 * brw_program.c
1359 */
1360 void brw_init_frag_prog_functions(struct dd_function_table *functions);
1361
1362 void brw_get_scratch_bo(struct brw_context *brw,
1363 struct brw_bo **scratch_bo, int size);
1364 void brw_alloc_stage_scratch(struct brw_context *brw,
1365 struct brw_stage_state *stage_state,
1366 unsigned per_thread_size);
1367 void brw_init_shader_time(struct brw_context *brw);
1368 int brw_get_shader_time_index(struct brw_context *brw,
1369 struct gl_program *prog,
1370 enum shader_time_shader_type type,
1371 bool is_glsl_sh);
1372 void brw_collect_and_report_shader_time(struct brw_context *brw);
1373 void brw_destroy_shader_time(struct brw_context *brw);
1374
1375 /* brw_urb.c
1376 */
1377 void brw_calculate_urb_fence(struct brw_context *brw, unsigned csize,
1378 unsigned vsize, unsigned sfsize);
1379 void brw_upload_urb_fence(struct brw_context *brw);
1380
1381 /* brw_curbe.c
1382 */
1383 void brw_upload_cs_urb_state(struct brw_context *brw);
1384
1385 /* brw_vs.c */
1386 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
1387
1388 /* brw_draw_upload.c */
1389 unsigned brw_get_vertex_surface_type(struct brw_context *brw,
1390 const struct gl_vertex_format *glformat);
1391
1392 static inline unsigned
brw_get_index_type(unsigned index_size)1393 brw_get_index_type(unsigned index_size)
1394 {
1395 /* The hw needs 0x00, 0x01, and 0x02 for ubyte, ushort, and uint,
1396 * respectively.
1397 */
1398 return index_size >> 1;
1399 }
1400
1401 void brw_prepare_vertices(struct brw_context *brw);
1402
1403 /* brw_wm_surface_state.c */
1404 void brw_update_buffer_texture_surface(struct gl_context *ctx,
1405 unsigned unit,
1406 uint32_t *surf_offset);
1407 void
1408 brw_update_sol_surface(struct brw_context *brw,
1409 struct gl_buffer_object *buffer_obj,
1410 uint32_t *out_offset, unsigned num_vector_components,
1411 unsigned stride_dwords, unsigned offset_dwords);
1412 void brw_upload_ubo_surfaces(struct brw_context *brw, struct gl_program *prog,
1413 struct brw_stage_state *stage_state,
1414 struct brw_stage_prog_data *prog_data);
1415 void brw_upload_image_surfaces(struct brw_context *brw,
1416 const struct gl_program *prog,
1417 struct brw_stage_state *stage_state,
1418 struct brw_stage_prog_data *prog_data);
1419
1420 /* brw_surface_formats.c */
1421 void brw_screen_init_surface_formats(struct brw_screen *screen);
1422 void brw_init_surface_formats(struct brw_context *brw);
1423 bool brw_render_target_supported(struct brw_context *brw,
1424 struct gl_renderbuffer *rb);
1425 uint32_t brw_depth_format(struct brw_context *brw, mesa_format format);
1426
1427 /* brw_performance_query.c */
1428 void brw_init_performance_queries(struct brw_context *brw);
1429
1430 /* intel_extensions.c */
1431 extern void brw_init_extensions(struct gl_context *ctx);
1432
1433 /* intel_state.c */
1434 extern int brw_translate_shadow_compare_func(GLenum func);
1435 extern int brw_translate_compare_func(GLenum func);
1436 extern int brw_translate_stencil_op(GLenum op);
1437
1438 /* brw_sync.c */
1439 void brw_init_syncobj_functions(struct dd_function_table *functions);
1440
1441 /* gfx6_sol.c */
1442 struct gl_transform_feedback_object *
1443 brw_new_transform_feedback(struct gl_context *ctx, GLuint name);
1444 void
1445 brw_delete_transform_feedback(struct gl_context *ctx,
1446 struct gl_transform_feedback_object *obj);
1447 void
1448 brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1449 struct gl_transform_feedback_object *obj);
1450 void
1451 brw_end_transform_feedback(struct gl_context *ctx,
1452 struct gl_transform_feedback_object *obj);
1453 void
1454 brw_pause_transform_feedback(struct gl_context *ctx,
1455 struct gl_transform_feedback_object *obj);
1456 void
1457 brw_resume_transform_feedback(struct gl_context *ctx,
1458 struct gl_transform_feedback_object *obj);
1459 void
1460 brw_save_primitives_written_counters(struct brw_context *brw,
1461 struct brw_transform_feedback_object *obj);
1462 GLsizei
1463 brw_get_transform_feedback_vertex_count(struct gl_context *ctx,
1464 struct gl_transform_feedback_object *obj,
1465 GLuint stream);
1466
1467 /* gfx7_sol_state.c */
1468 void
1469 gfx7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1470 struct gl_transform_feedback_object *obj);
1471 void
1472 gfx7_end_transform_feedback(struct gl_context *ctx,
1473 struct gl_transform_feedback_object *obj);
1474 void
1475 gfx7_pause_transform_feedback(struct gl_context *ctx,
1476 struct gl_transform_feedback_object *obj);
1477 void
1478 gfx7_resume_transform_feedback(struct gl_context *ctx,
1479 struct gl_transform_feedback_object *obj);
1480
1481 /* hsw_sol.c */
1482 void
1483 hsw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1484 struct gl_transform_feedback_object *obj);
1485 void
1486 hsw_end_transform_feedback(struct gl_context *ctx,
1487 struct gl_transform_feedback_object *obj);
1488 void
1489 hsw_pause_transform_feedback(struct gl_context *ctx,
1490 struct gl_transform_feedback_object *obj);
1491 void
1492 hsw_resume_transform_feedback(struct gl_context *ctx,
1493 struct gl_transform_feedback_object *obj);
1494
1495 /* brw_blorp_blit.cpp */
1496 GLbitfield
1497 brw_blorp_framebuffer(struct brw_context *brw,
1498 struct gl_framebuffer *readFb,
1499 struct gl_framebuffer *drawFb,
1500 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
1501 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
1502 GLbitfield mask, GLenum filter);
1503
1504 bool
1505 brw_blorp_copytexsubimage(struct brw_context *brw,
1506 struct gl_renderbuffer *src_rb,
1507 struct gl_texture_image *dst_image,
1508 int slice,
1509 int srcX0, int srcY0,
1510 int dstX0, int dstY0,
1511 int width, int height);
1512
1513 /* brw_generate_mipmap.c */
1514 void brw_generate_mipmap(struct gl_context *ctx, GLenum target,
1515 struct gl_texture_object *tex_obj);
1516
1517 void
1518 gfx6_get_sample_position(struct gl_context *ctx,
1519 struct gl_framebuffer *fb,
1520 GLuint index,
1521 GLfloat *result);
1522
1523 /* gfx8_multisample_state.c */
1524 void gfx8_emit_3dstate_sample_pattern(struct brw_context *brw);
1525
1526 /* gfx7_l3_state.c */
1527 void brw_emit_l3_state(struct brw_context *brw);
1528
1529 /* gfx7_urb.c */
1530 void
1531 gfx7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
1532 unsigned hs_size, unsigned ds_size,
1533 unsigned gs_size, unsigned fs_size);
1534
1535 void
1536 gfx6_upload_urb(struct brw_context *brw, unsigned vs_size,
1537 bool gs_present, unsigned gs_size);
1538 void
1539 gfx7_upload_urb(struct brw_context *brw, unsigned vs_size,
1540 bool gs_present, bool tess_present);
1541
1542 /* brw_reset.c */
1543 extern GLenum
1544 brw_get_graphics_reset_status(struct gl_context *ctx);
1545 void
1546 brw_check_for_reset(struct brw_context *brw);
1547
1548 /* brw_compute.c */
1549 extern void
1550 brw_init_compute_functions(struct dd_function_table *functions);
1551
1552 /* brw_program_binary.c */
1553 extern void
1554 brw_program_binary_init(unsigned device_id);
1555 extern void
1556 brw_get_program_binary_driver_sha1(struct gl_context *ctx, uint8_t *sha1);
1557 void brw_serialize_program_binary(struct gl_context *ctx,
1558 struct gl_shader_program *sh_prog,
1559 struct gl_program *prog);
1560 extern void
1561 brw_deserialize_program_binary(struct gl_context *ctx,
1562 struct gl_shader_program *shProg,
1563 struct gl_program *prog);
1564 void
1565 brw_program_serialize_nir(struct gl_context *ctx, struct gl_program *prog);
1566 void
1567 brw_program_deserialize_driver_blob(struct gl_context *ctx,
1568 struct gl_program *prog,
1569 gl_shader_stage stage);
1570
1571 /*======================================================================
1572 * Inline conversion functions. These are better-typed than the
1573 * macros used previously:
1574 */
1575 static inline struct brw_context *
brw_context(struct gl_context * ctx)1576 brw_context( struct gl_context *ctx )
1577 {
1578 return (struct brw_context *)ctx;
1579 }
1580
1581 static inline struct brw_program *
brw_program(struct gl_program * p)1582 brw_program(struct gl_program *p)
1583 {
1584 return (struct brw_program *) p;
1585 }
1586
1587 static inline const struct brw_program *
brw_program_const(const struct gl_program * p)1588 brw_program_const(const struct gl_program *p)
1589 {
1590 return (const struct brw_program *) p;
1591 }
1592
1593 static inline bool
brw_depth_writes_enabled(const struct brw_context * brw)1594 brw_depth_writes_enabled(const struct brw_context *brw)
1595 {
1596 const struct gl_context *ctx = &brw->ctx;
1597
1598 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1599 * because it would just overwrite the existing depth value with itself.
1600 *
1601 * These bonus depth writes not only use bandwidth, but they also can
1602 * prevent early depth processing. For example, if the pixel shader
1603 * discards, the hardware must invoke the to determine whether or not
1604 * to do the depth write. If writes are disabled, we may still be able
1605 * to do the depth test before the shader, and skip the shader execution.
1606 *
1607 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1608 * a programming note saying to disable depth writes for EQUAL.
1609 */
1610 return ctx->Depth.Test && ctx->Depth.Mask && ctx->Depth.Func != GL_EQUAL;
1611 }
1612
1613 void
1614 brw_emit_depthbuffer(struct brw_context *brw);
1615
1616 uint32_t get_hw_prim_for_gl_prim(int mode);
1617
1618 void
1619 gfx6_upload_push_constants(struct brw_context *brw,
1620 const struct gl_program *prog,
1621 const struct brw_stage_prog_data *prog_data,
1622 struct brw_stage_state *stage_state);
1623
1624 bool
1625 gfx9_use_linear_1d_layout(const struct brw_context *brw,
1626 const struct brw_mipmap_tree *mt);
1627
1628 /* brw_queryformat.c */
1629 void brw_query_internal_format(struct gl_context *ctx, GLenum target,
1630 GLenum internalFormat, GLenum pname,
1631 GLint *params);
1632
1633 #ifdef __cplusplus
1634 }
1635 #endif
1636
1637 #endif
1638