| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 181 const TargetRegisterClass *DstRC = Register::isVirtualRegister(DstReg) in getCopyRegClasses() local
189 const TargetRegisterClass *DstRC, in isVGPRToSGPRCopy()
196 const TargetRegisterClass *DstRC, in isSGPRToVGPRCopy()
261 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
614 const TargetRegisterClass *SrcRC, *DstRC; in runOnMachineFunction() local
676 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local
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| D | AMDGPUInstructionSelector.cpp | 498 const TargetRegisterClass *DstRC = in selectG_MERGE_VALUES() local
556 const TargetRegisterClass *DstRC = in selectG_UNMERGE_VALUES() local
605 const TargetRegisterClass *DstRC = in selectG_INSERT() local
1272 const TargetRegisterClass *DstRC in selectG_TRUNC() local
1483 const TargetRegisterClass *DstRC = in selectG_CONSTANT() local
1653 const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB, in selectG_PTR_MASK() local
1715 const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(DstTy, *DstRB, in selectG_EXTRACT_VECTOR_ELT() local
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| D | SIInstrInfo.cpp | 487 const TargetRegisterClass *DstRC = Register::isVirtualRegister(Reg) in shouldClusterMemOps() local
2177 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); in insertSelect() local
3424 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx); in verifyInstruction() local
4283 const TargetRegisterClass *DstRC, in legalizeGenericOperand()
4606 const TargetRegisterClass *DstRC = getOpRegClass(MI, 0); in legalizeOperands() local
4634 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in legalizeOperands() local
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| D | SIRegisterInfo.cpp | 1704 const TargetRegisterClass *DstRC, in shouldCoalesce()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 249 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); in selectCopy() local
277 const TargetRegisterClass *DstRC = in selectCopy() local
683 static bool canTurnIntoCOPY(const TargetRegisterClass *DstRC, in canTurnIntoCOPY()
692 const TargetRegisterClass *DstRC, const unsigned SrcReg, in selectTurnIntoCOPY()
727 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt() local
809 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectZext() local
902 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectAnyext() local
1216 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI); in emitExtractSubreg() local
1256 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI); in emitInsertSubreg() local
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| D | X86InstrInfo.cpp | 5579 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); in unfoldMemoryOperand() local
5662 const TargetRegisterClass *DstRC = nullptr; in unfoldMemoryOperand() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | DetectDeadLanes.cpp | 154 const TargetRegisterClass *DstRC, in isCrossCopy()
438 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes() local
487 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput() local
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| D | RegisterCoalescer.cpp | 466 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters() local
1325 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in reMaterializeTrivialDef() local
1798 auto DstRC = MRI->getRegClass(CP.getDstReg()); in joinCopy() local
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| D | PeepholeOptimizer.cpp | 474 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXCopy.cpp | 120 const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass; in processBlock() local
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| D | PPCVSXSwapRemoval.cpp | 898 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in handleSpecialSwappables() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | InstructionSelect.cpp | 175 auto DstRC = MRI.getRegClass(DstReg); in runOnMachineFunction() local
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| D | CombinerHelper.cpp | 96 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in matchCombineCopy() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.cpp | 279 const TargetRegisterClass *DstRC, in shouldCoalesce()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 242 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce()
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| D | HexagonGenInsert.cpp | 686 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR); in isValidInsertForm() local
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| D | HexagonBitSimplify.cpp | 437 auto &DstRC = *MRI.getRegClass(I.getOperand(0).getReg()); in parseRegSequence() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 681 const TargetRegisterClass *DstRC; in selectCopy() local
2055 const TargetRegisterClass *DstRC = in select() local
2380 const TargetRegisterClass *DstRC = in select() local
2779 unsigned EltSize, const TargetRegisterClass *DstRC, Register Scalar, in emitScalarToVector()
2845 auto *DstRC = &AArch64::GPR64RegClass; in selectMergeValues() local
2912 const TargetRegisterClass *DstRC = in emitExtractVectorElt() local
3398 const TargetRegisterClass *DstRC = in emitVectorConcat() local
3869 const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass; in emitLaneInsert() local
3984 const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass; in selectBuildVector() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 343 const TargetRegisterClass *DstRC, in shouldCoalesce()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local
614 const TargetRegisterClass *DstRC = in EmitCopyToRegClassNode() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 839 const TargetRegisterClass *DstRC, in shouldCoalesce()
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| D | ARMFastISel.cpp | 2054 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); in FinishCall() local
2074 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); in FinishCall() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 262 const TargetRegisterClass *DstRC = RegInfo.getMinimalPhysRegClass(Dst); in expandCopyACC() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 949 const TargetRegisterClass *DstRC, in shouldCoalesce()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 1206 const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass; in emitBuildPairF64Pseudo() local
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