1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/module.h>
12 #include <linux/ioport.h>
13 #include <linux/init.h>
14 #include <linux/console.h>
15 #include <linux/sysrq.h>
16 #include <linux/platform_device.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/ktime.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/rational.h>
26 #include <linux/slab.h>
27 #include <linux/of.h>
28 #include <linux/of_device.h>
29 #include <linux/io.h>
30 #include <linux/dma-mapping.h>
31
32 #include <asm/irq.h>
33 #include <linux/platform_data/serial-imx.h>
34 #include <linux/platform_data/dma-imx.h>
35
36 #include "serial_mctrl_gpio.h"
37
38 /* Register definitions */
39 #define URXD0 0x0 /* Receiver Register */
40 #define URTX0 0x40 /* Transmitter Register */
41 #define UCR1 0x80 /* Control Register 1 */
42 #define UCR2 0x84 /* Control Register 2 */
43 #define UCR3 0x88 /* Control Register 3 */
44 #define UCR4 0x8c /* Control Register 4 */
45 #define UFCR 0x90 /* FIFO Control Register */
46 #define USR1 0x94 /* Status Register 1 */
47 #define USR2 0x98 /* Status Register 2 */
48 #define UESC 0x9c /* Escape Character Register */
49 #define UTIM 0xa0 /* Escape Timer Register */
50 #define UBIR 0xa4 /* BRM Incremental Register */
51 #define UBMR 0xa8 /* BRM Modulator Register */
52 #define UBRC 0xac /* Baud Rate Count Register */
53 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
54 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
55 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
56
57 /* UART Control Register Bit Fields.*/
58 #define URXD_DUMMY_READ (1<<16)
59 #define URXD_CHARRDY (1<<15)
60 #define URXD_ERR (1<<14)
61 #define URXD_OVRRUN (1<<13)
62 #define URXD_FRMERR (1<<12)
63 #define URXD_BRK (1<<11)
64 #define URXD_PRERR (1<<10)
65 #define URXD_RX_DATA (0xFF<<0)
66 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
67 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
68 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
69 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
70 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
71 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
72 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
73 #define UCR1_IREN (1<<7) /* Infrared interface enable */
74 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
75 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
76 #define UCR1_SNDBRK (1<<4) /* Send break */
77 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
78 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
79 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
80 #define UCR1_DOZE (1<<1) /* Doze */
81 #define UCR1_UARTEN (1<<0) /* UART enabled */
82 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
83 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
84 #define UCR2_CTSC (1<<13) /* CTS pin control */
85 #define UCR2_CTS (1<<12) /* Clear to send */
86 #define UCR2_ESCEN (1<<11) /* Escape enable */
87 #define UCR2_PREN (1<<8) /* Parity enable */
88 #define UCR2_PROE (1<<7) /* Parity odd/even */
89 #define UCR2_STPB (1<<6) /* Stop */
90 #define UCR2_WS (1<<5) /* Word size */
91 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
92 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
93 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
94 #define UCR2_RXEN (1<<1) /* Receiver enabled */
95 #define UCR2_SRST (1<<0) /* SW reset */
96 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
97 #define UCR3_PARERREN (1<<12) /* Parity enable */
98 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
99 #define UCR3_DSR (1<<10) /* Data set ready */
100 #define UCR3_DCD (1<<9) /* Data carrier detect */
101 #define UCR3_RI (1<<8) /* Ring indicator */
102 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
103 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
104 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
105 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
106 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
107 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
108 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
109 #define UCR3_BPEN (1<<0) /* Preset registers enable */
110 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
111 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
112 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
113 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
114 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
115 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
116 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
117 #define UCR4_IRSC (1<<5) /* IR special case */
118 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
119 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
120 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
121 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
122 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
123 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
124 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
125 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
126 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
127 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
128 #define USR1_RTSS (1<<14) /* RTS pin status */
129 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
130 #define USR1_RTSD (1<<12) /* RTS delta */
131 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
132 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
133 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
134 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
135 #define USR1_DTRD (1<<7) /* DTR Delta */
136 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
137 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
138 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
139 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
140 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
141 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
142 #define USR2_IDLE (1<<12) /* Idle condition */
143 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
144 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
145 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
146 #define USR2_WAKE (1<<7) /* Wake */
147 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
148 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
149 #define USR2_TXDC (1<<3) /* Transmitter complete */
150 #define USR2_BRCD (1<<2) /* Break condition */
151 #define USR2_ORE (1<<1) /* Overrun error */
152 #define USR2_RDR (1<<0) /* Recv data ready */
153 #define UTS_FRCPERR (1<<13) /* Force parity error */
154 #define UTS_LOOP (1<<12) /* Loop tx and rx */
155 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
156 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
157 #define UTS_TXFULL (1<<4) /* TxFIFO full */
158 #define UTS_RXFULL (1<<3) /* RxFIFO full */
159 #define UTS_SOFTRST (1<<0) /* Software reset */
160
161 /* We've been assigned a range on the "Low-density serial ports" major */
162 #define SERIAL_IMX_MAJOR 207
163 #define MINOR_START 16
164 #define DEV_NAME "ttymxc"
165
166 /*
167 * This determines how often we check the modem status signals
168 * for any change. They generally aren't connected to an IRQ
169 * so we have to poll them. We also check immediately before
170 * filling the TX fifo incase CTS has been dropped.
171 */
172 #define MCTRL_TIMEOUT (250*HZ/1000)
173
174 #define DRIVER_NAME "IMX-uart"
175
176 #define UART_NR 8
177
178 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
179 enum imx_uart_type {
180 IMX1_UART,
181 IMX21_UART,
182 IMX53_UART,
183 IMX6Q_UART,
184 };
185
186 /* device type dependent stuff */
187 struct imx_uart_data {
188 unsigned uts_reg;
189 enum imx_uart_type devtype;
190 };
191
192 enum imx_tx_state {
193 OFF,
194 WAIT_AFTER_RTS,
195 SEND,
196 WAIT_AFTER_SEND,
197 };
198
199 struct imx_port {
200 struct uart_port port;
201 struct timer_list timer;
202 unsigned int old_status;
203 unsigned int have_rtscts:1;
204 unsigned int have_rtsgpio:1;
205 unsigned int dte_mode:1;
206 unsigned int inverted_tx:1;
207 unsigned int inverted_rx:1;
208 struct clk *clk_ipg;
209 struct clk *clk_per;
210 const struct imx_uart_data *devdata;
211
212 struct mctrl_gpios *gpios;
213
214 /* shadow registers */
215 unsigned int ucr1;
216 unsigned int ucr2;
217 unsigned int ucr3;
218 unsigned int ucr4;
219 unsigned int ufcr;
220
221 /* DMA fields */
222 unsigned int dma_is_enabled:1;
223 unsigned int dma_is_rxing:1;
224 unsigned int dma_is_txing:1;
225 struct dma_chan *dma_chan_rx, *dma_chan_tx;
226 struct scatterlist rx_sgl, tx_sgl[2];
227 void *rx_buf;
228 struct circ_buf rx_ring;
229 unsigned int rx_periods;
230 dma_cookie_t rx_cookie;
231 unsigned int tx_bytes;
232 unsigned int dma_tx_nents;
233 unsigned int saved_reg[10];
234 bool context_saved;
235
236 enum imx_tx_state tx_state;
237 struct hrtimer trigger_start_tx;
238 struct hrtimer trigger_stop_tx;
239 };
240
241 struct imx_port_ucrs {
242 unsigned int ucr1;
243 unsigned int ucr2;
244 unsigned int ucr3;
245 };
246
247 static struct imx_uart_data imx_uart_devdata[] = {
248 [IMX1_UART] = {
249 .uts_reg = IMX1_UTS,
250 .devtype = IMX1_UART,
251 },
252 [IMX21_UART] = {
253 .uts_reg = IMX21_UTS,
254 .devtype = IMX21_UART,
255 },
256 [IMX53_UART] = {
257 .uts_reg = IMX21_UTS,
258 .devtype = IMX53_UART,
259 },
260 [IMX6Q_UART] = {
261 .uts_reg = IMX21_UTS,
262 .devtype = IMX6Q_UART,
263 },
264 };
265
266 static const struct platform_device_id imx_uart_devtype[] = {
267 {
268 .name = "imx1-uart",
269 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
270 }, {
271 .name = "imx21-uart",
272 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
273 }, {
274 .name = "imx53-uart",
275 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
276 }, {
277 .name = "imx6q-uart",
278 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
279 }, {
280 /* sentinel */
281 }
282 };
283 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
284
285 static const struct of_device_id imx_uart_dt_ids[] = {
286 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
287 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
288 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
289 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
290 { /* sentinel */ }
291 };
292 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
293
imx_uart_writel(struct imx_port * sport,u32 val,u32 offset)294 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
295 {
296 switch (offset) {
297 case UCR1:
298 sport->ucr1 = val;
299 break;
300 case UCR2:
301 sport->ucr2 = val;
302 break;
303 case UCR3:
304 sport->ucr3 = val;
305 break;
306 case UCR4:
307 sport->ucr4 = val;
308 break;
309 case UFCR:
310 sport->ufcr = val;
311 break;
312 default:
313 break;
314 }
315 writel(val, sport->port.membase + offset);
316 }
317
imx_uart_readl(struct imx_port * sport,u32 offset)318 static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
319 {
320 switch (offset) {
321 case UCR1:
322 return sport->ucr1;
323 break;
324 case UCR2:
325 /*
326 * UCR2_SRST is the only bit in the cached registers that might
327 * differ from the value that was last written. As it only
328 * automatically becomes one after being cleared, reread
329 * conditionally.
330 */
331 if (!(sport->ucr2 & UCR2_SRST))
332 sport->ucr2 = readl(sport->port.membase + offset);
333 return sport->ucr2;
334 break;
335 case UCR3:
336 return sport->ucr3;
337 break;
338 case UCR4:
339 return sport->ucr4;
340 break;
341 case UFCR:
342 return sport->ufcr;
343 break;
344 default:
345 return readl(sport->port.membase + offset);
346 }
347 }
348
imx_uart_uts_reg(struct imx_port * sport)349 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
350 {
351 return sport->devdata->uts_reg;
352 }
353
imx_uart_is_imx1(struct imx_port * sport)354 static inline int imx_uart_is_imx1(struct imx_port *sport)
355 {
356 return sport->devdata->devtype == IMX1_UART;
357 }
358
imx_uart_is_imx21(struct imx_port * sport)359 static inline int imx_uart_is_imx21(struct imx_port *sport)
360 {
361 return sport->devdata->devtype == IMX21_UART;
362 }
363
imx_uart_is_imx53(struct imx_port * sport)364 static inline int imx_uart_is_imx53(struct imx_port *sport)
365 {
366 return sport->devdata->devtype == IMX53_UART;
367 }
368
imx_uart_is_imx6q(struct imx_port * sport)369 static inline int imx_uart_is_imx6q(struct imx_port *sport)
370 {
371 return sport->devdata->devtype == IMX6Q_UART;
372 }
373 /*
374 * Save and restore functions for UCR1, UCR2 and UCR3 registers
375 */
376 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_ucrs_save(struct imx_port * sport,struct imx_port_ucrs * ucr)377 static void imx_uart_ucrs_save(struct imx_port *sport,
378 struct imx_port_ucrs *ucr)
379 {
380 /* save control registers */
381 ucr->ucr1 = imx_uart_readl(sport, UCR1);
382 ucr->ucr2 = imx_uart_readl(sport, UCR2);
383 ucr->ucr3 = imx_uart_readl(sport, UCR3);
384 }
385
imx_uart_ucrs_restore(struct imx_port * sport,struct imx_port_ucrs * ucr)386 static void imx_uart_ucrs_restore(struct imx_port *sport,
387 struct imx_port_ucrs *ucr)
388 {
389 /* restore control registers */
390 imx_uart_writel(sport, ucr->ucr1, UCR1);
391 imx_uart_writel(sport, ucr->ucr2, UCR2);
392 imx_uart_writel(sport, ucr->ucr3, UCR3);
393 }
394 #endif
395
396 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_active(struct imx_port * sport,u32 * ucr2)397 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
398 {
399 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
400
401 sport->port.mctrl |= TIOCM_RTS;
402 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
403 }
404
405 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_inactive(struct imx_port * sport,u32 * ucr2)406 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
407 {
408 *ucr2 &= ~UCR2_CTSC;
409 *ucr2 |= UCR2_CTS;
410
411 sport->port.mctrl &= ~TIOCM_RTS;
412 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
413 }
414
start_hrtimer_ms(struct hrtimer * hrt,unsigned long msec)415 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
416 {
417 long sec = msec / MSEC_PER_SEC;
418 long nsec = (msec % MSEC_PER_SEC) * 1000000;
419 ktime_t t = ktime_set(sec, nsec);
420
421 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
422 }
423
424 /* called with port.lock taken and irqs off */
imx_uart_start_rx(struct uart_port * port)425 static void imx_uart_start_rx(struct uart_port *port)
426 {
427 struct imx_port *sport = (struct imx_port *)port;
428 unsigned int ucr1, ucr2;
429
430 ucr1 = imx_uart_readl(sport, UCR1);
431 ucr2 = imx_uart_readl(sport, UCR2);
432
433 ucr2 |= UCR2_RXEN;
434
435 if (sport->dma_is_enabled) {
436 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
437 } else {
438 ucr1 |= UCR1_RRDYEN;
439 ucr2 |= UCR2_ATEN;
440 }
441
442 /* Write UCR2 first as it includes RXEN */
443 imx_uart_writel(sport, ucr2, UCR2);
444 imx_uart_writel(sport, ucr1, UCR1);
445 }
446
447 /* called with port.lock taken and irqs off */
imx_uart_stop_tx(struct uart_port * port)448 static void imx_uart_stop_tx(struct uart_port *port)
449 {
450 struct imx_port *sport = (struct imx_port *)port;
451 u32 ucr1, ucr4, usr2;
452
453 if (sport->tx_state == OFF)
454 return;
455
456 /*
457 * We are maybe in the SMP context, so if the DMA TX thread is running
458 * on other cpu, we have to wait for it to finish.
459 */
460 if (sport->dma_is_txing)
461 return;
462
463 ucr1 = imx_uart_readl(sport, UCR1);
464 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
465
466 usr2 = imx_uart_readl(sport, USR2);
467 if (!(usr2 & USR2_TXDC)) {
468 /* The shifter is still busy, so retry once TC triggers */
469 return;
470 }
471
472 ucr4 = imx_uart_readl(sport, UCR4);
473 ucr4 &= ~UCR4_TCEN;
474 imx_uart_writel(sport, ucr4, UCR4);
475
476 /* in rs485 mode disable transmitter */
477 if (port->rs485.flags & SER_RS485_ENABLED) {
478 if (sport->tx_state == SEND) {
479 sport->tx_state = WAIT_AFTER_SEND;
480 start_hrtimer_ms(&sport->trigger_stop_tx,
481 port->rs485.delay_rts_after_send);
482 return;
483 }
484
485 if (sport->tx_state == WAIT_AFTER_RTS ||
486 sport->tx_state == WAIT_AFTER_SEND) {
487 u32 ucr2;
488
489 hrtimer_try_to_cancel(&sport->trigger_start_tx);
490
491 ucr2 = imx_uart_readl(sport, UCR2);
492 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
493 imx_uart_rts_active(sport, &ucr2);
494 else
495 imx_uart_rts_inactive(sport, &ucr2);
496 imx_uart_writel(sport, ucr2, UCR2);
497
498 imx_uart_start_rx(port);
499
500 sport->tx_state = OFF;
501 }
502 } else {
503 sport->tx_state = OFF;
504 }
505 }
506
507 /* called with port.lock taken and irqs off */
imx_uart_stop_rx(struct uart_port * port)508 static void imx_uart_stop_rx(struct uart_port *port)
509 {
510 struct imx_port *sport = (struct imx_port *)port;
511 u32 ucr1, ucr2, ucr4;
512
513 ucr1 = imx_uart_readl(sport, UCR1);
514 ucr2 = imx_uart_readl(sport, UCR2);
515 ucr4 = imx_uart_readl(sport, UCR4);
516
517 if (sport->dma_is_enabled) {
518 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
519 } else {
520 ucr1 &= ~UCR1_RRDYEN;
521 ucr2 &= ~UCR2_ATEN;
522 ucr4 &= ~UCR4_OREN;
523 }
524 imx_uart_writel(sport, ucr1, UCR1);
525 imx_uart_writel(sport, ucr4, UCR4);
526
527 ucr2 &= ~UCR2_RXEN;
528 imx_uart_writel(sport, ucr2, UCR2);
529 }
530
531 /* called with port.lock taken and irqs off */
imx_uart_enable_ms(struct uart_port * port)532 static void imx_uart_enable_ms(struct uart_port *port)
533 {
534 struct imx_port *sport = (struct imx_port *)port;
535
536 mod_timer(&sport->timer, jiffies);
537
538 mctrl_gpio_enable_ms(sport->gpios);
539 }
540
541 static void imx_uart_dma_tx(struct imx_port *sport);
542
543 /* called with port.lock taken and irqs off */
imx_uart_transmit_buffer(struct imx_port * sport)544 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
545 {
546 struct circ_buf *xmit = &sport->port.state->xmit;
547
548 if (sport->port.x_char) {
549 /* Send next char */
550 imx_uart_writel(sport, sport->port.x_char, URTX0);
551 sport->port.icount.tx++;
552 sport->port.x_char = 0;
553 return;
554 }
555
556 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
557 imx_uart_stop_tx(&sport->port);
558 return;
559 }
560
561 if (sport->dma_is_enabled) {
562 u32 ucr1;
563 /*
564 * We've just sent a X-char Ensure the TX DMA is enabled
565 * and the TX IRQ is disabled.
566 **/
567 ucr1 = imx_uart_readl(sport, UCR1);
568 ucr1 &= ~UCR1_TRDYEN;
569 if (sport->dma_is_txing) {
570 ucr1 |= UCR1_TXDMAEN;
571 imx_uart_writel(sport, ucr1, UCR1);
572 } else {
573 imx_uart_writel(sport, ucr1, UCR1);
574 imx_uart_dma_tx(sport);
575 }
576
577 return;
578 }
579
580 while (!uart_circ_empty(xmit) &&
581 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
582 /* send xmit->buf[xmit->tail]
583 * out the port here */
584 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
585 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
586 sport->port.icount.tx++;
587 }
588
589 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
590 uart_write_wakeup(&sport->port);
591
592 if (uart_circ_empty(xmit))
593 imx_uart_stop_tx(&sport->port);
594 }
595
imx_uart_dma_tx_callback(void * data)596 static void imx_uart_dma_tx_callback(void *data)
597 {
598 struct imx_port *sport = data;
599 struct scatterlist *sgl = &sport->tx_sgl[0];
600 struct circ_buf *xmit = &sport->port.state->xmit;
601 unsigned long flags;
602 u32 ucr1;
603
604 spin_lock_irqsave(&sport->port.lock, flags);
605
606 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
607
608 ucr1 = imx_uart_readl(sport, UCR1);
609 ucr1 &= ~UCR1_TXDMAEN;
610 imx_uart_writel(sport, ucr1, UCR1);
611
612 /* update the stat */
613 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
614 sport->port.icount.tx += sport->tx_bytes;
615
616 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
617
618 sport->dma_is_txing = 0;
619
620 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
621 uart_write_wakeup(&sport->port);
622
623 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
624 imx_uart_dma_tx(sport);
625 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
626 u32 ucr4 = imx_uart_readl(sport, UCR4);
627 ucr4 |= UCR4_TCEN;
628 imx_uart_writel(sport, ucr4, UCR4);
629 }
630
631 spin_unlock_irqrestore(&sport->port.lock, flags);
632 }
633
634 /* called with port.lock taken and irqs off */
imx_uart_dma_tx(struct imx_port * sport)635 static void imx_uart_dma_tx(struct imx_port *sport)
636 {
637 struct circ_buf *xmit = &sport->port.state->xmit;
638 struct scatterlist *sgl = sport->tx_sgl;
639 struct dma_async_tx_descriptor *desc;
640 struct dma_chan *chan = sport->dma_chan_tx;
641 struct device *dev = sport->port.dev;
642 u32 ucr1, ucr4;
643 int ret;
644
645 if (sport->dma_is_txing)
646 return;
647
648 ucr4 = imx_uart_readl(sport, UCR4);
649 ucr4 &= ~UCR4_TCEN;
650 imx_uart_writel(sport, ucr4, UCR4);
651
652 sport->tx_bytes = uart_circ_chars_pending(xmit);
653
654 if (xmit->tail < xmit->head || xmit->head == 0) {
655 sport->dma_tx_nents = 1;
656 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
657 } else {
658 sport->dma_tx_nents = 2;
659 sg_init_table(sgl, 2);
660 sg_set_buf(sgl, xmit->buf + xmit->tail,
661 UART_XMIT_SIZE - xmit->tail);
662 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
663 }
664
665 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
666 if (ret == 0) {
667 dev_err(dev, "DMA mapping error for TX.\n");
668 return;
669 }
670 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
671 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
672 if (!desc) {
673 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
674 DMA_TO_DEVICE);
675 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
676 return;
677 }
678 desc->callback = imx_uart_dma_tx_callback;
679 desc->callback_param = sport;
680
681 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
682 uart_circ_chars_pending(xmit));
683
684 ucr1 = imx_uart_readl(sport, UCR1);
685 ucr1 |= UCR1_TXDMAEN;
686 imx_uart_writel(sport, ucr1, UCR1);
687
688 /* fire it */
689 sport->dma_is_txing = 1;
690 dmaengine_submit(desc);
691 dma_async_issue_pending(chan);
692 return;
693 }
694
695 /* called with port.lock taken and irqs off */
imx_uart_start_tx(struct uart_port * port)696 static void imx_uart_start_tx(struct uart_port *port)
697 {
698 struct imx_port *sport = (struct imx_port *)port;
699 u32 ucr1;
700
701 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
702 return;
703
704 /*
705 * We cannot simply do nothing here if sport->tx_state == SEND already
706 * because UCR1_TXMPTYEN might already have been cleared in
707 * imx_uart_stop_tx(), but tx_state is still SEND.
708 */
709
710 if (port->rs485.flags & SER_RS485_ENABLED) {
711 if (sport->tx_state == OFF) {
712 u32 ucr2 = imx_uart_readl(sport, UCR2);
713 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
714 imx_uart_rts_active(sport, &ucr2);
715 else
716 imx_uart_rts_inactive(sport, &ucr2);
717 imx_uart_writel(sport, ucr2, UCR2);
718
719 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
720 imx_uart_stop_rx(port);
721
722 sport->tx_state = WAIT_AFTER_RTS;
723 start_hrtimer_ms(&sport->trigger_start_tx,
724 port->rs485.delay_rts_before_send);
725 return;
726 }
727
728 if (sport->tx_state == WAIT_AFTER_SEND
729 || sport->tx_state == WAIT_AFTER_RTS) {
730
731 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
732
733 /*
734 * Enable transmitter and shifter empty irq only if DMA
735 * is off. In the DMA case this is done in the
736 * tx-callback.
737 */
738 if (!sport->dma_is_enabled) {
739 u32 ucr4 = imx_uart_readl(sport, UCR4);
740 ucr4 |= UCR4_TCEN;
741 imx_uart_writel(sport, ucr4, UCR4);
742 }
743
744 sport->tx_state = SEND;
745 }
746 } else {
747 sport->tx_state = SEND;
748 }
749
750 if (!sport->dma_is_enabled) {
751 ucr1 = imx_uart_readl(sport, UCR1);
752 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
753 }
754
755 if (sport->dma_is_enabled) {
756 if (sport->port.x_char) {
757 /* We have X-char to send, so enable TX IRQ and
758 * disable TX DMA to let TX interrupt to send X-char */
759 ucr1 = imx_uart_readl(sport, UCR1);
760 ucr1 &= ~UCR1_TXDMAEN;
761 ucr1 |= UCR1_TRDYEN;
762 imx_uart_writel(sport, ucr1, UCR1);
763 return;
764 }
765
766 if (!uart_circ_empty(&port->state->xmit) &&
767 !uart_tx_stopped(port))
768 imx_uart_dma_tx(sport);
769 return;
770 }
771 }
772
__imx_uart_rtsint(int irq,void * dev_id)773 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
774 {
775 struct imx_port *sport = dev_id;
776 u32 usr1;
777
778 imx_uart_writel(sport, USR1_RTSD, USR1);
779 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
780 uart_handle_cts_change(&sport->port, !!usr1);
781 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
782
783 return IRQ_HANDLED;
784 }
785
imx_uart_rtsint(int irq,void * dev_id)786 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
787 {
788 struct imx_port *sport = dev_id;
789 irqreturn_t ret;
790
791 spin_lock(&sport->port.lock);
792
793 ret = __imx_uart_rtsint(irq, dev_id);
794
795 spin_unlock(&sport->port.lock);
796
797 return ret;
798 }
799
imx_uart_txint(int irq,void * dev_id)800 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
801 {
802 struct imx_port *sport = dev_id;
803
804 spin_lock(&sport->port.lock);
805 imx_uart_transmit_buffer(sport);
806 spin_unlock(&sport->port.lock);
807 return IRQ_HANDLED;
808 }
809
__imx_uart_rxint(int irq,void * dev_id)810 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
811 {
812 struct imx_port *sport = dev_id;
813 unsigned int rx, flg, ignored = 0;
814 struct tty_port *port = &sport->port.state->port;
815
816 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
817 u32 usr2;
818
819 flg = TTY_NORMAL;
820 sport->port.icount.rx++;
821
822 rx = imx_uart_readl(sport, URXD0);
823
824 usr2 = imx_uart_readl(sport, USR2);
825 if (usr2 & USR2_BRCD) {
826 imx_uart_writel(sport, USR2_BRCD, USR2);
827 if (uart_handle_break(&sport->port))
828 continue;
829 }
830
831 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
832 continue;
833
834 if (unlikely(rx & URXD_ERR)) {
835 if (rx & URXD_BRK)
836 sport->port.icount.brk++;
837 else if (rx & URXD_PRERR)
838 sport->port.icount.parity++;
839 else if (rx & URXD_FRMERR)
840 sport->port.icount.frame++;
841 if (rx & URXD_OVRRUN)
842 sport->port.icount.overrun++;
843
844 if (rx & sport->port.ignore_status_mask) {
845 if (++ignored > 100)
846 goto out;
847 continue;
848 }
849
850 rx &= (sport->port.read_status_mask | 0xFF);
851
852 if (rx & URXD_BRK)
853 flg = TTY_BREAK;
854 else if (rx & URXD_PRERR)
855 flg = TTY_PARITY;
856 else if (rx & URXD_FRMERR)
857 flg = TTY_FRAME;
858 if (rx & URXD_OVRRUN)
859 flg = TTY_OVERRUN;
860
861 sport->port.sysrq = 0;
862 }
863
864 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
865 goto out;
866
867 if (tty_insert_flip_char(port, rx, flg) == 0)
868 sport->port.icount.buf_overrun++;
869 }
870
871 out:
872 tty_flip_buffer_push(port);
873
874 return IRQ_HANDLED;
875 }
876
imx_uart_rxint(int irq,void * dev_id)877 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
878 {
879 struct imx_port *sport = dev_id;
880 irqreturn_t ret;
881
882 spin_lock(&sport->port.lock);
883
884 ret = __imx_uart_rxint(irq, dev_id);
885
886 spin_unlock(&sport->port.lock);
887
888 return ret;
889 }
890
891 static void imx_uart_clear_rx_errors(struct imx_port *sport);
892
893 /*
894 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
895 */
imx_uart_get_hwmctrl(struct imx_port * sport)896 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
897 {
898 unsigned int tmp = TIOCM_DSR;
899 unsigned usr1 = imx_uart_readl(sport, USR1);
900 unsigned usr2 = imx_uart_readl(sport, USR2);
901
902 if (usr1 & USR1_RTSS)
903 tmp |= TIOCM_CTS;
904
905 /* in DCE mode DCDIN is always 0 */
906 if (!(usr2 & USR2_DCDIN))
907 tmp |= TIOCM_CAR;
908
909 if (sport->dte_mode)
910 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
911 tmp |= TIOCM_RI;
912
913 return tmp;
914 }
915
916 /*
917 * Handle any change of modem status signal since we were last called.
918 */
imx_uart_mctrl_check(struct imx_port * sport)919 static void imx_uart_mctrl_check(struct imx_port *sport)
920 {
921 unsigned int status, changed;
922
923 status = imx_uart_get_hwmctrl(sport);
924 changed = status ^ sport->old_status;
925
926 if (changed == 0)
927 return;
928
929 sport->old_status = status;
930
931 if (changed & TIOCM_RI && status & TIOCM_RI)
932 sport->port.icount.rng++;
933 if (changed & TIOCM_DSR)
934 sport->port.icount.dsr++;
935 if (changed & TIOCM_CAR)
936 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
937 if (changed & TIOCM_CTS)
938 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
939
940 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
941 }
942
imx_uart_int(int irq,void * dev_id)943 static irqreturn_t imx_uart_int(int irq, void *dev_id)
944 {
945 struct imx_port *sport = dev_id;
946 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
947 irqreturn_t ret = IRQ_NONE;
948 unsigned long flags = 0;
949
950 /*
951 * IRQs might not be disabled upon entering this interrupt handler,
952 * e.g. when interrupt handlers are forced to be threaded. To support
953 * this scenario as well, disable IRQs when acquiring the spinlock.
954 */
955 spin_lock_irqsave(&sport->port.lock, flags);
956
957 usr1 = imx_uart_readl(sport, USR1);
958 usr2 = imx_uart_readl(sport, USR2);
959 ucr1 = imx_uart_readl(sport, UCR1);
960 ucr2 = imx_uart_readl(sport, UCR2);
961 ucr3 = imx_uart_readl(sport, UCR3);
962 ucr4 = imx_uart_readl(sport, UCR4);
963
964 /*
965 * Even if a condition is true that can trigger an irq only handle it if
966 * the respective irq source is enabled. This prevents some undesired
967 * actions, for example if a character that sits in the RX FIFO and that
968 * should be fetched via DMA is tried to be fetched using PIO. Or the
969 * receiver is currently off and so reading from URXD0 results in an
970 * exception. So just mask the (raw) status bits for disabled irqs.
971 */
972 if ((ucr1 & UCR1_RRDYEN) == 0)
973 usr1 &= ~USR1_RRDY;
974 if ((ucr2 & UCR2_ATEN) == 0)
975 usr1 &= ~USR1_AGTIM;
976 if ((ucr1 & UCR1_TRDYEN) == 0)
977 usr1 &= ~USR1_TRDY;
978 if ((ucr4 & UCR4_TCEN) == 0)
979 usr2 &= ~USR2_TXDC;
980 if ((ucr3 & UCR3_DTRDEN) == 0)
981 usr1 &= ~USR1_DTRD;
982 if ((ucr1 & UCR1_RTSDEN) == 0)
983 usr1 &= ~USR1_RTSD;
984 if ((ucr3 & UCR3_AWAKEN) == 0)
985 usr1 &= ~USR1_AWAKE;
986 if ((ucr4 & UCR4_OREN) == 0)
987 usr2 &= ~USR2_ORE;
988
989 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
990 imx_uart_writel(sport, USR1_AGTIM, USR1);
991
992 __imx_uart_rxint(irq, dev_id);
993 ret = IRQ_HANDLED;
994 }
995
996 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
997 imx_uart_transmit_buffer(sport);
998 ret = IRQ_HANDLED;
999 }
1000
1001 if (usr1 & USR1_DTRD) {
1002 imx_uart_writel(sport, USR1_DTRD, USR1);
1003
1004 imx_uart_mctrl_check(sport);
1005
1006 ret = IRQ_HANDLED;
1007 }
1008
1009 if (usr1 & USR1_RTSD) {
1010 __imx_uart_rtsint(irq, dev_id);
1011 ret = IRQ_HANDLED;
1012 }
1013
1014 if (usr1 & USR1_AWAKE) {
1015 imx_uart_writel(sport, USR1_AWAKE, USR1);
1016 ret = IRQ_HANDLED;
1017 }
1018
1019 if (usr2 & USR2_ORE) {
1020 sport->port.icount.overrun++;
1021 imx_uart_writel(sport, USR2_ORE, USR2);
1022 ret = IRQ_HANDLED;
1023 }
1024
1025 spin_unlock_irqrestore(&sport->port.lock, flags);
1026
1027 return ret;
1028 }
1029
1030 /*
1031 * Return TIOCSER_TEMT when transmitter is not busy.
1032 */
imx_uart_tx_empty(struct uart_port * port)1033 static unsigned int imx_uart_tx_empty(struct uart_port *port)
1034 {
1035 struct imx_port *sport = (struct imx_port *)port;
1036 unsigned int ret;
1037
1038 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1039
1040 /* If the TX DMA is working, return 0. */
1041 if (sport->dma_is_txing)
1042 ret = 0;
1043
1044 return ret;
1045 }
1046
1047 /* called with port.lock taken and irqs off */
imx_uart_get_mctrl(struct uart_port * port)1048 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1049 {
1050 struct imx_port *sport = (struct imx_port *)port;
1051 unsigned int ret = imx_uart_get_hwmctrl(sport);
1052
1053 mctrl_gpio_get(sport->gpios, &ret);
1054
1055 return ret;
1056 }
1057
1058 /* called with port.lock taken and irqs off */
imx_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)1059 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1060 {
1061 struct imx_port *sport = (struct imx_port *)port;
1062 u32 ucr3, uts;
1063
1064 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1065 u32 ucr2;
1066
1067 /*
1068 * Turn off autoRTS if RTS is lowered and restore autoRTS
1069 * setting if RTS is raised.
1070 */
1071 ucr2 = imx_uart_readl(sport, UCR2);
1072 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1073 if (mctrl & TIOCM_RTS) {
1074 ucr2 |= UCR2_CTS;
1075 /*
1076 * UCR2_IRTS is unset if and only if the port is
1077 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1078 * to get the state to restore to.
1079 */
1080 if (!(ucr2 & UCR2_IRTS))
1081 ucr2 |= UCR2_CTSC;
1082 }
1083 imx_uart_writel(sport, ucr2, UCR2);
1084 }
1085
1086 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1087 if (!(mctrl & TIOCM_DTR))
1088 ucr3 |= UCR3_DSR;
1089 imx_uart_writel(sport, ucr3, UCR3);
1090
1091 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1092 if (mctrl & TIOCM_LOOP)
1093 uts |= UTS_LOOP;
1094 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1095
1096 mctrl_gpio_set(sport->gpios, mctrl);
1097 }
1098
1099 /*
1100 * Interrupts always disabled.
1101 */
imx_uart_break_ctl(struct uart_port * port,int break_state)1102 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1103 {
1104 struct imx_port *sport = (struct imx_port *)port;
1105 unsigned long flags;
1106 u32 ucr1;
1107
1108 spin_lock_irqsave(&sport->port.lock, flags);
1109
1110 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1111
1112 if (break_state != 0)
1113 ucr1 |= UCR1_SNDBRK;
1114
1115 imx_uart_writel(sport, ucr1, UCR1);
1116
1117 spin_unlock_irqrestore(&sport->port.lock, flags);
1118 }
1119
1120 /*
1121 * This is our per-port timeout handler, for checking the
1122 * modem status signals.
1123 */
imx_uart_timeout(struct timer_list * t)1124 static void imx_uart_timeout(struct timer_list *t)
1125 {
1126 struct imx_port *sport = from_timer(sport, t, timer);
1127 unsigned long flags;
1128
1129 if (sport->port.state) {
1130 spin_lock_irqsave(&sport->port.lock, flags);
1131 imx_uart_mctrl_check(sport);
1132 spin_unlock_irqrestore(&sport->port.lock, flags);
1133
1134 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1135 }
1136 }
1137
1138 /*
1139 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1140 * [1] the RX DMA buffer is full.
1141 * [2] the aging timer expires
1142 *
1143 * Condition [2] is triggered when a character has been sitting in the FIFO
1144 * for at least 8 byte durations.
1145 */
imx_uart_dma_rx_callback(void * data)1146 static void imx_uart_dma_rx_callback(void *data)
1147 {
1148 struct imx_port *sport = data;
1149 struct dma_chan *chan = sport->dma_chan_rx;
1150 struct scatterlist *sgl = &sport->rx_sgl;
1151 struct tty_port *port = &sport->port.state->port;
1152 struct dma_tx_state state;
1153 struct circ_buf *rx_ring = &sport->rx_ring;
1154 enum dma_status status;
1155 unsigned int w_bytes = 0;
1156 unsigned int r_bytes;
1157 unsigned int bd_size;
1158
1159 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1160
1161 if (status == DMA_ERROR) {
1162 imx_uart_clear_rx_errors(sport);
1163 return;
1164 }
1165
1166 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1167
1168 /*
1169 * The state-residue variable represents the empty space
1170 * relative to the entire buffer. Taking this in consideration
1171 * the head is always calculated base on the buffer total
1172 * length - DMA transaction residue. The UART script from the
1173 * SDMA firmware will jump to the next buffer descriptor,
1174 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1175 * Taking this in consideration the tail is always at the
1176 * beginning of the buffer descriptor that contains the head.
1177 */
1178
1179 /* Calculate the head */
1180 rx_ring->head = sg_dma_len(sgl) - state.residue;
1181
1182 /* Calculate the tail. */
1183 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1184 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1185
1186 if (rx_ring->head <= sg_dma_len(sgl) &&
1187 rx_ring->head > rx_ring->tail) {
1188
1189 /* Move data from tail to head */
1190 r_bytes = rx_ring->head - rx_ring->tail;
1191
1192 /* CPU claims ownership of RX DMA buffer */
1193 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1194 DMA_FROM_DEVICE);
1195
1196 w_bytes = tty_insert_flip_string(port,
1197 sport->rx_buf + rx_ring->tail, r_bytes);
1198
1199 /* UART retrieves ownership of RX DMA buffer */
1200 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1201 DMA_FROM_DEVICE);
1202
1203 if (w_bytes != r_bytes)
1204 sport->port.icount.buf_overrun++;
1205
1206 sport->port.icount.rx += w_bytes;
1207 } else {
1208 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1209 WARN_ON(rx_ring->head <= rx_ring->tail);
1210 }
1211 }
1212
1213 if (w_bytes) {
1214 tty_flip_buffer_push(port);
1215 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1216 }
1217 }
1218
1219 /* RX DMA buffer periods */
1220 #define RX_DMA_PERIODS 16
1221 #define RX_BUF_SIZE (RX_DMA_PERIODS * PAGE_SIZE / 4)
1222
imx_uart_start_rx_dma(struct imx_port * sport)1223 static int imx_uart_start_rx_dma(struct imx_port *sport)
1224 {
1225 struct scatterlist *sgl = &sport->rx_sgl;
1226 struct dma_chan *chan = sport->dma_chan_rx;
1227 struct device *dev = sport->port.dev;
1228 struct dma_async_tx_descriptor *desc;
1229 int ret;
1230
1231 sport->rx_ring.head = 0;
1232 sport->rx_ring.tail = 0;
1233 sport->rx_periods = RX_DMA_PERIODS;
1234
1235 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1236 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1237 if (ret == 0) {
1238 dev_err(dev, "DMA mapping error for RX.\n");
1239 return -EINVAL;
1240 }
1241
1242 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1243 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1244 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1245
1246 if (!desc) {
1247 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1248 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1249 return -EINVAL;
1250 }
1251 desc->callback = imx_uart_dma_rx_callback;
1252 desc->callback_param = sport;
1253
1254 dev_dbg(dev, "RX: prepare for the DMA.\n");
1255 sport->dma_is_rxing = 1;
1256 sport->rx_cookie = dmaengine_submit(desc);
1257 dma_async_issue_pending(chan);
1258 return 0;
1259 }
1260
imx_uart_clear_rx_errors(struct imx_port * sport)1261 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1262 {
1263 struct tty_port *port = &sport->port.state->port;
1264 u32 usr1, usr2;
1265
1266 usr1 = imx_uart_readl(sport, USR1);
1267 usr2 = imx_uart_readl(sport, USR2);
1268
1269 if (usr2 & USR2_BRCD) {
1270 sport->port.icount.brk++;
1271 imx_uart_writel(sport, USR2_BRCD, USR2);
1272 uart_handle_break(&sport->port);
1273 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1274 sport->port.icount.buf_overrun++;
1275 tty_flip_buffer_push(port);
1276 } else {
1277 if (usr1 & USR1_FRAMERR) {
1278 sport->port.icount.frame++;
1279 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1280 } else if (usr1 & USR1_PARITYERR) {
1281 sport->port.icount.parity++;
1282 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1283 }
1284 }
1285
1286 if (usr2 & USR2_ORE) {
1287 sport->port.icount.overrun++;
1288 imx_uart_writel(sport, USR2_ORE, USR2);
1289 }
1290
1291 }
1292
1293 #define TXTL_DEFAULT 2 /* reset default */
1294 #define RXTL_DEFAULT 1 /* reset default */
1295 #define TXTL_DMA 8 /* DMA burst setting */
1296 #define RXTL_DMA 9 /* DMA burst setting */
1297
imx_uart_setup_ufcr(struct imx_port * sport,unsigned char txwl,unsigned char rxwl)1298 static void imx_uart_setup_ufcr(struct imx_port *sport,
1299 unsigned char txwl, unsigned char rxwl)
1300 {
1301 unsigned int val;
1302
1303 /* set receiver / transmitter trigger level */
1304 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1305 val |= txwl << UFCR_TXTL_SHF | rxwl;
1306 imx_uart_writel(sport, val, UFCR);
1307 }
1308
imx_uart_dma_exit(struct imx_port * sport)1309 static void imx_uart_dma_exit(struct imx_port *sport)
1310 {
1311 if (sport->dma_chan_rx) {
1312 dmaengine_terminate_sync(sport->dma_chan_rx);
1313 dma_release_channel(sport->dma_chan_rx);
1314 sport->dma_chan_rx = NULL;
1315 sport->rx_cookie = -EINVAL;
1316 kfree(sport->rx_buf);
1317 sport->rx_buf = NULL;
1318 }
1319
1320 if (sport->dma_chan_tx) {
1321 dmaengine_terminate_sync(sport->dma_chan_tx);
1322 dma_release_channel(sport->dma_chan_tx);
1323 sport->dma_chan_tx = NULL;
1324 }
1325 }
1326
imx_uart_dma_init(struct imx_port * sport)1327 static int imx_uart_dma_init(struct imx_port *sport)
1328 {
1329 struct dma_slave_config slave_config = {};
1330 struct device *dev = sport->port.dev;
1331 int ret;
1332
1333 /* Prepare for RX : */
1334 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1335 if (!sport->dma_chan_rx) {
1336 dev_dbg(dev, "cannot get the DMA channel.\n");
1337 ret = -EINVAL;
1338 goto err;
1339 }
1340
1341 slave_config.direction = DMA_DEV_TO_MEM;
1342 slave_config.src_addr = sport->port.mapbase + URXD0;
1343 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1344 /* one byte less than the watermark level to enable the aging timer */
1345 slave_config.src_maxburst = RXTL_DMA - 1;
1346 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1347 if (ret) {
1348 dev_err(dev, "error in RX dma configuration.\n");
1349 goto err;
1350 }
1351
1352 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL);
1353 if (!sport->rx_buf) {
1354 ret = -ENOMEM;
1355 goto err;
1356 }
1357 sport->rx_ring.buf = sport->rx_buf;
1358
1359 /* Prepare for TX : */
1360 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1361 if (!sport->dma_chan_tx) {
1362 dev_err(dev, "cannot get the TX DMA channel!\n");
1363 ret = -EINVAL;
1364 goto err;
1365 }
1366
1367 slave_config.direction = DMA_MEM_TO_DEV;
1368 slave_config.dst_addr = sport->port.mapbase + URTX0;
1369 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1370 slave_config.dst_maxburst = TXTL_DMA;
1371 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1372 if (ret) {
1373 dev_err(dev, "error in TX dma configuration.");
1374 goto err;
1375 }
1376
1377 return 0;
1378 err:
1379 imx_uart_dma_exit(sport);
1380 return ret;
1381 }
1382
imx_uart_enable_dma(struct imx_port * sport)1383 static void imx_uart_enable_dma(struct imx_port *sport)
1384 {
1385 u32 ucr1;
1386
1387 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1388
1389 /* set UCR1 */
1390 ucr1 = imx_uart_readl(sport, UCR1);
1391 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1392 imx_uart_writel(sport, ucr1, UCR1);
1393
1394 sport->dma_is_enabled = 1;
1395 }
1396
imx_uart_disable_dma(struct imx_port * sport)1397 static void imx_uart_disable_dma(struct imx_port *sport)
1398 {
1399 u32 ucr1;
1400
1401 /* clear UCR1 */
1402 ucr1 = imx_uart_readl(sport, UCR1);
1403 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1404 imx_uart_writel(sport, ucr1, UCR1);
1405
1406 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1407
1408 sport->dma_is_enabled = 0;
1409 }
1410
1411 /* half the RX buffer size */
1412 #define CTSTL 16
1413
imx_uart_startup(struct uart_port * port)1414 static int imx_uart_startup(struct uart_port *port)
1415 {
1416 struct imx_port *sport = (struct imx_port *)port;
1417 int retval, i;
1418 unsigned long flags;
1419 int dma_is_inited = 0;
1420 u32 ucr1, ucr2, ucr3, ucr4;
1421
1422 retval = clk_prepare_enable(sport->clk_per);
1423 if (retval)
1424 return retval;
1425 retval = clk_prepare_enable(sport->clk_ipg);
1426 if (retval) {
1427 clk_disable_unprepare(sport->clk_per);
1428 return retval;
1429 }
1430
1431 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1432
1433 /* disable the DREN bit (Data Ready interrupt enable) before
1434 * requesting IRQs
1435 */
1436 ucr4 = imx_uart_readl(sport, UCR4);
1437
1438 /* set the trigger level for CTS */
1439 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1440 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1441
1442 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1443
1444 /* Can we enable the DMA support? */
1445 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1446 dma_is_inited = 1;
1447
1448 spin_lock_irqsave(&sport->port.lock, flags);
1449 /* Reset fifo's and state machines */
1450 i = 100;
1451
1452 ucr2 = imx_uart_readl(sport, UCR2);
1453 ucr2 &= ~UCR2_SRST;
1454 imx_uart_writel(sport, ucr2, UCR2);
1455
1456 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1457 udelay(1);
1458
1459 /*
1460 * Finally, clear and enable interrupts
1461 */
1462 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1463 imx_uart_writel(sport, USR2_ORE, USR2);
1464
1465 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1466 ucr1 |= UCR1_UARTEN;
1467 if (sport->have_rtscts)
1468 ucr1 |= UCR1_RTSDEN;
1469
1470 imx_uart_writel(sport, ucr1, UCR1);
1471
1472 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1473 if (!sport->dma_is_enabled)
1474 ucr4 |= UCR4_OREN;
1475 if (sport->inverted_rx)
1476 ucr4 |= UCR4_INVR;
1477 imx_uart_writel(sport, ucr4, UCR4);
1478
1479 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1480 /*
1481 * configure tx polarity before enabling tx
1482 */
1483 if (sport->inverted_tx)
1484 ucr3 |= UCR3_INVT;
1485
1486 if (!imx_uart_is_imx1(sport)) {
1487 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1488
1489 if (sport->dte_mode)
1490 /* disable broken interrupts */
1491 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1492 }
1493 imx_uart_writel(sport, ucr3, UCR3);
1494
1495 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1496 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1497 if (!sport->have_rtscts)
1498 ucr2 |= UCR2_IRTS;
1499 /*
1500 * make sure the edge sensitive RTS-irq is disabled,
1501 * we're using RTSD instead.
1502 */
1503 if (!imx_uart_is_imx1(sport))
1504 ucr2 &= ~UCR2_RTSEN;
1505 imx_uart_writel(sport, ucr2, UCR2);
1506
1507 /*
1508 * Enable modem status interrupts
1509 */
1510 imx_uart_enable_ms(&sport->port);
1511
1512 if (dma_is_inited) {
1513 imx_uart_enable_dma(sport);
1514 imx_uart_start_rx_dma(sport);
1515 } else {
1516 ucr1 = imx_uart_readl(sport, UCR1);
1517 ucr1 |= UCR1_RRDYEN;
1518 imx_uart_writel(sport, ucr1, UCR1);
1519
1520 ucr2 = imx_uart_readl(sport, UCR2);
1521 ucr2 |= UCR2_ATEN;
1522 imx_uart_writel(sport, ucr2, UCR2);
1523 }
1524
1525 spin_unlock_irqrestore(&sport->port.lock, flags);
1526
1527 return 0;
1528 }
1529
imx_uart_shutdown(struct uart_port * port)1530 static void imx_uart_shutdown(struct uart_port *port)
1531 {
1532 struct imx_port *sport = (struct imx_port *)port;
1533 unsigned long flags;
1534 u32 ucr1, ucr2, ucr4;
1535
1536 if (sport->dma_is_enabled) {
1537 dmaengine_terminate_sync(sport->dma_chan_tx);
1538 if (sport->dma_is_txing) {
1539 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1540 sport->dma_tx_nents, DMA_TO_DEVICE);
1541 sport->dma_is_txing = 0;
1542 }
1543 dmaengine_terminate_sync(sport->dma_chan_rx);
1544 if (sport->dma_is_rxing) {
1545 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1546 1, DMA_FROM_DEVICE);
1547 sport->dma_is_rxing = 0;
1548 }
1549
1550 spin_lock_irqsave(&sport->port.lock, flags);
1551 imx_uart_stop_tx(port);
1552 imx_uart_stop_rx(port);
1553 imx_uart_disable_dma(sport);
1554 spin_unlock_irqrestore(&sport->port.lock, flags);
1555 imx_uart_dma_exit(sport);
1556 }
1557
1558 mctrl_gpio_disable_ms(sport->gpios);
1559
1560 spin_lock_irqsave(&sport->port.lock, flags);
1561 ucr2 = imx_uart_readl(sport, UCR2);
1562 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1563 imx_uart_writel(sport, ucr2, UCR2);
1564 spin_unlock_irqrestore(&sport->port.lock, flags);
1565
1566 /*
1567 * Stop our timer.
1568 */
1569 del_timer_sync(&sport->timer);
1570
1571 /*
1572 * Disable all interrupts, port and break condition.
1573 */
1574
1575 spin_lock_irqsave(&sport->port.lock, flags);
1576
1577 ucr1 = imx_uart_readl(sport, UCR1);
1578 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1579 imx_uart_writel(sport, ucr1, UCR1);
1580
1581 ucr4 = imx_uart_readl(sport, UCR4);
1582 ucr4 &= ~UCR4_TCEN;
1583 imx_uart_writel(sport, ucr4, UCR4);
1584
1585 spin_unlock_irqrestore(&sport->port.lock, flags);
1586
1587 clk_disable_unprepare(sport->clk_per);
1588 clk_disable_unprepare(sport->clk_ipg);
1589 }
1590
1591 /* called with port.lock taken and irqs off */
imx_uart_flush_buffer(struct uart_port * port)1592 static void imx_uart_flush_buffer(struct uart_port *port)
1593 {
1594 struct imx_port *sport = (struct imx_port *)port;
1595 struct scatterlist *sgl = &sport->tx_sgl[0];
1596 u32 ucr2;
1597 int i = 100, ubir, ubmr, uts;
1598
1599 if (!sport->dma_chan_tx)
1600 return;
1601
1602 sport->tx_bytes = 0;
1603 dmaengine_terminate_all(sport->dma_chan_tx);
1604 if (sport->dma_is_txing) {
1605 u32 ucr1;
1606
1607 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1608 DMA_TO_DEVICE);
1609 ucr1 = imx_uart_readl(sport, UCR1);
1610 ucr1 &= ~UCR1_TXDMAEN;
1611 imx_uart_writel(sport, ucr1, UCR1);
1612 sport->dma_is_txing = 0;
1613 }
1614
1615 /*
1616 * According to the Reference Manual description of the UART SRST bit:
1617 *
1618 * "Reset the transmit and receive state machines,
1619 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1620 * and UTS[6-3]".
1621 *
1622 * We don't need to restore the old values from USR1, USR2, URXD and
1623 * UTXD. UBRC is read only, so only save/restore the other three
1624 * registers.
1625 */
1626 ubir = imx_uart_readl(sport, UBIR);
1627 ubmr = imx_uart_readl(sport, UBMR);
1628 uts = imx_uart_readl(sport, IMX21_UTS);
1629
1630 ucr2 = imx_uart_readl(sport, UCR2);
1631 ucr2 &= ~UCR2_SRST;
1632 imx_uart_writel(sport, ucr2, UCR2);
1633
1634 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1635 udelay(1);
1636
1637 /* Restore the registers */
1638 imx_uart_writel(sport, ubir, UBIR);
1639 imx_uart_writel(sport, ubmr, UBMR);
1640 imx_uart_writel(sport, uts, IMX21_UTS);
1641 }
1642
1643 static void
imx_uart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)1644 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1645 struct ktermios *old)
1646 {
1647 struct imx_port *sport = (struct imx_port *)port;
1648 unsigned long flags;
1649 u32 ucr2, old_ucr2, ufcr;
1650 unsigned int baud, quot;
1651 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1652 unsigned long div;
1653 unsigned long num, denom, old_ubir, old_ubmr;
1654 uint64_t tdiv64;
1655
1656 /*
1657 * We only support CS7 and CS8.
1658 */
1659 while ((termios->c_cflag & CSIZE) != CS7 &&
1660 (termios->c_cflag & CSIZE) != CS8) {
1661 termios->c_cflag &= ~CSIZE;
1662 termios->c_cflag |= old_csize;
1663 old_csize = CS8;
1664 }
1665
1666 del_timer_sync(&sport->timer);
1667
1668 /*
1669 * Ask the core to calculate the divisor for us.
1670 */
1671 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1672 quot = uart_get_divisor(port, baud);
1673
1674 spin_lock_irqsave(&sport->port.lock, flags);
1675
1676 /*
1677 * Read current UCR2 and save it for future use, then clear all the bits
1678 * except those we will or may need to preserve.
1679 */
1680 old_ucr2 = imx_uart_readl(sport, UCR2);
1681 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1682
1683 ucr2 |= UCR2_SRST | UCR2_IRTS;
1684 if ((termios->c_cflag & CSIZE) == CS8)
1685 ucr2 |= UCR2_WS;
1686
1687 if (!sport->have_rtscts)
1688 termios->c_cflag &= ~CRTSCTS;
1689
1690 if (port->rs485.flags & SER_RS485_ENABLED) {
1691 /*
1692 * RTS is mandatory for rs485 operation, so keep
1693 * it under manual control and keep transmitter
1694 * disabled.
1695 */
1696 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1697 imx_uart_rts_active(sport, &ucr2);
1698 else
1699 imx_uart_rts_inactive(sport, &ucr2);
1700
1701 } else if (termios->c_cflag & CRTSCTS) {
1702 /*
1703 * Only let receiver control RTS output if we were not requested
1704 * to have RTS inactive (which then should take precedence).
1705 */
1706 if (ucr2 & UCR2_CTS)
1707 ucr2 |= UCR2_CTSC;
1708 }
1709
1710 if (termios->c_cflag & CRTSCTS)
1711 ucr2 &= ~UCR2_IRTS;
1712 if (termios->c_cflag & CSTOPB)
1713 ucr2 |= UCR2_STPB;
1714 if (termios->c_cflag & PARENB) {
1715 ucr2 |= UCR2_PREN;
1716 if (termios->c_cflag & PARODD)
1717 ucr2 |= UCR2_PROE;
1718 }
1719
1720 sport->port.read_status_mask = 0;
1721 if (termios->c_iflag & INPCK)
1722 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1723 if (termios->c_iflag & (BRKINT | PARMRK))
1724 sport->port.read_status_mask |= URXD_BRK;
1725
1726 /*
1727 * Characters to ignore
1728 */
1729 sport->port.ignore_status_mask = 0;
1730 if (termios->c_iflag & IGNPAR)
1731 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1732 if (termios->c_iflag & IGNBRK) {
1733 sport->port.ignore_status_mask |= URXD_BRK;
1734 /*
1735 * If we're ignoring parity and break indicators,
1736 * ignore overruns too (for real raw support).
1737 */
1738 if (termios->c_iflag & IGNPAR)
1739 sport->port.ignore_status_mask |= URXD_OVRRUN;
1740 }
1741
1742 if ((termios->c_cflag & CREAD) == 0)
1743 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1744
1745 /*
1746 * Update the per-port timeout.
1747 */
1748 uart_update_timeout(port, termios->c_cflag, baud);
1749
1750 /* custom-baudrate handling */
1751 div = sport->port.uartclk / (baud * 16);
1752 if (baud == 38400 && quot != div)
1753 baud = sport->port.uartclk / (quot * 16);
1754
1755 div = sport->port.uartclk / (baud * 16);
1756 if (div > 7)
1757 div = 7;
1758 if (!div)
1759 div = 1;
1760
1761 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1762 1 << 16, 1 << 16, &num, &denom);
1763
1764 tdiv64 = sport->port.uartclk;
1765 tdiv64 *= num;
1766 do_div(tdiv64, denom * 16 * div);
1767 tty_termios_encode_baud_rate(termios,
1768 (speed_t)tdiv64, (speed_t)tdiv64);
1769
1770 num -= 1;
1771 denom -= 1;
1772
1773 ufcr = imx_uart_readl(sport, UFCR);
1774 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1775 imx_uart_writel(sport, ufcr, UFCR);
1776
1777 /*
1778 * Two registers below should always be written both and in this
1779 * particular order. One consequence is that we need to check if any of
1780 * them changes and then update both. We do need the check for change
1781 * as even writing the same values seem to "restart"
1782 * transmission/receiving logic in the hardware, that leads to data
1783 * breakage even when rate doesn't in fact change. E.g., user switches
1784 * RTS/CTS handshake and suddenly gets broken bytes.
1785 */
1786 old_ubir = imx_uart_readl(sport, UBIR);
1787 old_ubmr = imx_uart_readl(sport, UBMR);
1788 if (old_ubir != num || old_ubmr != denom) {
1789 imx_uart_writel(sport, num, UBIR);
1790 imx_uart_writel(sport, denom, UBMR);
1791 }
1792
1793 if (!imx_uart_is_imx1(sport))
1794 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1795 IMX21_ONEMS);
1796
1797 imx_uart_writel(sport, ucr2, UCR2);
1798
1799 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1800 imx_uart_enable_ms(&sport->port);
1801
1802 spin_unlock_irqrestore(&sport->port.lock, flags);
1803 }
1804
imx_uart_type(struct uart_port * port)1805 static const char *imx_uart_type(struct uart_port *port)
1806 {
1807 struct imx_port *sport = (struct imx_port *)port;
1808
1809 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1810 }
1811
1812 /*
1813 * Configure/autoconfigure the port.
1814 */
imx_uart_config_port(struct uart_port * port,int flags)1815 static void imx_uart_config_port(struct uart_port *port, int flags)
1816 {
1817 struct imx_port *sport = (struct imx_port *)port;
1818
1819 if (flags & UART_CONFIG_TYPE)
1820 sport->port.type = PORT_IMX;
1821 }
1822
1823 /*
1824 * Verify the new serial_struct (for TIOCSSERIAL).
1825 * The only change we allow are to the flags and type, and
1826 * even then only between PORT_IMX and PORT_UNKNOWN
1827 */
1828 static int
imx_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1829 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1830 {
1831 struct imx_port *sport = (struct imx_port *)port;
1832 int ret = 0;
1833
1834 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1835 ret = -EINVAL;
1836 if (sport->port.irq != ser->irq)
1837 ret = -EINVAL;
1838 if (ser->io_type != UPIO_MEM)
1839 ret = -EINVAL;
1840 if (sport->port.uartclk / 16 != ser->baud_base)
1841 ret = -EINVAL;
1842 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1843 ret = -EINVAL;
1844 if (sport->port.iobase != ser->port)
1845 ret = -EINVAL;
1846 if (ser->hub6 != 0)
1847 ret = -EINVAL;
1848 return ret;
1849 }
1850
1851 #if defined(CONFIG_CONSOLE_POLL)
1852
imx_uart_poll_init(struct uart_port * port)1853 static int imx_uart_poll_init(struct uart_port *port)
1854 {
1855 struct imx_port *sport = (struct imx_port *)port;
1856 unsigned long flags;
1857 u32 ucr1, ucr2;
1858 int retval;
1859
1860 retval = clk_prepare_enable(sport->clk_ipg);
1861 if (retval)
1862 return retval;
1863 retval = clk_prepare_enable(sport->clk_per);
1864 if (retval)
1865 clk_disable_unprepare(sport->clk_ipg);
1866
1867 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1868
1869 spin_lock_irqsave(&sport->port.lock, flags);
1870
1871 /*
1872 * Be careful about the order of enabling bits here. First enable the
1873 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1874 * This prevents that a character that already sits in the RX fifo is
1875 * triggering an irq but the try to fetch it from there results in an
1876 * exception because UARTEN or RXEN is still off.
1877 */
1878 ucr1 = imx_uart_readl(sport, UCR1);
1879 ucr2 = imx_uart_readl(sport, UCR2);
1880
1881 if (imx_uart_is_imx1(sport))
1882 ucr1 |= IMX1_UCR1_UARTCLKEN;
1883
1884 ucr1 |= UCR1_UARTEN;
1885 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1886
1887 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1888 ucr2 &= ~UCR2_ATEN;
1889
1890 imx_uart_writel(sport, ucr1, UCR1);
1891 imx_uart_writel(sport, ucr2, UCR2);
1892
1893 /* now enable irqs */
1894 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1895 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1896
1897 spin_unlock_irqrestore(&sport->port.lock, flags);
1898
1899 return 0;
1900 }
1901
imx_uart_poll_get_char(struct uart_port * port)1902 static int imx_uart_poll_get_char(struct uart_port *port)
1903 {
1904 struct imx_port *sport = (struct imx_port *)port;
1905 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1906 return NO_POLL_CHAR;
1907
1908 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1909 }
1910
imx_uart_poll_put_char(struct uart_port * port,unsigned char c)1911 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1912 {
1913 struct imx_port *sport = (struct imx_port *)port;
1914 unsigned int status;
1915
1916 /* drain */
1917 do {
1918 status = imx_uart_readl(sport, USR1);
1919 } while (~status & USR1_TRDY);
1920
1921 /* write */
1922 imx_uart_writel(sport, c, URTX0);
1923
1924 /* flush */
1925 do {
1926 status = imx_uart_readl(sport, USR2);
1927 } while (~status & USR2_TXDC);
1928 }
1929 #endif
1930
1931 /* called with port.lock taken and irqs off or from .probe without locking */
imx_uart_rs485_config(struct uart_port * port,struct serial_rs485 * rs485conf)1932 static int imx_uart_rs485_config(struct uart_port *port,
1933 struct serial_rs485 *rs485conf)
1934 {
1935 struct imx_port *sport = (struct imx_port *)port;
1936 u32 ucr2;
1937
1938 /* RTS is required to control the transmitter */
1939 if (!sport->have_rtscts && !sport->have_rtsgpio)
1940 rs485conf->flags &= ~SER_RS485_ENABLED;
1941
1942 if (rs485conf->flags & SER_RS485_ENABLED) {
1943 /* Enable receiver if low-active RTS signal is requested */
1944 if (sport->have_rtscts && !sport->have_rtsgpio &&
1945 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1946 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1947
1948 /* disable transmitter */
1949 ucr2 = imx_uart_readl(sport, UCR2);
1950 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1951 imx_uart_rts_active(sport, &ucr2);
1952 else
1953 imx_uart_rts_inactive(sport, &ucr2);
1954 imx_uart_writel(sport, ucr2, UCR2);
1955 }
1956
1957 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1958 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1959 rs485conf->flags & SER_RS485_RX_DURING_TX)
1960 imx_uart_start_rx(port);
1961
1962 port->rs485 = *rs485conf;
1963
1964 return 0;
1965 }
1966
1967 static const struct uart_ops imx_uart_pops = {
1968 .tx_empty = imx_uart_tx_empty,
1969 .set_mctrl = imx_uart_set_mctrl,
1970 .get_mctrl = imx_uart_get_mctrl,
1971 .stop_tx = imx_uart_stop_tx,
1972 .start_tx = imx_uart_start_tx,
1973 .stop_rx = imx_uart_stop_rx,
1974 .enable_ms = imx_uart_enable_ms,
1975 .break_ctl = imx_uart_break_ctl,
1976 .startup = imx_uart_startup,
1977 .shutdown = imx_uart_shutdown,
1978 .flush_buffer = imx_uart_flush_buffer,
1979 .set_termios = imx_uart_set_termios,
1980 .type = imx_uart_type,
1981 .config_port = imx_uart_config_port,
1982 .verify_port = imx_uart_verify_port,
1983 #if defined(CONFIG_CONSOLE_POLL)
1984 .poll_init = imx_uart_poll_init,
1985 .poll_get_char = imx_uart_poll_get_char,
1986 .poll_put_char = imx_uart_poll_put_char,
1987 #endif
1988 };
1989
1990 static struct imx_port *imx_uart_ports[UART_NR];
1991
1992 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_console_putchar(struct uart_port * port,int ch)1993 static void imx_uart_console_putchar(struct uart_port *port, int ch)
1994 {
1995 struct imx_port *sport = (struct imx_port *)port;
1996
1997 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1998 barrier();
1999
2000 imx_uart_writel(sport, ch, URTX0);
2001 }
2002
2003 /*
2004 * Interrupts are disabled on entering
2005 */
2006 static void
imx_uart_console_write(struct console * co,const char * s,unsigned int count)2007 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
2008 {
2009 struct imx_port *sport = imx_uart_ports[co->index];
2010 struct imx_port_ucrs old_ucr;
2011 unsigned int ucr1;
2012 unsigned long flags = 0;
2013 int locked = 1;
2014
2015 if (sport->port.sysrq)
2016 locked = 0;
2017 else if (oops_in_progress)
2018 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2019 else
2020 spin_lock_irqsave(&sport->port.lock, flags);
2021
2022 /*
2023 * First, save UCR1/2/3 and then disable interrupts
2024 */
2025 imx_uart_ucrs_save(sport, &old_ucr);
2026 ucr1 = old_ucr.ucr1;
2027
2028 if (imx_uart_is_imx1(sport))
2029 ucr1 |= IMX1_UCR1_UARTCLKEN;
2030 ucr1 |= UCR1_UARTEN;
2031 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2032
2033 imx_uart_writel(sport, ucr1, UCR1);
2034
2035 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2036
2037 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2038
2039 /*
2040 * Finally, wait for transmitter to become empty
2041 * and restore UCR1/2/3
2042 */
2043 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
2044
2045 imx_uart_ucrs_restore(sport, &old_ucr);
2046
2047 if (locked)
2048 spin_unlock_irqrestore(&sport->port.lock, flags);
2049 }
2050
2051 /*
2052 * If the port was already initialised (eg, by a boot loader),
2053 * try to determine the current setup.
2054 */
2055 static void
imx_uart_console_get_options(struct imx_port * sport,int * baud,int * parity,int * bits)2056 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2057 int *parity, int *bits)
2058 {
2059
2060 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2061 /* ok, the port was enabled */
2062 unsigned int ucr2, ubir, ubmr, uartclk;
2063 unsigned int baud_raw;
2064 unsigned int ucfr_rfdiv;
2065
2066 ucr2 = imx_uart_readl(sport, UCR2);
2067
2068 *parity = 'n';
2069 if (ucr2 & UCR2_PREN) {
2070 if (ucr2 & UCR2_PROE)
2071 *parity = 'o';
2072 else
2073 *parity = 'e';
2074 }
2075
2076 if (ucr2 & UCR2_WS)
2077 *bits = 8;
2078 else
2079 *bits = 7;
2080
2081 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2082 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2083
2084 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2085 if (ucfr_rfdiv == 6)
2086 ucfr_rfdiv = 7;
2087 else
2088 ucfr_rfdiv = 6 - ucfr_rfdiv;
2089
2090 uartclk = clk_get_rate(sport->clk_per);
2091 uartclk /= ucfr_rfdiv;
2092
2093 { /*
2094 * The next code provides exact computation of
2095 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2096 * without need of float support or long long division,
2097 * which would be required to prevent 32bit arithmetic overflow
2098 */
2099 unsigned int mul = ubir + 1;
2100 unsigned int div = 16 * (ubmr + 1);
2101 unsigned int rem = uartclk % div;
2102
2103 baud_raw = (uartclk / div) * mul;
2104 baud_raw += (rem * mul + div / 2) / div;
2105 *baud = (baud_raw + 50) / 100 * 100;
2106 }
2107
2108 if (*baud != baud_raw)
2109 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2110 baud_raw, *baud);
2111 }
2112 }
2113
2114 static int
imx_uart_console_setup(struct console * co,char * options)2115 imx_uart_console_setup(struct console *co, char *options)
2116 {
2117 struct imx_port *sport;
2118 int baud = 9600;
2119 int bits = 8;
2120 int parity = 'n';
2121 int flow = 'n';
2122 int retval;
2123
2124 /*
2125 * Check whether an invalid uart number has been specified, and
2126 * if so, search for the first available port that does have
2127 * console support.
2128 */
2129 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2130 co->index = 0;
2131 sport = imx_uart_ports[co->index];
2132 if (sport == NULL)
2133 return -ENODEV;
2134
2135 /* For setting the registers, we only need to enable the ipg clock. */
2136 retval = clk_prepare_enable(sport->clk_ipg);
2137 if (retval)
2138 goto error_console;
2139
2140 if (options)
2141 uart_parse_options(options, &baud, &parity, &bits, &flow);
2142 else
2143 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2144
2145 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2146
2147 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2148
2149 if (retval) {
2150 clk_disable_unprepare(sport->clk_ipg);
2151 goto error_console;
2152 }
2153
2154 retval = clk_prepare_enable(sport->clk_per);
2155 if (retval)
2156 clk_disable_unprepare(sport->clk_ipg);
2157
2158 error_console:
2159 return retval;
2160 }
2161
2162 static struct uart_driver imx_uart_uart_driver;
2163 static struct console imx_uart_console = {
2164 .name = DEV_NAME,
2165 .write = imx_uart_console_write,
2166 .device = uart_console_device,
2167 .setup = imx_uart_console_setup,
2168 .flags = CON_PRINTBUFFER,
2169 .index = -1,
2170 .data = &imx_uart_uart_driver,
2171 };
2172
2173 #define IMX_CONSOLE &imx_uart_console
2174
2175 #else
2176 #define IMX_CONSOLE NULL
2177 #endif
2178
2179 static struct uart_driver imx_uart_uart_driver = {
2180 .owner = THIS_MODULE,
2181 .driver_name = DRIVER_NAME,
2182 .dev_name = DEV_NAME,
2183 .major = SERIAL_IMX_MAJOR,
2184 .minor = MINOR_START,
2185 .nr = ARRAY_SIZE(imx_uart_ports),
2186 .cons = IMX_CONSOLE,
2187 };
2188
2189 #ifdef CONFIG_OF
2190 /*
2191 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2192 * could successfully get all information from dt or a negative errno.
2193 */
imx_uart_probe_dt(struct imx_port * sport,struct platform_device * pdev)2194 static int imx_uart_probe_dt(struct imx_port *sport,
2195 struct platform_device *pdev)
2196 {
2197 struct device_node *np = pdev->dev.of_node;
2198 int ret;
2199
2200 sport->devdata = of_device_get_match_data(&pdev->dev);
2201 if (!sport->devdata)
2202 /* no device tree device */
2203 return 1;
2204
2205 ret = of_alias_get_id(np, "serial");
2206 if (ret < 0) {
2207 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2208 return ret;
2209 }
2210 sport->port.line = ret;
2211
2212 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2213 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2214 sport->have_rtscts = 1;
2215
2216 if (of_get_property(np, "fsl,dte-mode", NULL))
2217 sport->dte_mode = 1;
2218
2219 if (of_get_property(np, "rts-gpios", NULL))
2220 sport->have_rtsgpio = 1;
2221
2222 if (of_get_property(np, "fsl,inverted-tx", NULL))
2223 sport->inverted_tx = 1;
2224
2225 if (of_get_property(np, "fsl,inverted-rx", NULL))
2226 sport->inverted_rx = 1;
2227
2228 return 0;
2229 }
2230 #else
imx_uart_probe_dt(struct imx_port * sport,struct platform_device * pdev)2231 static inline int imx_uart_probe_dt(struct imx_port *sport,
2232 struct platform_device *pdev)
2233 {
2234 return 1;
2235 }
2236 #endif
2237
imx_uart_probe_pdata(struct imx_port * sport,struct platform_device * pdev)2238 static void imx_uart_probe_pdata(struct imx_port *sport,
2239 struct platform_device *pdev)
2240 {
2241 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2242
2243 sport->port.line = pdev->id;
2244 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
2245
2246 if (!pdata)
2247 return;
2248
2249 if (pdata->flags & IMXUART_HAVE_RTSCTS)
2250 sport->have_rtscts = 1;
2251 }
2252
imx_trigger_start_tx(struct hrtimer * t)2253 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2254 {
2255 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2256 unsigned long flags;
2257
2258 spin_lock_irqsave(&sport->port.lock, flags);
2259 if (sport->tx_state == WAIT_AFTER_RTS)
2260 imx_uart_start_tx(&sport->port);
2261 spin_unlock_irqrestore(&sport->port.lock, flags);
2262
2263 return HRTIMER_NORESTART;
2264 }
2265
imx_trigger_stop_tx(struct hrtimer * t)2266 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2267 {
2268 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2269 unsigned long flags;
2270
2271 spin_lock_irqsave(&sport->port.lock, flags);
2272 if (sport->tx_state == WAIT_AFTER_SEND)
2273 imx_uart_stop_tx(&sport->port);
2274 spin_unlock_irqrestore(&sport->port.lock, flags);
2275
2276 return HRTIMER_NORESTART;
2277 }
2278
imx_uart_probe(struct platform_device * pdev)2279 static int imx_uart_probe(struct platform_device *pdev)
2280 {
2281 struct imx_port *sport;
2282 void __iomem *base;
2283 int ret = 0;
2284 u32 ucr1;
2285 struct resource *res;
2286 int txirq, rxirq, rtsirq;
2287
2288 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2289 if (!sport)
2290 return -ENOMEM;
2291
2292 ret = imx_uart_probe_dt(sport, pdev);
2293 if (ret > 0)
2294 imx_uart_probe_pdata(sport, pdev);
2295 else if (ret < 0)
2296 return ret;
2297
2298 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2299 dev_err(&pdev->dev, "serial%d out of range\n",
2300 sport->port.line);
2301 return -EINVAL;
2302 }
2303
2304 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2305 base = devm_ioremap_resource(&pdev->dev, res);
2306 if (IS_ERR(base))
2307 return PTR_ERR(base);
2308
2309 rxirq = platform_get_irq(pdev, 0);
2310 if (rxirq < 0)
2311 return rxirq;
2312 txirq = platform_get_irq_optional(pdev, 1);
2313 rtsirq = platform_get_irq_optional(pdev, 2);
2314
2315 sport->port.dev = &pdev->dev;
2316 sport->port.mapbase = res->start;
2317 sport->port.membase = base;
2318 sport->port.type = PORT_IMX,
2319 sport->port.iotype = UPIO_MEM;
2320 sport->port.irq = rxirq;
2321 sport->port.fifosize = 32;
2322 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2323 sport->port.ops = &imx_uart_pops;
2324 sport->port.rs485_config = imx_uart_rs485_config;
2325 sport->port.flags = UPF_BOOT_AUTOCONF;
2326 timer_setup(&sport->timer, imx_uart_timeout, 0);
2327
2328 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2329 if (IS_ERR(sport->gpios))
2330 return PTR_ERR(sport->gpios);
2331
2332 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2333 if (IS_ERR(sport->clk_ipg)) {
2334 ret = PTR_ERR(sport->clk_ipg);
2335 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2336 return ret;
2337 }
2338
2339 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2340 if (IS_ERR(sport->clk_per)) {
2341 ret = PTR_ERR(sport->clk_per);
2342 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2343 return ret;
2344 }
2345
2346 sport->port.uartclk = clk_get_rate(sport->clk_per);
2347
2348 /* For register access, we only need to enable the ipg clock. */
2349 ret = clk_prepare_enable(sport->clk_ipg);
2350 if (ret) {
2351 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2352 return ret;
2353 }
2354
2355 /* initialize shadow register values */
2356 sport->ucr1 = readl(sport->port.membase + UCR1);
2357 sport->ucr2 = readl(sport->port.membase + UCR2);
2358 sport->ucr3 = readl(sport->port.membase + UCR3);
2359 sport->ucr4 = readl(sport->port.membase + UCR4);
2360 sport->ufcr = readl(sport->port.membase + UFCR);
2361
2362 ret = uart_get_rs485_mode(&sport->port);
2363 if (ret) {
2364 clk_disable_unprepare(sport->clk_ipg);
2365 return ret;
2366 }
2367
2368 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2369 (!sport->have_rtscts && !sport->have_rtsgpio))
2370 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2371
2372 /*
2373 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2374 * signal cannot be set low during transmission in case the
2375 * receiver is off (limitation of the i.MX UART IP).
2376 */
2377 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2378 sport->have_rtscts && !sport->have_rtsgpio &&
2379 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2380 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2381 dev_err(&pdev->dev,
2382 "low-active RTS not possible when receiver is off, enabling receiver\n");
2383
2384 imx_uart_rs485_config(&sport->port, &sport->port.rs485);
2385
2386 /* Disable interrupts before requesting them */
2387 ucr1 = imx_uart_readl(sport, UCR1);
2388 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2389 imx_uart_writel(sport, ucr1, UCR1);
2390
2391 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2392 /*
2393 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2394 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2395 * and DCD (when they are outputs) or enables the respective
2396 * irqs. So set this bit early, i.e. before requesting irqs.
2397 */
2398 u32 ufcr = imx_uart_readl(sport, UFCR);
2399 if (!(ufcr & UFCR_DCEDTE))
2400 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2401
2402 /*
2403 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2404 * enabled later because they cannot be cleared
2405 * (confirmed on i.MX25) which makes them unusable.
2406 */
2407 imx_uart_writel(sport,
2408 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2409 UCR3);
2410
2411 } else {
2412 u32 ucr3 = UCR3_DSR;
2413 u32 ufcr = imx_uart_readl(sport, UFCR);
2414 if (ufcr & UFCR_DCEDTE)
2415 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2416
2417 if (!imx_uart_is_imx1(sport))
2418 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2419 imx_uart_writel(sport, ucr3, UCR3);
2420 }
2421
2422 clk_disable_unprepare(sport->clk_ipg);
2423
2424 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2425 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2426 sport->trigger_start_tx.function = imx_trigger_start_tx;
2427 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2428
2429 /*
2430 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2431 * chips only have one interrupt.
2432 */
2433 if (txirq > 0) {
2434 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2435 dev_name(&pdev->dev), sport);
2436 if (ret) {
2437 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2438 ret);
2439 return ret;
2440 }
2441
2442 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2443 dev_name(&pdev->dev), sport);
2444 if (ret) {
2445 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2446 ret);
2447 return ret;
2448 }
2449
2450 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2451 dev_name(&pdev->dev), sport);
2452 if (ret) {
2453 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2454 ret);
2455 return ret;
2456 }
2457 } else {
2458 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2459 dev_name(&pdev->dev), sport);
2460 if (ret) {
2461 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2462 return ret;
2463 }
2464 }
2465
2466 imx_uart_ports[sport->port.line] = sport;
2467
2468 platform_set_drvdata(pdev, sport);
2469
2470 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2471 }
2472
imx_uart_remove(struct platform_device * pdev)2473 static int imx_uart_remove(struct platform_device *pdev)
2474 {
2475 struct imx_port *sport = platform_get_drvdata(pdev);
2476
2477 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2478 }
2479
imx_uart_restore_context(struct imx_port * sport)2480 static void imx_uart_restore_context(struct imx_port *sport)
2481 {
2482 unsigned long flags;
2483
2484 spin_lock_irqsave(&sport->port.lock, flags);
2485 if (!sport->context_saved) {
2486 spin_unlock_irqrestore(&sport->port.lock, flags);
2487 return;
2488 }
2489
2490 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2491 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2492 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2493 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2494 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2495 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2496 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2497 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2498 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2499 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2500 sport->context_saved = false;
2501 spin_unlock_irqrestore(&sport->port.lock, flags);
2502 }
2503
imx_uart_save_context(struct imx_port * sport)2504 static void imx_uart_save_context(struct imx_port *sport)
2505 {
2506 unsigned long flags;
2507
2508 /* Save necessary regs */
2509 spin_lock_irqsave(&sport->port.lock, flags);
2510 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2511 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2512 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2513 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2514 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2515 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2516 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2517 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2518 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2519 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2520 sport->context_saved = true;
2521 spin_unlock_irqrestore(&sport->port.lock, flags);
2522 }
2523
imx_uart_enable_wakeup(struct imx_port * sport,bool on)2524 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2525 {
2526 u32 ucr3;
2527
2528 ucr3 = imx_uart_readl(sport, UCR3);
2529 if (on) {
2530 imx_uart_writel(sport, USR1_AWAKE, USR1);
2531 ucr3 |= UCR3_AWAKEN;
2532 } else {
2533 ucr3 &= ~UCR3_AWAKEN;
2534 }
2535 imx_uart_writel(sport, ucr3, UCR3);
2536
2537 if (sport->have_rtscts) {
2538 u32 ucr1 = imx_uart_readl(sport, UCR1);
2539 if (on)
2540 ucr1 |= UCR1_RTSDEN;
2541 else
2542 ucr1 &= ~UCR1_RTSDEN;
2543 imx_uart_writel(sport, ucr1, UCR1);
2544 }
2545 }
2546
imx_uart_suspend_noirq(struct device * dev)2547 static int imx_uart_suspend_noirq(struct device *dev)
2548 {
2549 struct imx_port *sport = dev_get_drvdata(dev);
2550
2551 imx_uart_save_context(sport);
2552
2553 clk_disable(sport->clk_ipg);
2554
2555 pinctrl_pm_select_sleep_state(dev);
2556
2557 return 0;
2558 }
2559
imx_uart_resume_noirq(struct device * dev)2560 static int imx_uart_resume_noirq(struct device *dev)
2561 {
2562 struct imx_port *sport = dev_get_drvdata(dev);
2563 int ret;
2564
2565 pinctrl_pm_select_default_state(dev);
2566
2567 ret = clk_enable(sport->clk_ipg);
2568 if (ret)
2569 return ret;
2570
2571 imx_uart_restore_context(sport);
2572
2573 return 0;
2574 }
2575
imx_uart_suspend(struct device * dev)2576 static int imx_uart_suspend(struct device *dev)
2577 {
2578 struct imx_port *sport = dev_get_drvdata(dev);
2579 int ret;
2580
2581 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2582 disable_irq(sport->port.irq);
2583
2584 ret = clk_prepare_enable(sport->clk_ipg);
2585 if (ret)
2586 return ret;
2587
2588 /* enable wakeup from i.MX UART */
2589 imx_uart_enable_wakeup(sport, true);
2590
2591 return 0;
2592 }
2593
imx_uart_resume(struct device * dev)2594 static int imx_uart_resume(struct device *dev)
2595 {
2596 struct imx_port *sport = dev_get_drvdata(dev);
2597
2598 /* disable wakeup from i.MX UART */
2599 imx_uart_enable_wakeup(sport, false);
2600
2601 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2602 enable_irq(sport->port.irq);
2603
2604 clk_disable_unprepare(sport->clk_ipg);
2605
2606 return 0;
2607 }
2608
imx_uart_freeze(struct device * dev)2609 static int imx_uart_freeze(struct device *dev)
2610 {
2611 struct imx_port *sport = dev_get_drvdata(dev);
2612
2613 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2614
2615 return clk_prepare_enable(sport->clk_ipg);
2616 }
2617
imx_uart_thaw(struct device * dev)2618 static int imx_uart_thaw(struct device *dev)
2619 {
2620 struct imx_port *sport = dev_get_drvdata(dev);
2621
2622 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2623
2624 clk_disable_unprepare(sport->clk_ipg);
2625
2626 return 0;
2627 }
2628
2629 static const struct dev_pm_ops imx_uart_pm_ops = {
2630 .suspend_noirq = imx_uart_suspend_noirq,
2631 .resume_noirq = imx_uart_resume_noirq,
2632 .freeze_noirq = imx_uart_suspend_noirq,
2633 .restore_noirq = imx_uart_resume_noirq,
2634 .suspend = imx_uart_suspend,
2635 .resume = imx_uart_resume,
2636 .freeze = imx_uart_freeze,
2637 .thaw = imx_uart_thaw,
2638 .restore = imx_uart_thaw,
2639 };
2640
2641 static struct platform_driver imx_uart_platform_driver = {
2642 .probe = imx_uart_probe,
2643 .remove = imx_uart_remove,
2644
2645 .id_table = imx_uart_devtype,
2646 .driver = {
2647 .name = "imx-uart",
2648 .of_match_table = imx_uart_dt_ids,
2649 .pm = &imx_uart_pm_ops,
2650 },
2651 };
2652
imx_uart_init(void)2653 static int __init imx_uart_init(void)
2654 {
2655 int ret = uart_register_driver(&imx_uart_uart_driver);
2656
2657 if (ret)
2658 return ret;
2659
2660 ret = platform_driver_register(&imx_uart_platform_driver);
2661 if (ret != 0)
2662 uart_unregister_driver(&imx_uart_uart_driver);
2663
2664 return ret;
2665 }
2666
imx_uart_exit(void)2667 static void __exit imx_uart_exit(void)
2668 {
2669 platform_driver_unregister(&imx_uart_platform_driver);
2670 uart_unregister_driver(&imx_uart_uart_driver);
2671 }
2672
2673 module_init(imx_uart_init);
2674 module_exit(imx_uart_exit);
2675
2676 MODULE_AUTHOR("Sascha Hauer");
2677 MODULE_DESCRIPTION("IMX generic serial port driver");
2678 MODULE_LICENSE("GPL");
2679 MODULE_ALIAS("platform:imx-uart");
2680