1 /** 2 * Copyright 2021 Huawei Technologies Co., Ltd 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 #ifndef MINDSPORE_LITE_SRC_DELEGATE_TENSORRT_OP_POOL_TENSORRT_H_ 17 #define MINDSPORE_LITE_SRC_DELEGATE_TENSORRT_OP_POOL_TENSORRT_H_ 18 #include <string> 19 #include <vector> 20 #include "src/delegate/tensorrt/op/tensorrt_op.h" 21 22 namespace mindspore::lite { 23 class PoolTensorRT : public TensorRTOp { 24 public: PoolTensorRT(const schema::Primitive * primitive,const std::vector<mindspore::MSTensor> & in_tensors,const std::vector<mindspore::MSTensor> & out_tensors,const std::string & name)25 PoolTensorRT(const schema::Primitive *primitive, const std::vector<mindspore::MSTensor> &in_tensors, 26 const std::vector<mindspore::MSTensor> &out_tensors, const std::string &name) 27 : TensorRTOp(primitive, in_tensors, out_tensors, name) {} 28 29 ~PoolTensorRT() override = default; 30 31 int AddInnerOp(nvinfer1::INetworkDefinition *network) override; 32 33 int IsSupport(const schema::Primitive *primitive, const std::vector<mindspore::MSTensor> &in_tensors, 34 const std::vector<mindspore::MSTensor> &out_tensors) override; 35 36 private: 37 int ParseParams(); 38 39 void AddParams(nvinfer1::IPoolingLayer *pooling_layer); 40 41 std::vector<int64_t> kernel_size_; 42 43 std::vector<int64_t> stride_; 44 45 std::vector<int64_t> padding_; 46 47 nvinfer1::PoolingType pooling_type_; 48 49 schema::PadMode pad_mode_; 50 51 schema::ActivationType activation_type_; 52 }; 53 } // namespace mindspore::lite 54 #endif // MINDSPORE_LITE_SRC_DELEGATE_TENSORRT_OP_POOL_TENSORRT_H_ 55