1 /** 2 * Copyright 2021 Huawei Technologies Co., Ltd 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 #ifndef MINDSPORE_LITE_SRC_DELEGATE_TENSORRT_OP_REDUCE_TENSORRT_H_ 17 #define MINDSPORE_LITE_SRC_DELEGATE_TENSORRT_OP_REDUCE_TENSORRT_H_ 18 19 #include <string> 20 #include <vector> 21 #include <map> 22 #include "src/delegate/tensorrt/op/tensorrt_op.h" 23 24 namespace mindspore::lite { 25 class ReduceTensorRT : public TensorRTOp { 26 public: ReduceTensorRT(const schema::Primitive * primitive,const std::vector<mindspore::MSTensor> & in_tensors,const std::vector<mindspore::MSTensor> & out_tensors,const std::string & name)27 ReduceTensorRT(const schema::Primitive *primitive, const std::vector<mindspore::MSTensor> &in_tensors, 28 const std::vector<mindspore::MSTensor> &out_tensors, const std::string &name) 29 : TensorRTOp(primitive, in_tensors, out_tensors, name) {} 30 31 ~ReduceTensorRT() override = default; 32 33 int AddInnerOp(nvinfer1::INetworkDefinition *network) override; 34 35 int IsSupport(const schema::Primitive *primitive, const std::vector<mindspore::MSTensor> &in_tensors, 36 const std::vector<mindspore::MSTensor> &out_tensors) override; 37 38 private: 39 uint32_t GetAxis(); 40 std::map<schema::ReduceMode, nvinfer1::ReduceOperation> reduce_ops_ = { 41 {schema::ReduceMode::ReduceMode_ReduceMean, nvinfer1::ReduceOperation::kAVG}, 42 {schema::ReduceMode::ReduceMode_ReduceMax, nvinfer1::ReduceOperation::kMAX}, 43 {schema::ReduceMode::ReduceMode_ReduceMin, nvinfer1::ReduceOperation::kMIN}, 44 {schema::ReduceMode::ReduceMode_ReduceProd, nvinfer1::ReduceOperation::kPROD}, 45 {schema::ReduceMode::ReduceMode_ReduceSum, nvinfer1::ReduceOperation::kSUM}, 46 }; 47 nvinfer1::ReduceOperation reduce_op_; 48 Format out_format_; 49 }; 50 } // namespace mindspore::lite 51 #endif // MINDSPORE_LITE_SRC_DELEGATE_TENSORRT_OP_REDUCE_TENSORRT_H_ 52