| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 166 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR()
175 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX()
185 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI()
190 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
205 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
217 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
223 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX()
236 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
242 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0, in emitRRIII()
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| D | MipsMCCodeEmitter.cpp | 98 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| D | Locked.cpp | 89 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
110 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
115 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8632/ |
| D | Locked.cpp | 86 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
112 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
117 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPeephole.cpp | 240 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
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| D | HexagonBitTracker.cpp | 316 unsigned Reg0 = Reg[0].Reg; in evaluate() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 224 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 2063 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
2195 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2365 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDSTLane() local
2749 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDDup() local
2851 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2899 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2921 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2942 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3262 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
3281 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
[all …]
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| D | Thumb2SizeReduction.cpp | 746 Register Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
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| D | ARMAsmPrinter.cpp | 312 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 463 unsigned Reg0 = in emitPrologue() local
481 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 505 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
518 Register Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
556 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
567 Register Reg0 = MBBI->getOperand(0).getReg(); in InsertSEH() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMInstPrinter.cpp | 1437 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1450 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1505 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1552 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 2055 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0); in EmitInstruction() local
2086 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0); in EmitInstruction() local
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| D | X86InstrInfo.cpp | 4943 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in foldMemoryOperandImpl() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 739 uint16_t Reg0 = 0; variable
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 784 unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3, in buildEXP()
1133 Register Reg0 = I.getOperand(3).getReg(); in selectG_INTRINSIC_W_SIDE_EFFECTS() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 174 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in commuteInstructionImpl() local
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| D | RegisterCoalescer.cpp | 2502 unsigned Reg0; in valuesIdentical() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 395 Register Reg0 = MI.getOperand(0).getReg(); in commuteInstructionImpl() local
425 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); in commuteInstructionImpl() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.cpp | 968 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) { in isRegIntersect()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceInstX8664.cpp | 2711 const GPRRegister Reg0 = RegX8664::getEncodedGPR(VarReg0->getRegNum()); in emitIAS() local
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| D | IceInstX8632.cpp | 2784 const GPRRegister Reg0 = RegX8632::getEncodedGPR(VarReg0->getRegNum()); in emitIAS() local
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