1 /** 2 * Copyright 2021 Huawei Technologies Co., Ltd 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 #ifndef MINDSPORE_LITE_SRC_DELEGATE_TENSORRT_OP_RESIZE_TENSORRT_H_ 17 #define MINDSPORE_LITE_SRC_DELEGATE_TENSORRT_OP_RESIZE_TENSORRT_H_ 18 19 #include <string> 20 #include <vector> 21 #include <map> 22 #include "src/delegate/tensorrt/op/tensorrt_op.h" 23 24 namespace mindspore::lite { 25 class ResizeTensorRT : public TensorRTOp { 26 public: ResizeTensorRT(const schema::Primitive * primitive,const std::vector<mindspore::MSTensor> & in_tensors,const std::vector<mindspore::MSTensor> & out_tensors,const std::string & name)27 ResizeTensorRT(const schema::Primitive *primitive, const std::vector<mindspore::MSTensor> &in_tensors, 28 const std::vector<mindspore::MSTensor> &out_tensors, const std::string &name) 29 : TensorRTOp(primitive, in_tensors, out_tensors, name) {} 30 31 ~ResizeTensorRT() override = default; 32 33 int AddInnerOp(nvinfer1::INetworkDefinition *network) override; 34 35 int IsSupport(const schema::Primitive *primitive, const std::vector<mindspore::MSTensor> &in_tensors, 36 const std::vector<mindspore::MSTensor> &out_tensors) override; 37 38 private: 39 int SetOutputDims(nvinfer1::ITensor *resize_in_tensor, nvinfer1::IResizeLayer *resize_layer); 40 41 bool IsScaleOutputDim(const std::vector<int64_t> &in_shape, const std::vector<int64_t> &out_shape, 42 const std::vector<float> &shape_tensor_val); 43 44 int SetParams(nvinfer1::IResizeLayer *resize_layer); 45 }; 46 } // namespace mindspore::lite 47 #endif // MINDSPORE_LITE_SRC_DELEGATE_TENSORRT_OP_RESIZE_TENSORRT_H_ 48