1 /* 2 * Copyright © 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 */ 25 26 #ifndef AC_SHADOWED_REGS 27 #define AC_SHADOWED_REGS 28 29 #include "ac_gpu_info.h" 30 31 struct radeon_cmdbuf; 32 33 struct ac_reg_range { 34 unsigned offset; 35 unsigned size; 36 }; 37 38 enum ac_reg_range_type 39 { 40 SI_REG_RANGE_UCONFIG, 41 SI_REG_RANGE_CONTEXT, 42 SI_REG_RANGE_SH, 43 SI_REG_RANGE_CS_SH, 44 SI_NUM_SHADOWED_REG_RANGES, 45 46 SI_REG_RANGE_NON_SHADOWED = SI_NUM_SHADOWED_REG_RANGES, 47 SI_NUM_ALL_REG_RANGES, 48 }; 49 50 #ifdef __cplusplus 51 extern "C" { 52 #endif 53 54 typedef void (*set_context_reg_seq_array_fn)(struct radeon_cmdbuf *cs, unsigned reg, unsigned num, 55 const uint32_t *values); 56 57 void ac_get_reg_ranges(enum chip_class chip_class, enum radeon_family family, 58 enum ac_reg_range_type type, unsigned *num_ranges, 59 const struct ac_reg_range **ranges); 60 void ac_emulate_clear_state(const struct radeon_info *info, struct radeon_cmdbuf *cs, 61 set_context_reg_seq_array_fn set_context_reg_seq_array); 62 void ac_check_shadowed_regs(enum chip_class chip_class, enum radeon_family family, 63 unsigned reg_offset, unsigned count); 64 void ac_print_shadowed_regs(const struct radeon_info *info); 65 66 #ifdef __cplusplus 67 } 68 #endif 69 70 71 #endif 72