• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /**
2  * Copyright 2021 Huawei Technologies Co., Ltd
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 #ifndef MINDSPORE_LITE_SRC_DELEGATE_TENSORRT_OP_SCALE_TENSORRT_H_
17 #define MINDSPORE_LITE_SRC_DELEGATE_TENSORRT_OP_SCALE_TENSORRT_H_
18 #include <string>
19 #include <vector>
20 #include "src/delegate/tensorrt/op/tensorrt_op.h"
21 
22 using mindspore::lite::RET_ERROR;
23 using mindspore::lite::RET_OK;
24 namespace mindspore::lite {
25 class ScaleTensorRT : public TensorRTOp {
26  public:
ScaleTensorRT(const schema::Primitive * primitive,const std::vector<mindspore::MSTensor> & in_tensors,const std::vector<mindspore::MSTensor> & out_tensors,const std::string & name)27   ScaleTensorRT(const schema::Primitive *primitive, const std::vector<mindspore::MSTensor> &in_tensors,
28                 const std::vector<mindspore::MSTensor> &out_tensors, const std::string &name)
29       : TensorRTOp(primitive, in_tensors, out_tensors, name) {}
30 
31   ~ScaleTensorRT() override = default;
32 
33   int AddInnerOp(nvinfer1::INetworkDefinition *network) override;
34 
35   int IsSupport(const schema::Primitive *primitive, const std::vector<mindspore::MSTensor> &in_tensors,
36                 const std::vector<mindspore::MSTensor> &out_tensors) override;
37 
38  private:
39   nvinfer1::ITensor *AddUnsqueezeOp(nvinfer1::INetworkDefinition *network);
40 
41   nvinfer1::ITensor *AddSqueezeOp(nvinfer1::ITensor *in_tensor, nvinfer1::INetworkDefinition *network);
42 
43   nvinfer1::ScaleMode GetScaleMode(int64_t axis);
44 
45   nvinfer1::ITensor *PreProcessInputTensor(nvinfer1::INetworkDefinition *network);
46 
47   Format out_format_;
48 
49   nvinfer1::ScaleMode mode_;
50 };
51 }  // namespace mindspore::lite
52 #endif  // MINDSPORE_LITE_SRC_DELEGATE_TENSORRT_OP_SCALE_TENSORRT_H_
53