Searched defs:SuperRC (Results 1 – 11 of 11) sorted by relevance
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SILoadStoreOptimizer.cpp | 982 const TargetRegisterClass *SuperRC = in mergeRead2Pair() local 1124 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeImagePair() local 1177 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeSBufferLoadImmPair() local 1228 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeBufferLoadPair() local 1290 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeTBufferLoadPair() local 1362 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeTBufferStorePair() local 1524 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeBufferStorePair() local
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D | SIInstrInfo.cpp | 3864 const TargetRegisterClass *SuperRC, in buildExtractSubReg() 3897 const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm() 3936 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF); in isLegalRegOperand() local
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D | AMDGPUISelDAGToDAG.cpp | 596 const TargetRegisterClass *SuperRC = in getOperandRegClass() local
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D | SIISelLowering.cpp | 3324 const TargetRegisterClass *SuperRC, in computeIndirectRegAndOffset()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
D | HexagonRegisterInfo.cpp | 331 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) in getHexagonSubRegIndex() local
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D | HexagonCopyToCombine.cpp | 588 const TargetRegisterClass *SuperRC = nullptr; in combine() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
D | MachineCopyPropagation.cpp | 435 const TargetRegisterClass *SuperRC = UseDstRC; in isForwardableRegClassCopy() local
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D | AggressiveAntiDepBreaker.cpp | 629 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
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D | RegAllocGreedy.cpp | 2065 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() 2105 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
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D | TargetLoweringBase.cpp | 1128 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
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D | MachineVerifier.cpp | 1790 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
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