1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
3
4 #include <linux/printk.h>
5 #include <linux/dynamic_debug.h>
6 #include <linux/netdevice.h>
7 #include <linux/etherdevice.h>
8 #include <linux/if_vlan.h>
9 #include <linux/rtnetlink.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/cpumask.h>
13
14 #include "ionic.h"
15 #include "ionic_bus.h"
16 #include "ionic_lif.h"
17 #include "ionic_txrx.h"
18 #include "ionic_ethtool.h"
19 #include "ionic_debugfs.h"
20
21 /* queuetype support level */
22 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = {
23 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */
24 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */
25 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */
26 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support
27 * 1 = ... with Tx SG version 1
28 */
29 };
30
31 static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode);
32 static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr);
33 static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr);
34 static void ionic_link_status_check(struct ionic_lif *lif);
35 static void ionic_lif_handle_fw_down(struct ionic_lif *lif);
36 static void ionic_lif_handle_fw_up(struct ionic_lif *lif);
37 static void ionic_lif_set_netdev_info(struct ionic_lif *lif);
38
39 static void ionic_txrx_deinit(struct ionic_lif *lif);
40 static int ionic_txrx_init(struct ionic_lif *lif);
41 static int ionic_start_queues(struct ionic_lif *lif);
42 static void ionic_stop_queues(struct ionic_lif *lif);
43 static void ionic_lif_queue_identify(struct ionic_lif *lif);
44
ionic_dim_work(struct work_struct * work)45 static void ionic_dim_work(struct work_struct *work)
46 {
47 struct dim *dim = container_of(work, struct dim, work);
48 struct dim_cq_moder cur_moder;
49 struct ionic_qcq *qcq;
50 u32 new_coal;
51
52 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
53 qcq = container_of(dim, struct ionic_qcq, dim);
54 new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec);
55 new_coal = new_coal ? new_coal : 1;
56
57 if (qcq->intr.dim_coal_hw != new_coal) {
58 unsigned int qi = qcq->cq.bound_q->index;
59 struct ionic_lif *lif = qcq->q.lif;
60
61 qcq->intr.dim_coal_hw = new_coal;
62
63 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
64 lif->rxqcqs[qi]->intr.index,
65 qcq->intr.dim_coal_hw);
66 }
67
68 dim->state = DIM_START_MEASURE;
69 }
70
ionic_lif_deferred_work(struct work_struct * work)71 static void ionic_lif_deferred_work(struct work_struct *work)
72 {
73 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work);
74 struct ionic_deferred *def = &lif->deferred;
75 struct ionic_deferred_work *w = NULL;
76
77 do {
78 spin_lock_bh(&def->lock);
79 if (!list_empty(&def->list)) {
80 w = list_first_entry(&def->list,
81 struct ionic_deferred_work, list);
82 list_del(&w->list);
83 }
84 spin_unlock_bh(&def->lock);
85
86 if (!w)
87 break;
88
89 switch (w->type) {
90 case IONIC_DW_TYPE_RX_MODE:
91 ionic_lif_rx_mode(lif, w->rx_mode);
92 break;
93 case IONIC_DW_TYPE_RX_ADDR_ADD:
94 ionic_lif_addr_add(lif, w->addr);
95 break;
96 case IONIC_DW_TYPE_RX_ADDR_DEL:
97 ionic_lif_addr_del(lif, w->addr);
98 break;
99 case IONIC_DW_TYPE_LINK_STATUS:
100 ionic_link_status_check(lif);
101 break;
102 case IONIC_DW_TYPE_LIF_RESET:
103 if (w->fw_status)
104 ionic_lif_handle_fw_up(lif);
105 else
106 ionic_lif_handle_fw_down(lif);
107 break;
108 default:
109 break;
110 }
111 kfree(w);
112 w = NULL;
113 } while (true);
114 }
115
ionic_lif_deferred_enqueue(struct ionic_deferred * def,struct ionic_deferred_work * work)116 void ionic_lif_deferred_enqueue(struct ionic_deferred *def,
117 struct ionic_deferred_work *work)
118 {
119 spin_lock_bh(&def->lock);
120 list_add_tail(&work->list, &def->list);
121 spin_unlock_bh(&def->lock);
122 schedule_work(&def->work);
123 }
124
ionic_link_status_check(struct ionic_lif * lif)125 static void ionic_link_status_check(struct ionic_lif *lif)
126 {
127 struct net_device *netdev = lif->netdev;
128 u16 link_status;
129 bool link_up;
130
131 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
132 return;
133
134 link_status = le16_to_cpu(lif->info->status.link_status);
135 link_up = link_status == IONIC_PORT_OPER_STATUS_UP;
136
137 if (link_up) {
138 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) {
139 mutex_lock(&lif->queue_lock);
140 ionic_start_queues(lif);
141 mutex_unlock(&lif->queue_lock);
142 }
143
144 if (!netif_carrier_ok(netdev)) {
145 u32 link_speed;
146
147 ionic_port_identify(lif->ionic);
148 link_speed = le32_to_cpu(lif->info->status.link_speed);
149 netdev_info(netdev, "Link up - %d Gbps\n",
150 link_speed / 1000);
151 netif_carrier_on(netdev);
152 }
153 } else {
154 if (netif_carrier_ok(netdev)) {
155 netdev_info(netdev, "Link down\n");
156 netif_carrier_off(netdev);
157 }
158
159 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) {
160 mutex_lock(&lif->queue_lock);
161 ionic_stop_queues(lif);
162 mutex_unlock(&lif->queue_lock);
163 }
164 }
165
166 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
167 }
168
ionic_link_status_check_request(struct ionic_lif * lif,bool can_sleep)169 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep)
170 {
171 struct ionic_deferred_work *work;
172
173 /* we only need one request outstanding at a time */
174 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
175 return;
176
177 if (!can_sleep) {
178 work = kzalloc(sizeof(*work), GFP_ATOMIC);
179 if (!work) {
180 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
181 return;
182 }
183
184 work->type = IONIC_DW_TYPE_LINK_STATUS;
185 ionic_lif_deferred_enqueue(&lif->deferred, work);
186 } else {
187 ionic_link_status_check(lif);
188 }
189 }
190
ionic_isr(int irq,void * data)191 static irqreturn_t ionic_isr(int irq, void *data)
192 {
193 struct napi_struct *napi = data;
194
195 napi_schedule_irqoff(napi);
196
197 return IRQ_HANDLED;
198 }
199
ionic_request_irq(struct ionic_lif * lif,struct ionic_qcq * qcq)200 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq)
201 {
202 struct ionic_intr_info *intr = &qcq->intr;
203 struct device *dev = lif->ionic->dev;
204 struct ionic_queue *q = &qcq->q;
205 const char *name;
206
207 if (lif->registered)
208 name = lif->netdev->name;
209 else
210 name = dev_name(dev);
211
212 snprintf(intr->name, sizeof(intr->name),
213 "%s-%s-%s", IONIC_DRV_NAME, name, q->name);
214
215 return devm_request_irq(dev, intr->vector, ionic_isr,
216 0, intr->name, &qcq->napi);
217 }
218
ionic_intr_alloc(struct ionic_lif * lif,struct ionic_intr_info * intr)219 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
220 {
221 struct ionic *ionic = lif->ionic;
222 int index;
223
224 index = find_first_zero_bit(ionic->intrs, ionic->nintrs);
225 if (index == ionic->nintrs) {
226 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n",
227 __func__, index, ionic->nintrs);
228 return -ENOSPC;
229 }
230
231 set_bit(index, ionic->intrs);
232 ionic_intr_init(&ionic->idev, intr, index);
233
234 return 0;
235 }
236
ionic_intr_free(struct ionic * ionic,int index)237 static void ionic_intr_free(struct ionic *ionic, int index)
238 {
239 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs)
240 clear_bit(index, ionic->intrs);
241 }
242
ionic_qcq_enable(struct ionic_qcq * qcq)243 static int ionic_qcq_enable(struct ionic_qcq *qcq)
244 {
245 struct ionic_queue *q = &qcq->q;
246 struct ionic_lif *lif = q->lif;
247 struct ionic_dev *idev;
248 struct device *dev;
249
250 struct ionic_admin_ctx ctx = {
251 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
252 .cmd.q_control = {
253 .opcode = IONIC_CMD_Q_CONTROL,
254 .lif_index = cpu_to_le16(lif->index),
255 .type = q->type,
256 .index = cpu_to_le32(q->index),
257 .oper = IONIC_Q_ENABLE,
258 },
259 };
260
261 idev = &lif->ionic->idev;
262 dev = lif->ionic->dev;
263
264 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n",
265 ctx.cmd.q_control.index, ctx.cmd.q_control.type);
266
267 if (qcq->flags & IONIC_QCQ_F_INTR) {
268 irq_set_affinity_hint(qcq->intr.vector,
269 &qcq->intr.affinity_mask);
270 napi_enable(&qcq->napi);
271 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index);
272 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
273 IONIC_INTR_MASK_CLEAR);
274 }
275
276 return ionic_adminq_post_wait(lif, &ctx);
277 }
278
ionic_qcq_disable(struct ionic_qcq * qcq,bool send_to_hw)279 static int ionic_qcq_disable(struct ionic_qcq *qcq, bool send_to_hw)
280 {
281 struct ionic_queue *q;
282 struct ionic_lif *lif;
283 int err = 0;
284
285 struct ionic_admin_ctx ctx = {
286 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
287 .cmd.q_control = {
288 .opcode = IONIC_CMD_Q_CONTROL,
289 .oper = IONIC_Q_DISABLE,
290 },
291 };
292
293 if (!qcq)
294 return -ENXIO;
295
296 q = &qcq->q;
297 lif = q->lif;
298
299 if (qcq->flags & IONIC_QCQ_F_INTR) {
300 struct ionic_dev *idev = &lif->ionic->idev;
301
302 cancel_work_sync(&qcq->dim.work);
303 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
304 IONIC_INTR_MASK_SET);
305 synchronize_irq(qcq->intr.vector);
306 irq_set_affinity_hint(qcq->intr.vector, NULL);
307 napi_disable(&qcq->napi);
308 }
309
310 if (send_to_hw) {
311 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index);
312 ctx.cmd.q_control.type = q->type;
313 ctx.cmd.q_control.index = cpu_to_le32(q->index);
314 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n",
315 ctx.cmd.q_control.index, ctx.cmd.q_control.type);
316
317 err = ionic_adminq_post_wait(lif, &ctx);
318 }
319
320 return err;
321 }
322
ionic_lif_qcq_deinit(struct ionic_lif * lif,struct ionic_qcq * qcq)323 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
324 {
325 struct ionic_dev *idev = &lif->ionic->idev;
326
327 if (!qcq)
328 return;
329
330 if (!(qcq->flags & IONIC_QCQ_F_INITED))
331 return;
332
333 if (qcq->flags & IONIC_QCQ_F_INTR) {
334 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
335 IONIC_INTR_MASK_SET);
336 netif_napi_del(&qcq->napi);
337 }
338
339 qcq->flags &= ~IONIC_QCQ_F_INITED;
340 }
341
ionic_qcq_intr_free(struct ionic_lif * lif,struct ionic_qcq * qcq)342 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq)
343 {
344 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0)
345 return;
346
347 irq_set_affinity_hint(qcq->intr.vector, NULL);
348 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi);
349 qcq->intr.vector = 0;
350 ionic_intr_free(lif->ionic, qcq->intr.index);
351 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
352 }
353
ionic_qcq_free(struct ionic_lif * lif,struct ionic_qcq * qcq)354 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq)
355 {
356 struct device *dev = lif->ionic->dev;
357
358 if (!qcq)
359 return;
360
361 ionic_debugfs_del_qcq(qcq);
362
363 if (qcq->q_base) {
364 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa);
365 qcq->q_base = NULL;
366 qcq->q_base_pa = 0;
367 }
368
369 if (qcq->cq_base) {
370 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa);
371 qcq->cq_base = NULL;
372 qcq->cq_base_pa = 0;
373 }
374
375 if (qcq->sg_base) {
376 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa);
377 qcq->sg_base = NULL;
378 qcq->sg_base_pa = 0;
379 }
380
381 ionic_qcq_intr_free(lif, qcq);
382
383 if (qcq->cq.info) {
384 devm_kfree(dev, qcq->cq.info);
385 qcq->cq.info = NULL;
386 }
387 if (qcq->q.info) {
388 devm_kfree(dev, qcq->q.info);
389 qcq->q.info = NULL;
390 }
391 }
392
ionic_qcqs_free(struct ionic_lif * lif)393 static void ionic_qcqs_free(struct ionic_lif *lif)
394 {
395 struct device *dev = lif->ionic->dev;
396
397 if (lif->notifyqcq) {
398 ionic_qcq_free(lif, lif->notifyqcq);
399 devm_kfree(dev, lif->notifyqcq);
400 lif->notifyqcq = NULL;
401 }
402
403 if (lif->adminqcq) {
404 ionic_qcq_free(lif, lif->adminqcq);
405 devm_kfree(dev, lif->adminqcq);
406 lif->adminqcq = NULL;
407 }
408
409 if (lif->rxqcqs) {
410 devm_kfree(dev, lif->rxqstats);
411 lif->rxqstats = NULL;
412 devm_kfree(dev, lif->rxqcqs);
413 lif->rxqcqs = NULL;
414 }
415
416 if (lif->txqcqs) {
417 devm_kfree(dev, lif->txqstats);
418 lif->txqstats = NULL;
419 devm_kfree(dev, lif->txqcqs);
420 lif->txqcqs = NULL;
421 }
422 }
423
ionic_link_qcq_interrupts(struct ionic_qcq * src_qcq,struct ionic_qcq * n_qcq)424 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq,
425 struct ionic_qcq *n_qcq)
426 {
427 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) {
428 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index);
429 n_qcq->flags &= ~IONIC_QCQ_F_INTR;
430 }
431
432 n_qcq->intr.vector = src_qcq->intr.vector;
433 n_qcq->intr.index = src_qcq->intr.index;
434 }
435
ionic_alloc_qcq_interrupt(struct ionic_lif * lif,struct ionic_qcq * qcq)436 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq)
437 {
438 int err;
439
440 if (!(qcq->flags & IONIC_QCQ_F_INTR)) {
441 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
442 return 0;
443 }
444
445 err = ionic_intr_alloc(lif, &qcq->intr);
446 if (err) {
447 netdev_warn(lif->netdev, "no intr for %s: %d\n",
448 qcq->q.name, err);
449 goto err_out;
450 }
451
452 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index);
453 if (err < 0) {
454 netdev_warn(lif->netdev, "no vector for %s: %d\n",
455 qcq->q.name, err);
456 goto err_out_free_intr;
457 }
458 qcq->intr.vector = err;
459 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index,
460 IONIC_INTR_MASK_SET);
461
462 err = ionic_request_irq(lif, qcq);
463 if (err) {
464 netdev_warn(lif->netdev, "irq request failed %d\n", err);
465 goto err_out_free_intr;
466 }
467
468 /* try to get the irq on the local numa node first */
469 qcq->intr.cpu = cpumask_local_spread(qcq->intr.index,
470 dev_to_node(lif->ionic->dev));
471 if (qcq->intr.cpu != -1)
472 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask);
473
474 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index);
475 return 0;
476
477 err_out_free_intr:
478 ionic_intr_free(lif->ionic, qcq->intr.index);
479 err_out:
480 return err;
481 }
482
ionic_qcq_alloc(struct ionic_lif * lif,unsigned int type,unsigned int index,const char * name,unsigned int flags,unsigned int num_descs,unsigned int desc_size,unsigned int cq_desc_size,unsigned int sg_desc_size,unsigned int pid,struct ionic_qcq ** qcq)483 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type,
484 unsigned int index,
485 const char *name, unsigned int flags,
486 unsigned int num_descs, unsigned int desc_size,
487 unsigned int cq_desc_size,
488 unsigned int sg_desc_size,
489 unsigned int pid, struct ionic_qcq **qcq)
490 {
491 struct ionic_dev *idev = &lif->ionic->idev;
492 struct device *dev = lif->ionic->dev;
493 void *q_base, *cq_base, *sg_base;
494 dma_addr_t cq_base_pa = 0;
495 dma_addr_t sg_base_pa = 0;
496 dma_addr_t q_base_pa = 0;
497 struct ionic_qcq *new;
498 int err;
499
500 *qcq = NULL;
501
502 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL);
503 if (!new) {
504 netdev_err(lif->netdev, "Cannot allocate queue structure\n");
505 err = -ENOMEM;
506 goto err_out;
507 }
508
509 new->flags = flags;
510
511 new->q.info = devm_kcalloc(dev, num_descs, sizeof(*new->q.info),
512 GFP_KERNEL);
513 if (!new->q.info) {
514 netdev_err(lif->netdev, "Cannot allocate queue info\n");
515 err = -ENOMEM;
516 goto err_out_free_qcq;
517 }
518
519 new->q.type = type;
520
521 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs,
522 desc_size, sg_desc_size, pid);
523 if (err) {
524 netdev_err(lif->netdev, "Cannot initialize queue\n");
525 goto err_out_free_q_info;
526 }
527
528 err = ionic_alloc_qcq_interrupt(lif, new);
529 if (err)
530 goto err_out;
531
532 new->cq.info = devm_kcalloc(dev, num_descs, sizeof(*new->cq.info),
533 GFP_KERNEL);
534 if (!new->cq.info) {
535 netdev_err(lif->netdev, "Cannot allocate completion queue info\n");
536 err = -ENOMEM;
537 goto err_out_free_irq;
538 }
539
540 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size);
541 if (err) {
542 netdev_err(lif->netdev, "Cannot initialize completion queue\n");
543 goto err_out_free_cq_info;
544 }
545
546 if (flags & IONIC_QCQ_F_NOTIFYQ) {
547 int q_size, cq_size;
548
549 /* q & cq need to be contiguous in case of notifyq */
550 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE);
551 cq_size = ALIGN(num_descs * cq_desc_size, PAGE_SIZE);
552
553 new->q_size = PAGE_SIZE + q_size + cq_size;
554 new->q_base = dma_alloc_coherent(dev, new->q_size,
555 &new->q_base_pa, GFP_KERNEL);
556 if (!new->q_base) {
557 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n");
558 err = -ENOMEM;
559 goto err_out_free_cq_info;
560 }
561 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE);
562 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE);
563 ionic_q_map(&new->q, q_base, q_base_pa);
564
565 cq_base = PTR_ALIGN(q_base + q_size, PAGE_SIZE);
566 cq_base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE);
567 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
568 ionic_cq_bind(&new->cq, &new->q);
569 } else {
570 new->q_size = PAGE_SIZE + (num_descs * desc_size);
571 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa,
572 GFP_KERNEL);
573 if (!new->q_base) {
574 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n");
575 err = -ENOMEM;
576 goto err_out_free_cq_info;
577 }
578 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE);
579 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE);
580 ionic_q_map(&new->q, q_base, q_base_pa);
581
582 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size);
583 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa,
584 GFP_KERNEL);
585 if (!new->cq_base) {
586 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n");
587 err = -ENOMEM;
588 goto err_out_free_q;
589 }
590 cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE);
591 cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE);
592 ionic_cq_map(&new->cq, cq_base, cq_base_pa);
593 ionic_cq_bind(&new->cq, &new->q);
594 }
595
596 if (flags & IONIC_QCQ_F_SG) {
597 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size);
598 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa,
599 GFP_KERNEL);
600 if (!new->sg_base) {
601 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n");
602 err = -ENOMEM;
603 goto err_out_free_cq;
604 }
605 sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE);
606 sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE);
607 ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
608 }
609
610 INIT_WORK(&new->dim.work, ionic_dim_work);
611 new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
612
613 *qcq = new;
614
615 return 0;
616
617 err_out_free_cq:
618 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa);
619 err_out_free_q:
620 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa);
621 err_out_free_cq_info:
622 devm_kfree(dev, new->cq.info);
623 err_out_free_irq:
624 if (flags & IONIC_QCQ_F_INTR) {
625 devm_free_irq(dev, new->intr.vector, &new->napi);
626 ionic_intr_free(lif->ionic, new->intr.index);
627 }
628 err_out_free_q_info:
629 devm_kfree(dev, new->q.info);
630 err_out_free_qcq:
631 devm_kfree(dev, new);
632 err_out:
633 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err);
634 return err;
635 }
636
ionic_qcqs_alloc(struct ionic_lif * lif)637 static int ionic_qcqs_alloc(struct ionic_lif *lif)
638 {
639 struct device *dev = lif->ionic->dev;
640 unsigned int flags;
641 int err;
642
643 flags = IONIC_QCQ_F_INTR;
644 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
645 IONIC_ADMINQ_LENGTH,
646 sizeof(struct ionic_admin_cmd),
647 sizeof(struct ionic_admin_comp),
648 0, lif->kern_pid, &lif->adminqcq);
649 if (err)
650 return err;
651 ionic_debugfs_add_qcq(lif, lif->adminqcq);
652
653 if (lif->ionic->nnqs_per_lif) {
654 flags = IONIC_QCQ_F_NOTIFYQ;
655 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq",
656 flags, IONIC_NOTIFYQ_LENGTH,
657 sizeof(struct ionic_notifyq_cmd),
658 sizeof(union ionic_notifyq_comp),
659 0, lif->kern_pid, &lif->notifyqcq);
660 if (err)
661 goto err_out;
662 ionic_debugfs_add_qcq(lif, lif->notifyqcq);
663
664 /* Let the notifyq ride on the adminq interrupt */
665 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq);
666 }
667
668 err = -ENOMEM;
669 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif,
670 sizeof(struct ionic_qcq *), GFP_KERNEL);
671 if (!lif->txqcqs)
672 goto err_out;
673 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif,
674 sizeof(struct ionic_qcq *), GFP_KERNEL);
675 if (!lif->rxqcqs)
676 goto err_out;
677
678 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif,
679 sizeof(struct ionic_tx_stats), GFP_KERNEL);
680 if (!lif->txqstats)
681 goto err_out;
682 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif,
683 sizeof(struct ionic_rx_stats), GFP_KERNEL);
684 if (!lif->rxqstats)
685 goto err_out;
686
687 return 0;
688
689 err_out:
690 ionic_qcqs_free(lif);
691 return err;
692 }
693
ionic_qcq_sanitize(struct ionic_qcq * qcq)694 static void ionic_qcq_sanitize(struct ionic_qcq *qcq)
695 {
696 qcq->q.tail_idx = 0;
697 qcq->q.head_idx = 0;
698 qcq->cq.tail_idx = 0;
699 qcq->cq.done_color = 1;
700 memset(qcq->q_base, 0, qcq->q_size);
701 memset(qcq->cq_base, 0, qcq->cq_size);
702 memset(qcq->sg_base, 0, qcq->sg_size);
703 }
704
ionic_lif_txq_init(struct ionic_lif * lif,struct ionic_qcq * qcq)705 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
706 {
707 struct device *dev = lif->ionic->dev;
708 struct ionic_queue *q = &qcq->q;
709 struct ionic_cq *cq = &qcq->cq;
710 struct ionic_admin_ctx ctx = {
711 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
712 .cmd.q_init = {
713 .opcode = IONIC_CMD_Q_INIT,
714 .lif_index = cpu_to_le16(lif->index),
715 .type = q->type,
716 .ver = lif->qtype_info[q->type].version,
717 .index = cpu_to_le32(q->index),
718 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
719 IONIC_QINIT_F_SG),
720 .pid = cpu_to_le16(q->pid),
721 .ring_size = ilog2(q->num_descs),
722 .ring_base = cpu_to_le64(q->base_pa),
723 .cq_ring_base = cpu_to_le64(cq->base_pa),
724 .sg_ring_base = cpu_to_le64(q->sg_base_pa),
725 },
726 };
727 unsigned int intr_index;
728 int err;
729
730 if (qcq->flags & IONIC_QCQ_F_INTR)
731 intr_index = qcq->intr.index;
732 else
733 intr_index = lif->rxqcqs[q->index]->intr.index;
734 ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index);
735
736 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid);
737 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index);
738 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
739 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
740 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags);
741 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver);
742 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index);
743
744 ionic_qcq_sanitize(qcq);
745
746 err = ionic_adminq_post_wait(lif, &ctx);
747 if (err)
748 return err;
749
750 q->hw_type = ctx.comp.q_init.hw_type;
751 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
752 q->dbval = IONIC_DBELL_QID(q->hw_index);
753
754 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type);
755 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index);
756
757 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
758 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi,
759 NAPI_POLL_WEIGHT);
760
761 qcq->flags |= IONIC_QCQ_F_INITED;
762
763 return 0;
764 }
765
ionic_lif_rxq_init(struct ionic_lif * lif,struct ionic_qcq * qcq)766 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
767 {
768 struct device *dev = lif->ionic->dev;
769 struct ionic_queue *q = &qcq->q;
770 struct ionic_cq *cq = &qcq->cq;
771 struct ionic_admin_ctx ctx = {
772 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
773 .cmd.q_init = {
774 .opcode = IONIC_CMD_Q_INIT,
775 .lif_index = cpu_to_le16(lif->index),
776 .type = q->type,
777 .ver = lif->qtype_info[q->type].version,
778 .index = cpu_to_le32(q->index),
779 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
780 IONIC_QINIT_F_SG),
781 .intr_index = cpu_to_le16(cq->bound_intr->index),
782 .pid = cpu_to_le16(q->pid),
783 .ring_size = ilog2(q->num_descs),
784 .ring_base = cpu_to_le64(q->base_pa),
785 .cq_ring_base = cpu_to_le64(cq->base_pa),
786 .sg_ring_base = cpu_to_le64(q->sg_base_pa),
787 },
788 };
789 int err;
790
791 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid);
792 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index);
793 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
794 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
795 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags);
796 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver);
797 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index);
798
799 ionic_qcq_sanitize(qcq);
800
801 err = ionic_adminq_post_wait(lif, &ctx);
802 if (err)
803 return err;
804
805 q->hw_type = ctx.comp.q_init.hw_type;
806 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
807 q->dbval = IONIC_DBELL_QID(q->hw_index);
808
809 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type);
810 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index);
811
812 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
813 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi,
814 NAPI_POLL_WEIGHT);
815 else
816 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi,
817 NAPI_POLL_WEIGHT);
818
819 qcq->flags |= IONIC_QCQ_F_INITED;
820
821 return 0;
822 }
823
ionic_notifyq_service(struct ionic_cq * cq,struct ionic_cq_info * cq_info)824 static bool ionic_notifyq_service(struct ionic_cq *cq,
825 struct ionic_cq_info *cq_info)
826 {
827 union ionic_notifyq_comp *comp = cq_info->cq_desc;
828 struct ionic_deferred_work *work;
829 struct net_device *netdev;
830 struct ionic_queue *q;
831 struct ionic_lif *lif;
832 u64 eid;
833
834 q = cq->bound_q;
835 lif = q->info[0].cb_arg;
836 netdev = lif->netdev;
837 eid = le64_to_cpu(comp->event.eid);
838
839 /* Have we run out of new completions to process? */
840 if ((s64)(eid - lif->last_eid) <= 0)
841 return false;
842
843 lif->last_eid = eid;
844
845 dev_dbg(lif->ionic->dev, "notifyq event:\n");
846 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1,
847 comp, sizeof(*comp), true);
848
849 switch (le16_to_cpu(comp->event.ecode)) {
850 case IONIC_EVENT_LINK_CHANGE:
851 ionic_link_status_check_request(lif, false);
852 break;
853 case IONIC_EVENT_RESET:
854 work = kzalloc(sizeof(*work), GFP_ATOMIC);
855 if (!work) {
856 netdev_err(lif->netdev, "%s OOM\n", __func__);
857 } else {
858 work->type = IONIC_DW_TYPE_LIF_RESET;
859 ionic_lif_deferred_enqueue(&lif->deferred, work);
860 }
861 break;
862 default:
863 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n",
864 comp->event.ecode, eid);
865 break;
866 }
867
868 return true;
869 }
870
ionic_adminq_service(struct ionic_cq * cq,struct ionic_cq_info * cq_info)871 static bool ionic_adminq_service(struct ionic_cq *cq,
872 struct ionic_cq_info *cq_info)
873 {
874 struct ionic_admin_comp *comp = cq_info->cq_desc;
875
876 if (!color_match(comp->color, cq->done_color))
877 return false;
878
879 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index));
880
881 return true;
882 }
883
ionic_adminq_napi(struct napi_struct * napi,int budget)884 static int ionic_adminq_napi(struct napi_struct *napi, int budget)
885 {
886 struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr;
887 struct ionic_lif *lif = napi_to_cq(napi)->lif;
888 struct ionic_dev *idev = &lif->ionic->idev;
889 unsigned int flags = 0;
890 int n_work = 0;
891 int a_work = 0;
892 int work_done;
893
894 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED)
895 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget,
896 ionic_notifyq_service, NULL, NULL);
897
898 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED)
899 a_work = ionic_cq_service(&lif->adminqcq->cq, budget,
900 ionic_adminq_service, NULL, NULL);
901
902 work_done = max(n_work, a_work);
903 if (work_done < budget && napi_complete_done(napi, work_done)) {
904 flags |= IONIC_INTR_CRED_UNMASK;
905 lif->adminqcq->cq.bound_intr->rearm_count++;
906 }
907
908 if (work_done || flags) {
909 flags |= IONIC_INTR_CRED_RESET_COALESCE;
910 ionic_intr_credits(idev->intr_ctrl,
911 intr->index,
912 n_work + a_work, flags);
913 }
914
915 return work_done;
916 }
917
ionic_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * ns)918 void ionic_get_stats64(struct net_device *netdev,
919 struct rtnl_link_stats64 *ns)
920 {
921 struct ionic_lif *lif = netdev_priv(netdev);
922 struct ionic_lif_stats *ls;
923
924 memset(ns, 0, sizeof(*ns));
925 ls = &lif->info->stats;
926
927 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) +
928 le64_to_cpu(ls->rx_mcast_packets) +
929 le64_to_cpu(ls->rx_bcast_packets);
930
931 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) +
932 le64_to_cpu(ls->tx_mcast_packets) +
933 le64_to_cpu(ls->tx_bcast_packets);
934
935 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) +
936 le64_to_cpu(ls->rx_mcast_bytes) +
937 le64_to_cpu(ls->rx_bcast_bytes);
938
939 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) +
940 le64_to_cpu(ls->tx_mcast_bytes) +
941 le64_to_cpu(ls->tx_bcast_bytes);
942
943 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) +
944 le64_to_cpu(ls->rx_mcast_drop_packets) +
945 le64_to_cpu(ls->rx_bcast_drop_packets);
946
947 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) +
948 le64_to_cpu(ls->tx_mcast_drop_packets) +
949 le64_to_cpu(ls->tx_bcast_drop_packets);
950
951 ns->multicast = le64_to_cpu(ls->rx_mcast_packets);
952
953 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty);
954
955 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) +
956 le64_to_cpu(ls->rx_queue_disabled) +
957 le64_to_cpu(ls->rx_desc_fetch_error) +
958 le64_to_cpu(ls->rx_desc_data_error);
959
960 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) +
961 le64_to_cpu(ls->tx_queue_disabled) +
962 le64_to_cpu(ls->tx_desc_fetch_error) +
963 le64_to_cpu(ls->tx_desc_data_error);
964
965 ns->rx_errors = ns->rx_over_errors +
966 ns->rx_missed_errors;
967
968 ns->tx_errors = ns->tx_aborted_errors;
969 }
970
ionic_lif_addr_add(struct ionic_lif * lif,const u8 * addr)971 static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr)
972 {
973 struct ionic_admin_ctx ctx = {
974 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
975 .cmd.rx_filter_add = {
976 .opcode = IONIC_CMD_RX_FILTER_ADD,
977 .lif_index = cpu_to_le16(lif->index),
978 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_MAC),
979 },
980 };
981 struct ionic_rx_filter *f;
982 int err;
983
984 /* don't bother if we already have it */
985 spin_lock_bh(&lif->rx_filters.lock);
986 f = ionic_rx_filter_by_addr(lif, addr);
987 spin_unlock_bh(&lif->rx_filters.lock);
988 if (f)
989 return 0;
990
991 netdev_dbg(lif->netdev, "rx_filter add ADDR %pM\n", addr);
992
993 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, ETH_ALEN);
994 err = ionic_adminq_post_wait(lif, &ctx);
995 if (err && err != -EEXIST)
996 return err;
997
998 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx);
999 }
1000
ionic_lif_addr_del(struct ionic_lif * lif,const u8 * addr)1001 static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr)
1002 {
1003 struct ionic_admin_ctx ctx = {
1004 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1005 .cmd.rx_filter_del = {
1006 .opcode = IONIC_CMD_RX_FILTER_DEL,
1007 .lif_index = cpu_to_le16(lif->index),
1008 },
1009 };
1010 struct ionic_rx_filter *f;
1011 int err;
1012
1013 spin_lock_bh(&lif->rx_filters.lock);
1014 f = ionic_rx_filter_by_addr(lif, addr);
1015 if (!f) {
1016 spin_unlock_bh(&lif->rx_filters.lock);
1017 return -ENOENT;
1018 }
1019
1020 netdev_dbg(lif->netdev, "rx_filter del ADDR %pM (id %d)\n",
1021 addr, f->filter_id);
1022
1023 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id);
1024 ionic_rx_filter_free(lif, f);
1025 spin_unlock_bh(&lif->rx_filters.lock);
1026
1027 err = ionic_adminq_post_wait(lif, &ctx);
1028 if (err && err != -EEXIST)
1029 return err;
1030
1031 return 0;
1032 }
1033
ionic_lif_addr(struct ionic_lif * lif,const u8 * addr,bool add,bool can_sleep)1034 static int ionic_lif_addr(struct ionic_lif *lif, const u8 *addr, bool add,
1035 bool can_sleep)
1036 {
1037 struct ionic_deferred_work *work;
1038 unsigned int nmfilters;
1039 unsigned int nufilters;
1040
1041 if (add) {
1042 /* Do we have space for this filter? We test the counters
1043 * here before checking the need for deferral so that we
1044 * can return an overflow error to the stack.
1045 */
1046 nmfilters = le32_to_cpu(lif->identity->eth.max_mcast_filters);
1047 nufilters = le32_to_cpu(lif->identity->eth.max_ucast_filters);
1048
1049 if ((is_multicast_ether_addr(addr) && lif->nmcast < nmfilters))
1050 lif->nmcast++;
1051 else if (!is_multicast_ether_addr(addr) &&
1052 lif->nucast < nufilters)
1053 lif->nucast++;
1054 else
1055 return -ENOSPC;
1056 } else {
1057 if (is_multicast_ether_addr(addr) && lif->nmcast)
1058 lif->nmcast--;
1059 else if (!is_multicast_ether_addr(addr) && lif->nucast)
1060 lif->nucast--;
1061 }
1062
1063 if (!can_sleep) {
1064 work = kzalloc(sizeof(*work), GFP_ATOMIC);
1065 if (!work) {
1066 netdev_err(lif->netdev, "%s OOM\n", __func__);
1067 return -ENOMEM;
1068 }
1069 work->type = add ? IONIC_DW_TYPE_RX_ADDR_ADD :
1070 IONIC_DW_TYPE_RX_ADDR_DEL;
1071 memcpy(work->addr, addr, ETH_ALEN);
1072 netdev_dbg(lif->netdev, "deferred: rx_filter %s %pM\n",
1073 add ? "add" : "del", addr);
1074 ionic_lif_deferred_enqueue(&lif->deferred, work);
1075 } else {
1076 netdev_dbg(lif->netdev, "rx_filter %s %pM\n",
1077 add ? "add" : "del", addr);
1078 if (add)
1079 return ionic_lif_addr_add(lif, addr);
1080 else
1081 return ionic_lif_addr_del(lif, addr);
1082 }
1083
1084 return 0;
1085 }
1086
ionic_addr_add(struct net_device * netdev,const u8 * addr)1087 static int ionic_addr_add(struct net_device *netdev, const u8 *addr)
1088 {
1089 return ionic_lif_addr(netdev_priv(netdev), addr, true, true);
1090 }
1091
ionic_ndo_addr_add(struct net_device * netdev,const u8 * addr)1092 static int ionic_ndo_addr_add(struct net_device *netdev, const u8 *addr)
1093 {
1094 return ionic_lif_addr(netdev_priv(netdev), addr, true, false);
1095 }
1096
ionic_addr_del(struct net_device * netdev,const u8 * addr)1097 static int ionic_addr_del(struct net_device *netdev, const u8 *addr)
1098 {
1099 /* Don't delete our own address from the uc list */
1100 if (ether_addr_equal(addr, netdev->dev_addr))
1101 return 0;
1102
1103 return ionic_lif_addr(netdev_priv(netdev), addr, false, true);
1104 }
1105
ionic_ndo_addr_del(struct net_device * netdev,const u8 * addr)1106 static int ionic_ndo_addr_del(struct net_device *netdev, const u8 *addr)
1107 {
1108 return ionic_lif_addr(netdev_priv(netdev), addr, false, false);
1109 }
1110
ionic_lif_rx_mode(struct ionic_lif * lif,unsigned int rx_mode)1111 static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode)
1112 {
1113 struct ionic_admin_ctx ctx = {
1114 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1115 .cmd.rx_mode_set = {
1116 .opcode = IONIC_CMD_RX_MODE_SET,
1117 .lif_index = cpu_to_le16(lif->index),
1118 .rx_mode = cpu_to_le16(rx_mode),
1119 },
1120 };
1121 char buf[128];
1122 int err;
1123 int i;
1124 #define REMAIN(__x) (sizeof(buf) - (__x))
1125
1126 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:",
1127 lif->rx_mode, rx_mode);
1128 if (rx_mode & IONIC_RX_MODE_F_UNICAST)
1129 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST");
1130 if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
1131 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST");
1132 if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
1133 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST");
1134 if (rx_mode & IONIC_RX_MODE_F_PROMISC)
1135 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC");
1136 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
1137 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI");
1138 netdev_dbg(lif->netdev, "lif%d %s\n", lif->index, buf);
1139
1140 err = ionic_adminq_post_wait(lif, &ctx);
1141 if (err)
1142 netdev_warn(lif->netdev, "set rx_mode 0x%04x failed: %d\n",
1143 rx_mode, err);
1144 else
1145 lif->rx_mode = rx_mode;
1146 }
1147
ionic_set_rx_mode(struct net_device * netdev,bool can_sleep)1148 static void ionic_set_rx_mode(struct net_device *netdev, bool can_sleep)
1149 {
1150 struct ionic_lif *lif = netdev_priv(netdev);
1151 struct ionic_deferred_work *work;
1152 unsigned int nfilters;
1153 unsigned int rx_mode;
1154
1155 rx_mode = IONIC_RX_MODE_F_UNICAST;
1156 rx_mode |= (netdev->flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0;
1157 rx_mode |= (netdev->flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0;
1158 rx_mode |= (netdev->flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0;
1159 rx_mode |= (netdev->flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0;
1160
1161 /* sync unicast addresses
1162 * next check to see if we're in an overflow state
1163 * if so, we track that we overflowed and enable NIC PROMISC
1164 * else if the overflow is set and not needed
1165 * we remove our overflow flag and check the netdev flags
1166 * to see if we can disable NIC PROMISC
1167 */
1168 if (can_sleep)
1169 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del);
1170 else
1171 __dev_uc_sync(netdev, ionic_ndo_addr_add, ionic_ndo_addr_del);
1172 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters);
1173 if (netdev_uc_count(netdev) + 1 > nfilters) {
1174 rx_mode |= IONIC_RX_MODE_F_PROMISC;
1175 lif->uc_overflow = true;
1176 } else if (lif->uc_overflow) {
1177 lif->uc_overflow = false;
1178 if (!(netdev->flags & IFF_PROMISC))
1179 rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
1180 }
1181
1182 /* same for multicast */
1183 if (can_sleep)
1184 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del);
1185 else
1186 __dev_mc_sync(netdev, ionic_ndo_addr_add, ionic_ndo_addr_del);
1187 nfilters = le32_to_cpu(lif->identity->eth.max_mcast_filters);
1188 if (netdev_mc_count(netdev) > nfilters) {
1189 rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
1190 lif->mc_overflow = true;
1191 } else if (lif->mc_overflow) {
1192 lif->mc_overflow = false;
1193 if (!(netdev->flags & IFF_ALLMULTI))
1194 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
1195 }
1196
1197 if (lif->rx_mode != rx_mode) {
1198 if (!can_sleep) {
1199 work = kzalloc(sizeof(*work), GFP_ATOMIC);
1200 if (!work) {
1201 netdev_err(lif->netdev, "%s OOM\n", __func__);
1202 return;
1203 }
1204 work->type = IONIC_DW_TYPE_RX_MODE;
1205 work->rx_mode = rx_mode;
1206 netdev_dbg(lif->netdev, "deferred: rx_mode\n");
1207 ionic_lif_deferred_enqueue(&lif->deferred, work);
1208 } else {
1209 ionic_lif_rx_mode(lif, rx_mode);
1210 }
1211 }
1212 }
1213
ionic_ndo_set_rx_mode(struct net_device * netdev)1214 static void ionic_ndo_set_rx_mode(struct net_device *netdev)
1215 {
1216 ionic_set_rx_mode(netdev, false);
1217 }
1218
ionic_netdev_features_to_nic(netdev_features_t features)1219 static __le64 ionic_netdev_features_to_nic(netdev_features_t features)
1220 {
1221 u64 wanted = 0;
1222
1223 if (features & NETIF_F_HW_VLAN_CTAG_TX)
1224 wanted |= IONIC_ETH_HW_VLAN_TX_TAG;
1225 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1226 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP;
1227 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1228 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER;
1229 if (features & NETIF_F_RXHASH)
1230 wanted |= IONIC_ETH_HW_RX_HASH;
1231 if (features & NETIF_F_RXCSUM)
1232 wanted |= IONIC_ETH_HW_RX_CSUM;
1233 if (features & NETIF_F_SG)
1234 wanted |= IONIC_ETH_HW_TX_SG;
1235 if (features & NETIF_F_HW_CSUM)
1236 wanted |= IONIC_ETH_HW_TX_CSUM;
1237 if (features & NETIF_F_TSO)
1238 wanted |= IONIC_ETH_HW_TSO;
1239 if (features & NETIF_F_TSO6)
1240 wanted |= IONIC_ETH_HW_TSO_IPV6;
1241 if (features & NETIF_F_TSO_ECN)
1242 wanted |= IONIC_ETH_HW_TSO_ECN;
1243 if (features & NETIF_F_GSO_GRE)
1244 wanted |= IONIC_ETH_HW_TSO_GRE;
1245 if (features & NETIF_F_GSO_GRE_CSUM)
1246 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM;
1247 if (features & NETIF_F_GSO_IPXIP4)
1248 wanted |= IONIC_ETH_HW_TSO_IPXIP4;
1249 if (features & NETIF_F_GSO_IPXIP6)
1250 wanted |= IONIC_ETH_HW_TSO_IPXIP6;
1251 if (features & NETIF_F_GSO_UDP_TUNNEL)
1252 wanted |= IONIC_ETH_HW_TSO_UDP;
1253 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM)
1254 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM;
1255
1256 return cpu_to_le64(wanted);
1257 }
1258
ionic_set_nic_features(struct ionic_lif * lif,netdev_features_t features)1259 static int ionic_set_nic_features(struct ionic_lif *lif,
1260 netdev_features_t features)
1261 {
1262 struct device *dev = lif->ionic->dev;
1263 struct ionic_admin_ctx ctx = {
1264 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1265 .cmd.lif_setattr = {
1266 .opcode = IONIC_CMD_LIF_SETATTR,
1267 .index = cpu_to_le16(lif->index),
1268 .attr = IONIC_LIF_ATTR_FEATURES,
1269 },
1270 };
1271 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG |
1272 IONIC_ETH_HW_VLAN_RX_STRIP |
1273 IONIC_ETH_HW_VLAN_RX_FILTER;
1274 u64 old_hw_features;
1275 int err;
1276
1277 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features);
1278 err = ionic_adminq_post_wait(lif, &ctx);
1279 if (err)
1280 return err;
1281
1282 old_hw_features = lif->hw_features;
1283 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features &
1284 ctx.comp.lif_setattr.features);
1285
1286 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH)
1287 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
1288
1289 if ((vlan_flags & features) &&
1290 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features)))
1291 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n");
1292
1293 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1294 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n");
1295 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1296 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n");
1297 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1298 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n");
1299 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1300 dev_dbg(dev, "feature ETH_HW_RX_HASH\n");
1301 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1302 dev_dbg(dev, "feature ETH_HW_TX_SG\n");
1303 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1304 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n");
1305 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1306 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n");
1307 if (lif->hw_features & IONIC_ETH_HW_TSO)
1308 dev_dbg(dev, "feature ETH_HW_TSO\n");
1309 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1310 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n");
1311 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1312 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n");
1313 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1314 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n");
1315 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1316 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n");
1317 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1318 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n");
1319 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1320 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n");
1321 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1322 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n");
1323 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1324 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n");
1325
1326 return 0;
1327 }
1328
ionic_init_nic_features(struct ionic_lif * lif)1329 static int ionic_init_nic_features(struct ionic_lif *lif)
1330 {
1331 struct net_device *netdev = lif->netdev;
1332 netdev_features_t features;
1333 int err;
1334
1335 /* set up what we expect to support by default */
1336 features = NETIF_F_HW_VLAN_CTAG_TX |
1337 NETIF_F_HW_VLAN_CTAG_RX |
1338 NETIF_F_HW_VLAN_CTAG_FILTER |
1339 NETIF_F_RXHASH |
1340 NETIF_F_SG |
1341 NETIF_F_HW_CSUM |
1342 NETIF_F_RXCSUM |
1343 NETIF_F_TSO |
1344 NETIF_F_TSO6 |
1345 NETIF_F_TSO_ECN;
1346
1347 err = ionic_set_nic_features(lif, features);
1348 if (err)
1349 return err;
1350
1351 /* tell the netdev what we actually can support */
1352 netdev->features |= NETIF_F_HIGHDMA;
1353
1354 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
1355 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
1356 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
1357 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1358 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
1359 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1360 if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
1361 netdev->hw_features |= NETIF_F_RXHASH;
1362 if (lif->hw_features & IONIC_ETH_HW_TX_SG)
1363 netdev->hw_features |= NETIF_F_SG;
1364
1365 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
1366 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
1367 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
1368 netdev->hw_enc_features |= NETIF_F_RXCSUM;
1369 if (lif->hw_features & IONIC_ETH_HW_TSO)
1370 netdev->hw_enc_features |= NETIF_F_TSO;
1371 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
1372 netdev->hw_enc_features |= NETIF_F_TSO6;
1373 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
1374 netdev->hw_enc_features |= NETIF_F_TSO_ECN;
1375 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
1376 netdev->hw_enc_features |= NETIF_F_GSO_GRE;
1377 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
1378 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM;
1379 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
1380 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4;
1381 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
1382 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6;
1383 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
1384 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
1385 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
1386 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
1387
1388 netdev->hw_features |= netdev->hw_enc_features;
1389 netdev->features |= netdev->hw_features;
1390 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES;
1391
1392 netdev->priv_flags |= IFF_UNICAST_FLT |
1393 IFF_LIVE_ADDR_CHANGE;
1394
1395 return 0;
1396 }
1397
ionic_set_features(struct net_device * netdev,netdev_features_t features)1398 static int ionic_set_features(struct net_device *netdev,
1399 netdev_features_t features)
1400 {
1401 struct ionic_lif *lif = netdev_priv(netdev);
1402 int err;
1403
1404 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n",
1405 __func__, (u64)lif->netdev->features, (u64)features);
1406
1407 err = ionic_set_nic_features(lif, features);
1408
1409 return err;
1410 }
1411
ionic_set_mac_address(struct net_device * netdev,void * sa)1412 static int ionic_set_mac_address(struct net_device *netdev, void *sa)
1413 {
1414 struct sockaddr *addr = sa;
1415 u8 *mac;
1416 int err;
1417
1418 mac = (u8 *)addr->sa_data;
1419 if (ether_addr_equal(netdev->dev_addr, mac))
1420 return 0;
1421
1422 err = eth_prepare_mac_addr_change(netdev, addr);
1423 if (err)
1424 return err;
1425
1426 if (!is_zero_ether_addr(netdev->dev_addr)) {
1427 netdev_info(netdev, "deleting mac addr %pM\n",
1428 netdev->dev_addr);
1429 ionic_addr_del(netdev, netdev->dev_addr);
1430 }
1431
1432 eth_commit_mac_addr_change(netdev, addr);
1433 netdev_info(netdev, "updating mac addr %pM\n", mac);
1434
1435 return ionic_addr_add(netdev, mac);
1436 }
1437
ionic_stop_queues_reconfig(struct ionic_lif * lif)1438 static void ionic_stop_queues_reconfig(struct ionic_lif *lif)
1439 {
1440 /* Stop and clean the queues before reconfiguration */
1441 mutex_lock(&lif->queue_lock);
1442 netif_device_detach(lif->netdev);
1443 ionic_stop_queues(lif);
1444 ionic_txrx_deinit(lif);
1445 }
1446
ionic_start_queues_reconfig(struct ionic_lif * lif)1447 static int ionic_start_queues_reconfig(struct ionic_lif *lif)
1448 {
1449 int err;
1450
1451 /* Re-init the queues after reconfiguration */
1452
1453 /* The only way txrx_init can fail here is if communication
1454 * with FW is suddenly broken. There's not much we can do
1455 * at this point - error messages have already been printed,
1456 * so we can continue on and the user can eventually do a
1457 * DOWN and UP to try to reset and clear the issue.
1458 */
1459 err = ionic_txrx_init(lif);
1460 mutex_unlock(&lif->queue_lock);
1461 ionic_link_status_check_request(lif, true);
1462 netif_device_attach(lif->netdev);
1463
1464 return err;
1465 }
1466
ionic_change_mtu(struct net_device * netdev,int new_mtu)1467 static int ionic_change_mtu(struct net_device *netdev, int new_mtu)
1468 {
1469 struct ionic_lif *lif = netdev_priv(netdev);
1470 struct ionic_admin_ctx ctx = {
1471 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1472 .cmd.lif_setattr = {
1473 .opcode = IONIC_CMD_LIF_SETATTR,
1474 .index = cpu_to_le16(lif->index),
1475 .attr = IONIC_LIF_ATTR_MTU,
1476 .mtu = cpu_to_le32(new_mtu),
1477 },
1478 };
1479 int err;
1480
1481 err = ionic_adminq_post_wait(lif, &ctx);
1482 if (err)
1483 return err;
1484
1485 netdev->mtu = new_mtu;
1486 /* if we're not running, nothing more to do */
1487 if (!netif_running(netdev))
1488 return 0;
1489
1490 ionic_stop_queues_reconfig(lif);
1491 return ionic_start_queues_reconfig(lif);
1492 }
1493
ionic_tx_timeout_work(struct work_struct * ws)1494 static void ionic_tx_timeout_work(struct work_struct *ws)
1495 {
1496 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work);
1497
1498 netdev_info(lif->netdev, "Tx Timeout recovery\n");
1499
1500 /* if we were stopped before this scheduled job was launched,
1501 * don't bother the queues as they are already stopped.
1502 */
1503 if (!netif_running(lif->netdev))
1504 return;
1505
1506 ionic_stop_queues_reconfig(lif);
1507 ionic_start_queues_reconfig(lif);
1508 }
1509
ionic_tx_timeout(struct net_device * netdev,unsigned int txqueue)1510 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1511 {
1512 struct ionic_lif *lif = netdev_priv(netdev);
1513
1514 schedule_work(&lif->tx_timeout_work);
1515 }
1516
ionic_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)1517 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1518 u16 vid)
1519 {
1520 struct ionic_lif *lif = netdev_priv(netdev);
1521 struct ionic_admin_ctx ctx = {
1522 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1523 .cmd.rx_filter_add = {
1524 .opcode = IONIC_CMD_RX_FILTER_ADD,
1525 .lif_index = cpu_to_le16(lif->index),
1526 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_VLAN),
1527 .vlan.vlan = cpu_to_le16(vid),
1528 },
1529 };
1530 int err;
1531
1532 netdev_dbg(netdev, "rx_filter add VLAN %d\n", vid);
1533 err = ionic_adminq_post_wait(lif, &ctx);
1534 if (err)
1535 return err;
1536
1537 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx);
1538 }
1539
ionic_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)1540 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1541 u16 vid)
1542 {
1543 struct ionic_lif *lif = netdev_priv(netdev);
1544 struct ionic_admin_ctx ctx = {
1545 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1546 .cmd.rx_filter_del = {
1547 .opcode = IONIC_CMD_RX_FILTER_DEL,
1548 .lif_index = cpu_to_le16(lif->index),
1549 },
1550 };
1551 struct ionic_rx_filter *f;
1552
1553 spin_lock_bh(&lif->rx_filters.lock);
1554
1555 f = ionic_rx_filter_by_vlan(lif, vid);
1556 if (!f) {
1557 spin_unlock_bh(&lif->rx_filters.lock);
1558 return -ENOENT;
1559 }
1560
1561 netdev_dbg(netdev, "rx_filter del VLAN %d (id %d)\n",
1562 vid, f->filter_id);
1563
1564 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id);
1565 ionic_rx_filter_free(lif, f);
1566 spin_unlock_bh(&lif->rx_filters.lock);
1567
1568 return ionic_adminq_post_wait(lif, &ctx);
1569 }
1570
ionic_lif_rss_config(struct ionic_lif * lif,const u16 types,const u8 * key,const u32 * indir)1571 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types,
1572 const u8 *key, const u32 *indir)
1573 {
1574 struct ionic_admin_ctx ctx = {
1575 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
1576 .cmd.lif_setattr = {
1577 .opcode = IONIC_CMD_LIF_SETATTR,
1578 .attr = IONIC_LIF_ATTR_RSS,
1579 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa),
1580 },
1581 };
1582 unsigned int i, tbl_sz;
1583
1584 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) {
1585 lif->rss_types = types;
1586 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types);
1587 }
1588
1589 if (key)
1590 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
1591
1592 if (indir) {
1593 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1594 for (i = 0; i < tbl_sz; i++)
1595 lif->rss_ind_tbl[i] = indir[i];
1596 }
1597
1598 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
1599 IONIC_RSS_HASH_KEY_SIZE);
1600
1601 return ionic_adminq_post_wait(lif, &ctx);
1602 }
1603
ionic_lif_rss_init(struct ionic_lif * lif)1604 static int ionic_lif_rss_init(struct ionic_lif *lif)
1605 {
1606 unsigned int tbl_sz;
1607 unsigned int i;
1608
1609 lif->rss_types = IONIC_RSS_TYPE_IPV4 |
1610 IONIC_RSS_TYPE_IPV4_TCP |
1611 IONIC_RSS_TYPE_IPV4_UDP |
1612 IONIC_RSS_TYPE_IPV6 |
1613 IONIC_RSS_TYPE_IPV6_TCP |
1614 IONIC_RSS_TYPE_IPV6_UDP;
1615
1616 /* Fill indirection table with 'default' values */
1617 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1618 for (i = 0; i < tbl_sz; i++)
1619 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs);
1620
1621 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
1622 }
1623
ionic_lif_rss_deinit(struct ionic_lif * lif)1624 static void ionic_lif_rss_deinit(struct ionic_lif *lif)
1625 {
1626 int tbl_sz;
1627
1628 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
1629 memset(lif->rss_ind_tbl, 0, tbl_sz);
1630 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE);
1631
1632 ionic_lif_rss_config(lif, 0x0, NULL, NULL);
1633 }
1634
ionic_txrx_disable(struct ionic_lif * lif)1635 static void ionic_txrx_disable(struct ionic_lif *lif)
1636 {
1637 unsigned int i;
1638 int err = 0;
1639
1640 if (lif->txqcqs) {
1641 for (i = 0; i < lif->nxqs; i++)
1642 err = ionic_qcq_disable(lif->txqcqs[i], (err != -ETIMEDOUT));
1643 }
1644
1645 if (lif->rxqcqs) {
1646 for (i = 0; i < lif->nxqs; i++)
1647 err = ionic_qcq_disable(lif->rxqcqs[i], (err != -ETIMEDOUT));
1648 }
1649 }
1650
ionic_txrx_deinit(struct ionic_lif * lif)1651 static void ionic_txrx_deinit(struct ionic_lif *lif)
1652 {
1653 unsigned int i;
1654
1655 if (lif->txqcqs) {
1656 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) {
1657 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
1658 ionic_tx_flush(&lif->txqcqs[i]->cq);
1659 ionic_tx_empty(&lif->txqcqs[i]->q);
1660 }
1661 }
1662
1663 if (lif->rxqcqs) {
1664 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) {
1665 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]);
1666 ionic_rx_empty(&lif->rxqcqs[i]->q);
1667 }
1668 }
1669 lif->rx_mode = 0;
1670 }
1671
ionic_txrx_free(struct ionic_lif * lif)1672 static void ionic_txrx_free(struct ionic_lif *lif)
1673 {
1674 unsigned int i;
1675
1676 if (lif->txqcqs) {
1677 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) {
1678 ionic_qcq_free(lif, lif->txqcqs[i]);
1679 devm_kfree(lif->ionic->dev, lif->txqcqs[i]);
1680 lif->txqcqs[i] = NULL;
1681 }
1682 }
1683
1684 if (lif->rxqcqs) {
1685 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) {
1686 ionic_qcq_free(lif, lif->rxqcqs[i]);
1687 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]);
1688 lif->rxqcqs[i] = NULL;
1689 }
1690 }
1691 }
1692
ionic_txrx_alloc(struct ionic_lif * lif)1693 static int ionic_txrx_alloc(struct ionic_lif *lif)
1694 {
1695 unsigned int sg_desc_sz;
1696 unsigned int flags;
1697 unsigned int i;
1698 int err = 0;
1699
1700 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
1701 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz ==
1702 sizeof(struct ionic_txq_sg_desc_v1))
1703 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
1704 else
1705 sg_desc_sz = sizeof(struct ionic_txq_sg_desc);
1706
1707 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG;
1708 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
1709 flags |= IONIC_QCQ_F_INTR;
1710 for (i = 0; i < lif->nxqs; i++) {
1711 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
1712 lif->ntxq_descs,
1713 sizeof(struct ionic_txq_desc),
1714 sizeof(struct ionic_txq_comp),
1715 sg_desc_sz,
1716 lif->kern_pid, &lif->txqcqs[i]);
1717 if (err)
1718 goto err_out;
1719
1720 if (flags & IONIC_QCQ_F_INTR) {
1721 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
1722 lif->txqcqs[i]->intr.index,
1723 lif->tx_coalesce_hw);
1724 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state))
1725 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw;
1726 }
1727
1728 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]);
1729 }
1730
1731 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR;
1732 for (i = 0; i < lif->nxqs; i++) {
1733 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
1734 lif->nrxq_descs,
1735 sizeof(struct ionic_rxq_desc),
1736 sizeof(struct ionic_rxq_comp),
1737 sizeof(struct ionic_rxq_sg_desc),
1738 lif->kern_pid, &lif->rxqcqs[i]);
1739 if (err)
1740 goto err_out;
1741
1742 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
1743 lif->rxqcqs[i]->intr.index,
1744 lif->rx_coalesce_hw);
1745 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state))
1746 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw;
1747
1748 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
1749 ionic_link_qcq_interrupts(lif->rxqcqs[i],
1750 lif->txqcqs[i]);
1751
1752 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]);
1753 }
1754
1755 return 0;
1756
1757 err_out:
1758 ionic_txrx_free(lif);
1759
1760 return err;
1761 }
1762
ionic_txrx_init(struct ionic_lif * lif)1763 static int ionic_txrx_init(struct ionic_lif *lif)
1764 {
1765 unsigned int i;
1766 int err;
1767
1768 for (i = 0; i < lif->nxqs; i++) {
1769 err = ionic_lif_txq_init(lif, lif->txqcqs[i]);
1770 if (err)
1771 goto err_out;
1772
1773 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]);
1774 if (err) {
1775 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
1776 goto err_out;
1777 }
1778 }
1779
1780 if (lif->netdev->features & NETIF_F_RXHASH)
1781 ionic_lif_rss_init(lif);
1782
1783 ionic_set_rx_mode(lif->netdev, true);
1784
1785 return 0;
1786
1787 err_out:
1788 while (i--) {
1789 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
1790 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]);
1791 }
1792
1793 return err;
1794 }
1795
ionic_txrx_enable(struct ionic_lif * lif)1796 static int ionic_txrx_enable(struct ionic_lif *lif)
1797 {
1798 int derr = 0;
1799 int i, err;
1800
1801 for (i = 0; i < lif->nxqs; i++) {
1802 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) {
1803 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i);
1804 err = -ENXIO;
1805 goto err_out;
1806 }
1807
1808 ionic_rx_fill(&lif->rxqcqs[i]->q);
1809 err = ionic_qcq_enable(lif->rxqcqs[i]);
1810 if (err)
1811 goto err_out;
1812
1813 err = ionic_qcq_enable(lif->txqcqs[i]);
1814 if (err) {
1815 derr = ionic_qcq_disable(lif->rxqcqs[i], (err != -ETIMEDOUT));
1816 goto err_out;
1817 }
1818 }
1819
1820 return 0;
1821
1822 err_out:
1823 while (i--) {
1824 derr = ionic_qcq_disable(lif->txqcqs[i], (derr != -ETIMEDOUT));
1825 derr = ionic_qcq_disable(lif->rxqcqs[i], (derr != -ETIMEDOUT));
1826 }
1827
1828 return err;
1829 }
1830
ionic_start_queues(struct ionic_lif * lif)1831 static int ionic_start_queues(struct ionic_lif *lif)
1832 {
1833 int err;
1834
1835 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state))
1836 return 0;
1837
1838 err = ionic_txrx_enable(lif);
1839 if (err) {
1840 clear_bit(IONIC_LIF_F_UP, lif->state);
1841 return err;
1842 }
1843 netif_tx_wake_all_queues(lif->netdev);
1844
1845 return 0;
1846 }
1847
ionic_open(struct net_device * netdev)1848 static int ionic_open(struct net_device *netdev)
1849 {
1850 struct ionic_lif *lif = netdev_priv(netdev);
1851 int err;
1852
1853 err = ionic_txrx_alloc(lif);
1854 if (err)
1855 return err;
1856
1857 err = ionic_txrx_init(lif);
1858 if (err)
1859 goto err_out;
1860
1861 err = netif_set_real_num_tx_queues(netdev, lif->nxqs);
1862 if (err)
1863 goto err_txrx_deinit;
1864
1865 err = netif_set_real_num_rx_queues(netdev, lif->nxqs);
1866 if (err)
1867 goto err_txrx_deinit;
1868
1869 /* don't start the queues until we have link */
1870 if (netif_carrier_ok(netdev)) {
1871 err = ionic_start_queues(lif);
1872 if (err)
1873 goto err_txrx_deinit;
1874 }
1875
1876 return 0;
1877
1878 err_txrx_deinit:
1879 ionic_txrx_deinit(lif);
1880 err_out:
1881 ionic_txrx_free(lif);
1882 return err;
1883 }
1884
ionic_stop_queues(struct ionic_lif * lif)1885 static void ionic_stop_queues(struct ionic_lif *lif)
1886 {
1887 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state))
1888 return;
1889
1890 netif_tx_disable(lif->netdev);
1891 ionic_txrx_disable(lif);
1892 }
1893
ionic_stop(struct net_device * netdev)1894 static int ionic_stop(struct net_device *netdev)
1895 {
1896 struct ionic_lif *lif = netdev_priv(netdev);
1897
1898 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
1899 return 0;
1900
1901 ionic_stop_queues(lif);
1902 ionic_txrx_deinit(lif);
1903 ionic_txrx_free(lif);
1904
1905 return 0;
1906 }
1907
ionic_get_vf_config(struct net_device * netdev,int vf,struct ifla_vf_info * ivf)1908 static int ionic_get_vf_config(struct net_device *netdev,
1909 int vf, struct ifla_vf_info *ivf)
1910 {
1911 struct ionic_lif *lif = netdev_priv(netdev);
1912 struct ionic *ionic = lif->ionic;
1913 int ret = 0;
1914
1915 if (!netif_device_present(netdev))
1916 return -EBUSY;
1917
1918 down_read(&ionic->vf_op_lock);
1919
1920 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
1921 ret = -EINVAL;
1922 } else {
1923 ivf->vf = vf;
1924 ivf->vlan = le16_to_cpu(ionic->vfs[vf].vlanid);
1925 ivf->qos = 0;
1926 ivf->spoofchk = ionic->vfs[vf].spoofchk;
1927 ivf->linkstate = ionic->vfs[vf].linkstate;
1928 ivf->max_tx_rate = le32_to_cpu(ionic->vfs[vf].maxrate);
1929 ivf->trusted = ionic->vfs[vf].trusted;
1930 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr);
1931 }
1932
1933 up_read(&ionic->vf_op_lock);
1934 return ret;
1935 }
1936
ionic_get_vf_stats(struct net_device * netdev,int vf,struct ifla_vf_stats * vf_stats)1937 static int ionic_get_vf_stats(struct net_device *netdev, int vf,
1938 struct ifla_vf_stats *vf_stats)
1939 {
1940 struct ionic_lif *lif = netdev_priv(netdev);
1941 struct ionic *ionic = lif->ionic;
1942 struct ionic_lif_stats *vs;
1943 int ret = 0;
1944
1945 if (!netif_device_present(netdev))
1946 return -EBUSY;
1947
1948 down_read(&ionic->vf_op_lock);
1949
1950 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
1951 ret = -EINVAL;
1952 } else {
1953 memset(vf_stats, 0, sizeof(*vf_stats));
1954 vs = &ionic->vfs[vf].stats;
1955
1956 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets);
1957 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets);
1958 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes);
1959 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes);
1960 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets);
1961 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets);
1962 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) +
1963 le64_to_cpu(vs->rx_mcast_drop_packets) +
1964 le64_to_cpu(vs->rx_bcast_drop_packets);
1965 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) +
1966 le64_to_cpu(vs->tx_mcast_drop_packets) +
1967 le64_to_cpu(vs->tx_bcast_drop_packets);
1968 }
1969
1970 up_read(&ionic->vf_op_lock);
1971 return ret;
1972 }
1973
ionic_set_vf_mac(struct net_device * netdev,int vf,u8 * mac)1974 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
1975 {
1976 struct ionic_lif *lif = netdev_priv(netdev);
1977 struct ionic *ionic = lif->ionic;
1978 int ret;
1979
1980 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac)))
1981 return -EINVAL;
1982
1983 if (!netif_device_present(netdev))
1984 return -EBUSY;
1985
1986 down_write(&ionic->vf_op_lock);
1987
1988 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
1989 ret = -EINVAL;
1990 } else {
1991 ret = ionic_set_vf_config(ionic, vf, IONIC_VF_ATTR_MAC, mac);
1992 if (!ret)
1993 ether_addr_copy(ionic->vfs[vf].macaddr, mac);
1994 }
1995
1996 up_write(&ionic->vf_op_lock);
1997 return ret;
1998 }
1999
ionic_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 proto)2000 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2001 u8 qos, __be16 proto)
2002 {
2003 struct ionic_lif *lif = netdev_priv(netdev);
2004 struct ionic *ionic = lif->ionic;
2005 int ret;
2006
2007 /* until someday when we support qos */
2008 if (qos)
2009 return -EINVAL;
2010
2011 if (vlan > 4095)
2012 return -EINVAL;
2013
2014 if (proto != htons(ETH_P_8021Q))
2015 return -EPROTONOSUPPORT;
2016
2017 if (!netif_device_present(netdev))
2018 return -EBUSY;
2019
2020 down_write(&ionic->vf_op_lock);
2021
2022 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2023 ret = -EINVAL;
2024 } else {
2025 ret = ionic_set_vf_config(ionic, vf,
2026 IONIC_VF_ATTR_VLAN, (u8 *)&vlan);
2027 if (!ret)
2028 ionic->vfs[vf].vlanid = cpu_to_le16(vlan);
2029 }
2030
2031 up_write(&ionic->vf_op_lock);
2032 return ret;
2033 }
2034
ionic_set_vf_rate(struct net_device * netdev,int vf,int tx_min,int tx_max)2035 static int ionic_set_vf_rate(struct net_device *netdev, int vf,
2036 int tx_min, int tx_max)
2037 {
2038 struct ionic_lif *lif = netdev_priv(netdev);
2039 struct ionic *ionic = lif->ionic;
2040 int ret;
2041
2042 /* setting the min just seems silly */
2043 if (tx_min)
2044 return -EINVAL;
2045
2046 if (!netif_device_present(netdev))
2047 return -EBUSY;
2048
2049 down_write(&ionic->vf_op_lock);
2050
2051 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2052 ret = -EINVAL;
2053 } else {
2054 ret = ionic_set_vf_config(ionic, vf,
2055 IONIC_VF_ATTR_RATE, (u8 *)&tx_max);
2056 if (!ret)
2057 lif->ionic->vfs[vf].maxrate = cpu_to_le32(tx_max);
2058 }
2059
2060 up_write(&ionic->vf_op_lock);
2061 return ret;
2062 }
2063
ionic_set_vf_spoofchk(struct net_device * netdev,int vf,bool set)2064 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set)
2065 {
2066 struct ionic_lif *lif = netdev_priv(netdev);
2067 struct ionic *ionic = lif->ionic;
2068 u8 data = set; /* convert to u8 for config */
2069 int ret;
2070
2071 if (!netif_device_present(netdev))
2072 return -EBUSY;
2073
2074 down_write(&ionic->vf_op_lock);
2075
2076 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2077 ret = -EINVAL;
2078 } else {
2079 ret = ionic_set_vf_config(ionic, vf,
2080 IONIC_VF_ATTR_SPOOFCHK, &data);
2081 if (!ret)
2082 ionic->vfs[vf].spoofchk = data;
2083 }
2084
2085 up_write(&ionic->vf_op_lock);
2086 return ret;
2087 }
2088
ionic_set_vf_trust(struct net_device * netdev,int vf,bool set)2089 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set)
2090 {
2091 struct ionic_lif *lif = netdev_priv(netdev);
2092 struct ionic *ionic = lif->ionic;
2093 u8 data = set; /* convert to u8 for config */
2094 int ret;
2095
2096 if (!netif_device_present(netdev))
2097 return -EBUSY;
2098
2099 down_write(&ionic->vf_op_lock);
2100
2101 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2102 ret = -EINVAL;
2103 } else {
2104 ret = ionic_set_vf_config(ionic, vf,
2105 IONIC_VF_ATTR_TRUST, &data);
2106 if (!ret)
2107 ionic->vfs[vf].trusted = data;
2108 }
2109
2110 up_write(&ionic->vf_op_lock);
2111 return ret;
2112 }
2113
ionic_set_vf_link_state(struct net_device * netdev,int vf,int set)2114 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set)
2115 {
2116 struct ionic_lif *lif = netdev_priv(netdev);
2117 struct ionic *ionic = lif->ionic;
2118 u8 data;
2119 int ret;
2120
2121 switch (set) {
2122 case IFLA_VF_LINK_STATE_ENABLE:
2123 data = IONIC_VF_LINK_STATUS_UP;
2124 break;
2125 case IFLA_VF_LINK_STATE_DISABLE:
2126 data = IONIC_VF_LINK_STATUS_DOWN;
2127 break;
2128 case IFLA_VF_LINK_STATE_AUTO:
2129 data = IONIC_VF_LINK_STATUS_AUTO;
2130 break;
2131 default:
2132 return -EINVAL;
2133 }
2134
2135 if (!netif_device_present(netdev))
2136 return -EBUSY;
2137
2138 down_write(&ionic->vf_op_lock);
2139
2140 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) {
2141 ret = -EINVAL;
2142 } else {
2143 ret = ionic_set_vf_config(ionic, vf,
2144 IONIC_VF_ATTR_LINKSTATE, &data);
2145 if (!ret)
2146 ionic->vfs[vf].linkstate = set;
2147 }
2148
2149 up_write(&ionic->vf_op_lock);
2150 return ret;
2151 }
2152
2153 static const struct net_device_ops ionic_netdev_ops = {
2154 .ndo_open = ionic_open,
2155 .ndo_stop = ionic_stop,
2156 .ndo_start_xmit = ionic_start_xmit,
2157 .ndo_get_stats64 = ionic_get_stats64,
2158 .ndo_set_rx_mode = ionic_ndo_set_rx_mode,
2159 .ndo_set_features = ionic_set_features,
2160 .ndo_set_mac_address = ionic_set_mac_address,
2161 .ndo_validate_addr = eth_validate_addr,
2162 .ndo_tx_timeout = ionic_tx_timeout,
2163 .ndo_change_mtu = ionic_change_mtu,
2164 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid,
2165 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid,
2166 .ndo_set_vf_vlan = ionic_set_vf_vlan,
2167 .ndo_set_vf_trust = ionic_set_vf_trust,
2168 .ndo_set_vf_mac = ionic_set_vf_mac,
2169 .ndo_set_vf_rate = ionic_set_vf_rate,
2170 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk,
2171 .ndo_get_vf_config = ionic_get_vf_config,
2172 .ndo_set_vf_link_state = ionic_set_vf_link_state,
2173 .ndo_get_vf_stats = ionic_get_vf_stats,
2174 };
2175
ionic_swap_queues(struct ionic_qcq * a,struct ionic_qcq * b)2176 static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b)
2177 {
2178 /* only swapping the queues, not the napi, flags, or other stuff */
2179 swap(a->q.num_descs, b->q.num_descs);
2180 swap(a->q.base, b->q.base);
2181 swap(a->q.base_pa, b->q.base_pa);
2182 swap(a->q.info, b->q.info);
2183 swap(a->q_base, b->q_base);
2184 swap(a->q_base_pa, b->q_base_pa);
2185 swap(a->q_size, b->q_size);
2186
2187 swap(a->q.sg_base, b->q.sg_base);
2188 swap(a->q.sg_base_pa, b->q.sg_base_pa);
2189 swap(a->sg_base, b->sg_base);
2190 swap(a->sg_base_pa, b->sg_base_pa);
2191 swap(a->sg_size, b->sg_size);
2192
2193 swap(a->cq.num_descs, b->cq.num_descs);
2194 swap(a->cq.base, b->cq.base);
2195 swap(a->cq.base_pa, b->cq.base_pa);
2196 swap(a->cq.info, b->cq.info);
2197 swap(a->cq_base, b->cq_base);
2198 swap(a->cq_base_pa, b->cq_base_pa);
2199 swap(a->cq_size, b->cq_size);
2200 }
2201
ionic_reconfigure_queues(struct ionic_lif * lif,struct ionic_queue_params * qparam)2202 int ionic_reconfigure_queues(struct ionic_lif *lif,
2203 struct ionic_queue_params *qparam)
2204 {
2205 struct ionic_qcq **tx_qcqs = NULL;
2206 struct ionic_qcq **rx_qcqs = NULL;
2207 unsigned int sg_desc_sz;
2208 unsigned int flags;
2209 int err = -ENOMEM;
2210 unsigned int i;
2211
2212 /* allocate temporary qcq arrays to hold new queue structs */
2213 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) {
2214 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif,
2215 sizeof(struct ionic_qcq *), GFP_KERNEL);
2216 if (!tx_qcqs)
2217 goto err_out;
2218 }
2219 if (qparam->nxqs != lif->nxqs || qparam->nrxq_descs != lif->nrxq_descs) {
2220 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif,
2221 sizeof(struct ionic_qcq *), GFP_KERNEL);
2222 if (!rx_qcqs)
2223 goto err_out;
2224 }
2225
2226 /* allocate new desc_info and rings, but leave the interrupt setup
2227 * until later so as to not mess with the still-running queues
2228 */
2229 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
2230 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz ==
2231 sizeof(struct ionic_txq_sg_desc_v1))
2232 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
2233 else
2234 sg_desc_sz = sizeof(struct ionic_txq_sg_desc);
2235
2236 if (tx_qcqs) {
2237 for (i = 0; i < qparam->nxqs; i++) {
2238 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR;
2239 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
2240 qparam->ntxq_descs,
2241 sizeof(struct ionic_txq_desc),
2242 sizeof(struct ionic_txq_comp),
2243 sg_desc_sz,
2244 lif->kern_pid, &tx_qcqs[i]);
2245 if (err)
2246 goto err_out;
2247 }
2248 }
2249
2250 if (rx_qcqs) {
2251 for (i = 0; i < qparam->nxqs; i++) {
2252 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR;
2253 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
2254 qparam->nrxq_descs,
2255 sizeof(struct ionic_rxq_desc),
2256 sizeof(struct ionic_rxq_comp),
2257 sizeof(struct ionic_rxq_sg_desc),
2258 lif->kern_pid, &rx_qcqs[i]);
2259 if (err)
2260 goto err_out;
2261 }
2262 }
2263
2264 /* stop and clean the queues */
2265 ionic_stop_queues_reconfig(lif);
2266
2267 if (qparam->nxqs != lif->nxqs) {
2268 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs);
2269 if (err)
2270 goto err_out_reinit_unlock;
2271 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs);
2272 if (err) {
2273 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs);
2274 goto err_out_reinit_unlock;
2275 }
2276 }
2277
2278 /* swap new desc_info and rings, keeping existing interrupt config */
2279 if (tx_qcqs) {
2280 lif->ntxq_descs = qparam->ntxq_descs;
2281 for (i = 0; i < qparam->nxqs; i++)
2282 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]);
2283 }
2284
2285 if (rx_qcqs) {
2286 lif->nrxq_descs = qparam->nrxq_descs;
2287 for (i = 0; i < qparam->nxqs; i++)
2288 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]);
2289 }
2290
2291 /* if we need to change the interrupt layout, this is the time */
2292 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) ||
2293 qparam->nxqs != lif->nxqs) {
2294 if (qparam->intr_split) {
2295 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
2296 } else {
2297 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state);
2298 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs;
2299 lif->tx_coalesce_hw = lif->rx_coalesce_hw;
2300 }
2301
2302 /* clear existing interrupt assignments */
2303 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) {
2304 ionic_qcq_intr_free(lif, lif->txqcqs[i]);
2305 ionic_qcq_intr_free(lif, lif->rxqcqs[i]);
2306 }
2307
2308 /* re-assign the interrupts */
2309 for (i = 0; i < qparam->nxqs; i++) {
2310 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR;
2311 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]);
2312 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
2313 lif->rxqcqs[i]->intr.index,
2314 lif->rx_coalesce_hw);
2315
2316 if (qparam->intr_split) {
2317 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR;
2318 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]);
2319 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
2320 lif->txqcqs[i]->intr.index,
2321 lif->tx_coalesce_hw);
2322 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state))
2323 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw;
2324 } else {
2325 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2326 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]);
2327 }
2328 }
2329 }
2330
2331 /* now we can rework the debugfs mappings */
2332 if (tx_qcqs) {
2333 for (i = 0; i < qparam->nxqs; i++) {
2334 ionic_debugfs_del_qcq(lif->txqcqs[i]);
2335 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]);
2336 }
2337 }
2338
2339 if (rx_qcqs) {
2340 for (i = 0; i < qparam->nxqs; i++) {
2341 ionic_debugfs_del_qcq(lif->rxqcqs[i]);
2342 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]);
2343 }
2344 }
2345
2346 swap(lif->nxqs, qparam->nxqs);
2347
2348 err_out_reinit_unlock:
2349 /* re-init the queues, but don't loose an error code */
2350 if (err)
2351 ionic_start_queues_reconfig(lif);
2352 else
2353 err = ionic_start_queues_reconfig(lif);
2354
2355 err_out:
2356 /* free old allocs without cleaning intr */
2357 for (i = 0; i < qparam->nxqs; i++) {
2358 if (tx_qcqs && tx_qcqs[i]) {
2359 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2360 ionic_qcq_free(lif, tx_qcqs[i]);
2361 devm_kfree(lif->ionic->dev, tx_qcqs[i]);
2362 tx_qcqs[i] = NULL;
2363 }
2364 if (rx_qcqs && rx_qcqs[i]) {
2365 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2366 ionic_qcq_free(lif, rx_qcqs[i]);
2367 devm_kfree(lif->ionic->dev, rx_qcqs[i]);
2368 rx_qcqs[i] = NULL;
2369 }
2370 }
2371
2372 /* free q array */
2373 if (rx_qcqs) {
2374 devm_kfree(lif->ionic->dev, rx_qcqs);
2375 rx_qcqs = NULL;
2376 }
2377 if (tx_qcqs) {
2378 devm_kfree(lif->ionic->dev, tx_qcqs);
2379 tx_qcqs = NULL;
2380 }
2381
2382 /* clean the unused dma and info allocations when new set is smaller
2383 * than the full array, but leave the qcq shells in place
2384 */
2385 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) {
2386 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2387 ionic_qcq_free(lif, lif->txqcqs[i]);
2388
2389 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR;
2390 ionic_qcq_free(lif, lif->rxqcqs[i]);
2391 }
2392
2393 return err;
2394 }
2395
ionic_lif_alloc(struct ionic * ionic)2396 int ionic_lif_alloc(struct ionic *ionic)
2397 {
2398 struct device *dev = ionic->dev;
2399 union ionic_lif_identity *lid;
2400 struct net_device *netdev;
2401 struct ionic_lif *lif;
2402 int tbl_sz;
2403 int err;
2404
2405 lid = kzalloc(sizeof(*lid), GFP_KERNEL);
2406 if (!lid)
2407 return -ENOMEM;
2408
2409 netdev = alloc_etherdev_mqs(sizeof(*lif),
2410 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif);
2411 if (!netdev) {
2412 dev_err(dev, "Cannot allocate netdev, aborting\n");
2413 err = -ENOMEM;
2414 goto err_out_free_lid;
2415 }
2416
2417 SET_NETDEV_DEV(netdev, dev);
2418
2419 lif = netdev_priv(netdev);
2420 lif->netdev = netdev;
2421 ionic->lif = lif;
2422 netdev->netdev_ops = &ionic_netdev_ops;
2423 ionic_ethtool_set_ops(netdev);
2424
2425 netdev->watchdog_timeo = 2 * HZ;
2426 netif_carrier_off(netdev);
2427
2428 lif->identity = lid;
2429 lif->lif_type = IONIC_LIF_TYPE_CLASSIC;
2430 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity);
2431 if (err) {
2432 dev_err(ionic->dev, "Cannot identify type %d: %d\n",
2433 lif->lif_type, err);
2434 goto err_out_free_netdev;
2435 }
2436 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU,
2437 le32_to_cpu(lif->identity->eth.min_frame_size));
2438 lif->netdev->max_mtu =
2439 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN;
2440
2441 lif->neqs = ionic->neqs_per_lif;
2442 lif->nxqs = ionic->ntxqs_per_lif;
2443
2444 lif->ionic = ionic;
2445 lif->index = 0;
2446 lif->ntxq_descs = IONIC_DEF_TXRX_DESC;
2447 lif->nrxq_descs = IONIC_DEF_TXRX_DESC;
2448 lif->tx_budget = IONIC_TX_BUDGET_DEFAULT;
2449
2450 /* Convert the default coalesce value to actual hw resolution */
2451 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT;
2452 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic,
2453 lif->rx_coalesce_usecs);
2454 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs;
2455 lif->tx_coalesce_hw = lif->rx_coalesce_hw;
2456 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state);
2457 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state);
2458
2459 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
2460
2461 spin_lock_init(&lif->adminq_lock);
2462
2463 spin_lock_init(&lif->deferred.lock);
2464 INIT_LIST_HEAD(&lif->deferred.list);
2465 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work);
2466
2467 /* allocate lif info */
2468 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE);
2469 lif->info = dma_alloc_coherent(dev, lif->info_sz,
2470 &lif->info_pa, GFP_KERNEL);
2471 if (!lif->info) {
2472 dev_err(dev, "Failed to allocate lif info, aborting\n");
2473 err = -ENOMEM;
2474 goto err_out_free_netdev;
2475 }
2476
2477 ionic_debugfs_add_lif(lif);
2478
2479 /* allocate control queues and txrx queue arrays */
2480 ionic_lif_queue_identify(lif);
2481 err = ionic_qcqs_alloc(lif);
2482 if (err)
2483 goto err_out_free_lif_info;
2484
2485 /* allocate rss indirection table */
2486 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
2487 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz;
2488 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz,
2489 &lif->rss_ind_tbl_pa,
2490 GFP_KERNEL);
2491
2492 if (!lif->rss_ind_tbl) {
2493 err = -ENOMEM;
2494 dev_err(dev, "Failed to allocate rss indirection table, aborting\n");
2495 goto err_out_free_qcqs;
2496 }
2497 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE);
2498
2499 return 0;
2500
2501 err_out_free_qcqs:
2502 ionic_qcqs_free(lif);
2503 err_out_free_lif_info:
2504 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
2505 lif->info = NULL;
2506 lif->info_pa = 0;
2507 err_out_free_netdev:
2508 free_netdev(lif->netdev);
2509 lif = NULL;
2510 err_out_free_lid:
2511 kfree(lid);
2512
2513 return err;
2514 }
2515
ionic_lif_reset(struct ionic_lif * lif)2516 static void ionic_lif_reset(struct ionic_lif *lif)
2517 {
2518 struct ionic_dev *idev = &lif->ionic->idev;
2519
2520 mutex_lock(&lif->ionic->dev_cmd_lock);
2521 ionic_dev_cmd_lif_reset(idev, lif->index);
2522 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
2523 mutex_unlock(&lif->ionic->dev_cmd_lock);
2524 }
2525
ionic_lif_handle_fw_down(struct ionic_lif * lif)2526 static void ionic_lif_handle_fw_down(struct ionic_lif *lif)
2527 {
2528 struct ionic *ionic = lif->ionic;
2529
2530 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state))
2531 return;
2532
2533 dev_info(ionic->dev, "FW Down: Stopping LIFs\n");
2534
2535 netif_device_detach(lif->netdev);
2536
2537 if (test_bit(IONIC_LIF_F_UP, lif->state)) {
2538 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n");
2539 mutex_lock(&lif->queue_lock);
2540 ionic_stop_queues(lif);
2541 mutex_unlock(&lif->queue_lock);
2542 }
2543
2544 if (netif_running(lif->netdev)) {
2545 ionic_txrx_deinit(lif);
2546 ionic_txrx_free(lif);
2547 }
2548 ionic_lif_deinit(lif);
2549 ionic_reset(ionic);
2550 ionic_qcqs_free(lif);
2551
2552 dev_info(ionic->dev, "FW Down: LIFs stopped\n");
2553 }
2554
ionic_lif_handle_fw_up(struct ionic_lif * lif)2555 static void ionic_lif_handle_fw_up(struct ionic_lif *lif)
2556 {
2557 struct ionic *ionic = lif->ionic;
2558 int err;
2559
2560 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state))
2561 return;
2562
2563 dev_info(ionic->dev, "FW Up: restarting LIFs\n");
2564
2565 ionic_init_devinfo(ionic);
2566 err = ionic_identify(ionic);
2567 if (err)
2568 goto err_out;
2569 err = ionic_port_identify(ionic);
2570 if (err)
2571 goto err_out;
2572 err = ionic_port_init(ionic);
2573 if (err)
2574 goto err_out;
2575 err = ionic_qcqs_alloc(lif);
2576 if (err)
2577 goto err_out;
2578
2579 err = ionic_lif_init(lif);
2580 if (err)
2581 goto err_qcqs_free;
2582
2583 if (lif->registered)
2584 ionic_lif_set_netdev_info(lif);
2585
2586 ionic_rx_filter_replay(lif);
2587
2588 if (netif_running(lif->netdev)) {
2589 err = ionic_txrx_alloc(lif);
2590 if (err)
2591 goto err_lifs_deinit;
2592
2593 err = ionic_txrx_init(lif);
2594 if (err)
2595 goto err_txrx_free;
2596 }
2597
2598 clear_bit(IONIC_LIF_F_FW_RESET, lif->state);
2599 ionic_link_status_check_request(lif, true);
2600 netif_device_attach(lif->netdev);
2601 dev_info(ionic->dev, "FW Up: LIFs restarted\n");
2602
2603 return;
2604
2605 err_txrx_free:
2606 ionic_txrx_free(lif);
2607 err_lifs_deinit:
2608 ionic_lif_deinit(lif);
2609 err_qcqs_free:
2610 ionic_qcqs_free(lif);
2611 err_out:
2612 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err);
2613 }
2614
ionic_lif_free(struct ionic_lif * lif)2615 void ionic_lif_free(struct ionic_lif *lif)
2616 {
2617 struct device *dev = lif->ionic->dev;
2618
2619 /* free rss indirection table */
2620 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl,
2621 lif->rss_ind_tbl_pa);
2622 lif->rss_ind_tbl = NULL;
2623 lif->rss_ind_tbl_pa = 0;
2624
2625 /* free queues */
2626 ionic_qcqs_free(lif);
2627 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state))
2628 ionic_lif_reset(lif);
2629
2630 /* free lif info */
2631 kfree(lif->identity);
2632 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
2633 lif->info = NULL;
2634 lif->info_pa = 0;
2635
2636 /* unmap doorbell page */
2637 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
2638 lif->kern_dbpage = NULL;
2639 kfree(lif->dbid_inuse);
2640 lif->dbid_inuse = NULL;
2641
2642 /* free netdev & lif */
2643 ionic_debugfs_del_lif(lif);
2644 free_netdev(lif->netdev);
2645 }
2646
ionic_lif_deinit(struct ionic_lif * lif)2647 void ionic_lif_deinit(struct ionic_lif *lif)
2648 {
2649 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state))
2650 return;
2651
2652 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
2653 cancel_work_sync(&lif->deferred.work);
2654 cancel_work_sync(&lif->tx_timeout_work);
2655 ionic_rx_filters_deinit(lif);
2656 if (lif->netdev->features & NETIF_F_RXHASH)
2657 ionic_lif_rss_deinit(lif);
2658 }
2659
2660 napi_disable(&lif->adminqcq->napi);
2661 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
2662 ionic_lif_qcq_deinit(lif, lif->adminqcq);
2663
2664 mutex_destroy(&lif->queue_lock);
2665 ionic_lif_reset(lif);
2666 }
2667
ionic_lif_adminq_init(struct ionic_lif * lif)2668 static int ionic_lif_adminq_init(struct ionic_lif *lif)
2669 {
2670 struct device *dev = lif->ionic->dev;
2671 struct ionic_q_init_comp comp;
2672 struct ionic_dev *idev;
2673 struct ionic_qcq *qcq;
2674 struct ionic_queue *q;
2675 int err;
2676
2677 idev = &lif->ionic->idev;
2678 qcq = lif->adminqcq;
2679 q = &qcq->q;
2680
2681 mutex_lock(&lif->ionic->dev_cmd_lock);
2682 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index);
2683 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
2684 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp);
2685 mutex_unlock(&lif->ionic->dev_cmd_lock);
2686 if (err) {
2687 netdev_err(lif->netdev, "adminq init failed %d\n", err);
2688 return err;
2689 }
2690
2691 q->hw_type = comp.hw_type;
2692 q->hw_index = le32_to_cpu(comp.hw_index);
2693 q->dbval = IONIC_DBELL_QID(q->hw_index);
2694
2695 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type);
2696 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index);
2697
2698 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi,
2699 NAPI_POLL_WEIGHT);
2700
2701 napi_enable(&qcq->napi);
2702
2703 if (qcq->flags & IONIC_QCQ_F_INTR)
2704 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
2705 IONIC_INTR_MASK_CLEAR);
2706
2707 qcq->flags |= IONIC_QCQ_F_INITED;
2708
2709 return 0;
2710 }
2711
ionic_lif_notifyq_init(struct ionic_lif * lif)2712 static int ionic_lif_notifyq_init(struct ionic_lif *lif)
2713 {
2714 struct ionic_qcq *qcq = lif->notifyqcq;
2715 struct device *dev = lif->ionic->dev;
2716 struct ionic_queue *q = &qcq->q;
2717 int err;
2718
2719 struct ionic_admin_ctx ctx = {
2720 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
2721 .cmd.q_init = {
2722 .opcode = IONIC_CMD_Q_INIT,
2723 .lif_index = cpu_to_le16(lif->index),
2724 .type = q->type,
2725 .ver = lif->qtype_info[q->type].version,
2726 .index = cpu_to_le32(q->index),
2727 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
2728 IONIC_QINIT_F_ENA),
2729 .intr_index = cpu_to_le16(lif->adminqcq->intr.index),
2730 .pid = cpu_to_le16(q->pid),
2731 .ring_size = ilog2(q->num_descs),
2732 .ring_base = cpu_to_le64(q->base_pa),
2733 }
2734 };
2735
2736 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid);
2737 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index);
2738 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
2739 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
2740
2741 err = ionic_adminq_post_wait(lif, &ctx);
2742 if (err)
2743 return err;
2744
2745 lif->last_eid = 0;
2746 q->hw_type = ctx.comp.q_init.hw_type;
2747 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
2748 q->dbval = IONIC_DBELL_QID(q->hw_index);
2749
2750 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type);
2751 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index);
2752
2753 /* preset the callback info */
2754 q->info[0].cb_arg = lif;
2755
2756 qcq->flags |= IONIC_QCQ_F_INITED;
2757
2758 return 0;
2759 }
2760
ionic_station_set(struct ionic_lif * lif)2761 static int ionic_station_set(struct ionic_lif *lif)
2762 {
2763 struct net_device *netdev = lif->netdev;
2764 struct ionic_admin_ctx ctx = {
2765 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
2766 .cmd.lif_getattr = {
2767 .opcode = IONIC_CMD_LIF_GETATTR,
2768 .index = cpu_to_le16(lif->index),
2769 .attr = IONIC_LIF_ATTR_MAC,
2770 },
2771 };
2772 struct sockaddr addr;
2773 int err;
2774
2775 err = ionic_adminq_post_wait(lif, &ctx);
2776 if (err)
2777 return err;
2778 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n",
2779 ctx.comp.lif_getattr.mac);
2780 if (is_zero_ether_addr(ctx.comp.lif_getattr.mac))
2781 return 0;
2782
2783 if (!is_zero_ether_addr(netdev->dev_addr)) {
2784 /* If the netdev mac is non-zero and doesn't match the default
2785 * device address, it was set by something earlier and we're
2786 * likely here again after a fw-upgrade reset. We need to be
2787 * sure the netdev mac is in our filter list.
2788 */
2789 if (!ether_addr_equal(ctx.comp.lif_getattr.mac,
2790 netdev->dev_addr))
2791 ionic_lif_addr(lif, netdev->dev_addr, true, true);
2792 } else {
2793 /* Update the netdev mac with the device's mac */
2794 memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len);
2795 addr.sa_family = AF_INET;
2796 err = eth_prepare_mac_addr_change(netdev, &addr);
2797 if (err) {
2798 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n",
2799 addr.sa_data, err);
2800 return 0;
2801 }
2802
2803 eth_commit_mac_addr_change(netdev, &addr);
2804 }
2805
2806 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n",
2807 netdev->dev_addr);
2808 ionic_lif_addr(lif, netdev->dev_addr, true, true);
2809
2810 return 0;
2811 }
2812
ionic_lif_init(struct ionic_lif * lif)2813 int ionic_lif_init(struct ionic_lif *lif)
2814 {
2815 struct ionic_dev *idev = &lif->ionic->idev;
2816 struct device *dev = lif->ionic->dev;
2817 struct ionic_lif_init_comp comp;
2818 int dbpage_num;
2819 int err;
2820
2821 mutex_lock(&lif->ionic->dev_cmd_lock);
2822 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
2823 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT);
2824 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp);
2825 mutex_unlock(&lif->ionic->dev_cmd_lock);
2826 if (err)
2827 return err;
2828
2829 lif->hw_index = le16_to_cpu(comp.hw_index);
2830 mutex_init(&lif->queue_lock);
2831
2832 /* now that we have the hw_index we can figure out our doorbell page */
2833 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif);
2834 if (!lif->dbid_count) {
2835 dev_err(dev, "No doorbell pages, aborting\n");
2836 return -EINVAL;
2837 }
2838
2839 lif->dbid_inuse = bitmap_zalloc(lif->dbid_count, GFP_KERNEL);
2840 if (!lif->dbid_inuse) {
2841 dev_err(dev, "Failed alloc doorbell id bitmap, aborting\n");
2842 return -ENOMEM;
2843 }
2844
2845 /* first doorbell id reserved for kernel (dbid aka pid == zero) */
2846 set_bit(0, lif->dbid_inuse);
2847 lif->kern_pid = 0;
2848
2849 dbpage_num = ionic_db_page_num(lif, lif->kern_pid);
2850 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num);
2851 if (!lif->kern_dbpage) {
2852 dev_err(dev, "Cannot map dbpage, aborting\n");
2853 err = -ENOMEM;
2854 goto err_out_free_dbid;
2855 }
2856
2857 err = ionic_lif_adminq_init(lif);
2858 if (err)
2859 goto err_out_adminq_deinit;
2860
2861 if (lif->ionic->nnqs_per_lif) {
2862 err = ionic_lif_notifyq_init(lif);
2863 if (err)
2864 goto err_out_notifyq_deinit;
2865 }
2866
2867 err = ionic_init_nic_features(lif);
2868 if (err)
2869 goto err_out_notifyq_deinit;
2870
2871 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) {
2872 err = ionic_rx_filters_init(lif);
2873 if (err)
2874 goto err_out_notifyq_deinit;
2875 }
2876
2877 err = ionic_station_set(lif);
2878 if (err)
2879 goto err_out_notifyq_deinit;
2880
2881 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT;
2882
2883 set_bit(IONIC_LIF_F_INITED, lif->state);
2884
2885 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work);
2886
2887 return 0;
2888
2889 err_out_notifyq_deinit:
2890 ionic_lif_qcq_deinit(lif, lif->notifyqcq);
2891 err_out_adminq_deinit:
2892 ionic_lif_qcq_deinit(lif, lif->adminqcq);
2893 ionic_lif_reset(lif);
2894 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
2895 lif->kern_dbpage = NULL;
2896 err_out_free_dbid:
2897 kfree(lif->dbid_inuse);
2898 lif->dbid_inuse = NULL;
2899
2900 return err;
2901 }
2902
ionic_lif_notify_work(struct work_struct * ws)2903 static void ionic_lif_notify_work(struct work_struct *ws)
2904 {
2905 }
2906
ionic_lif_set_netdev_info(struct ionic_lif * lif)2907 static void ionic_lif_set_netdev_info(struct ionic_lif *lif)
2908 {
2909 struct ionic_admin_ctx ctx = {
2910 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
2911 .cmd.lif_setattr = {
2912 .opcode = IONIC_CMD_LIF_SETATTR,
2913 .index = cpu_to_le16(lif->index),
2914 .attr = IONIC_LIF_ATTR_NAME,
2915 },
2916 };
2917
2918 strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name,
2919 sizeof(ctx.cmd.lif_setattr.name));
2920
2921 ionic_adminq_post_wait(lif, &ctx);
2922 }
2923
ionic_netdev_lif(struct net_device * netdev)2924 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev)
2925 {
2926 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit)
2927 return NULL;
2928
2929 return netdev_priv(netdev);
2930 }
2931
ionic_lif_notify(struct notifier_block * nb,unsigned long event,void * info)2932 static int ionic_lif_notify(struct notifier_block *nb,
2933 unsigned long event, void *info)
2934 {
2935 struct net_device *ndev = netdev_notifier_info_to_dev(info);
2936 struct ionic *ionic = container_of(nb, struct ionic, nb);
2937 struct ionic_lif *lif = ionic_netdev_lif(ndev);
2938
2939 if (!lif || lif->ionic != ionic)
2940 return NOTIFY_DONE;
2941
2942 switch (event) {
2943 case NETDEV_CHANGENAME:
2944 ionic_lif_set_netdev_info(lif);
2945 break;
2946 }
2947
2948 return NOTIFY_DONE;
2949 }
2950
ionic_lif_register(struct ionic_lif * lif)2951 int ionic_lif_register(struct ionic_lif *lif)
2952 {
2953 int err;
2954
2955 INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work);
2956
2957 lif->ionic->nb.notifier_call = ionic_lif_notify;
2958
2959 err = register_netdevice_notifier(&lif->ionic->nb);
2960 if (err)
2961 lif->ionic->nb.notifier_call = NULL;
2962
2963 /* only register LIF0 for now */
2964 err = register_netdev(lif->netdev);
2965 if (err) {
2966 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n");
2967 return err;
2968 }
2969 lif->registered = true;
2970 ionic_lif_set_netdev_info(lif);
2971
2972 return 0;
2973 }
2974
ionic_lif_unregister(struct ionic_lif * lif)2975 void ionic_lif_unregister(struct ionic_lif *lif)
2976 {
2977 if (lif->ionic->nb.notifier_call) {
2978 unregister_netdevice_notifier(&lif->ionic->nb);
2979 cancel_work_sync(&lif->ionic->nb_work);
2980 lif->ionic->nb.notifier_call = NULL;
2981 }
2982
2983 if (lif->netdev->reg_state == NETREG_REGISTERED)
2984 unregister_netdev(lif->netdev);
2985 lif->registered = false;
2986 }
2987
ionic_lif_queue_identify(struct ionic_lif * lif)2988 static void ionic_lif_queue_identify(struct ionic_lif *lif)
2989 {
2990 union ionic_q_identity __iomem *q_ident;
2991 struct ionic *ionic = lif->ionic;
2992 struct ionic_dev *idev;
2993 int qtype;
2994 int err;
2995
2996 idev = &lif->ionic->idev;
2997 q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data;
2998
2999 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) {
3000 struct ionic_qtype_info *qti = &lif->qtype_info[qtype];
3001
3002 /* filter out the ones we know about */
3003 switch (qtype) {
3004 case IONIC_QTYPE_ADMINQ:
3005 case IONIC_QTYPE_NOTIFYQ:
3006 case IONIC_QTYPE_RXQ:
3007 case IONIC_QTYPE_TXQ:
3008 break;
3009 default:
3010 continue;
3011 }
3012
3013 memset(qti, 0, sizeof(*qti));
3014
3015 mutex_lock(&ionic->dev_cmd_lock);
3016 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype,
3017 ionic_qtype_versions[qtype]);
3018 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
3019 if (!err) {
3020 qti->version = readb(&q_ident->version);
3021 qti->supported = readb(&q_ident->supported);
3022 qti->features = readq(&q_ident->features);
3023 qti->desc_sz = readw(&q_ident->desc_sz);
3024 qti->comp_sz = readw(&q_ident->comp_sz);
3025 qti->sg_desc_sz = readw(&q_ident->sg_desc_sz);
3026 qti->max_sg_elems = readw(&q_ident->max_sg_elems);
3027 qti->sg_desc_stride = readw(&q_ident->sg_desc_stride);
3028 }
3029 mutex_unlock(&ionic->dev_cmd_lock);
3030
3031 if (err == -EINVAL) {
3032 dev_err(ionic->dev, "qtype %d not supported\n", qtype);
3033 continue;
3034 } else if (err == -EIO) {
3035 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n");
3036 return;
3037 } else if (err) {
3038 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n",
3039 qtype, err);
3040 return;
3041 }
3042
3043 dev_dbg(ionic->dev, " qtype[%d].version = %d\n",
3044 qtype, qti->version);
3045 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n",
3046 qtype, qti->supported);
3047 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n",
3048 qtype, qti->features);
3049 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n",
3050 qtype, qti->desc_sz);
3051 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n",
3052 qtype, qti->comp_sz);
3053 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n",
3054 qtype, qti->sg_desc_sz);
3055 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n",
3056 qtype, qti->max_sg_elems);
3057 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n",
3058 qtype, qti->sg_desc_stride);
3059 }
3060 }
3061
ionic_lif_identify(struct ionic * ionic,u8 lif_type,union ionic_lif_identity * lid)3062 int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
3063 union ionic_lif_identity *lid)
3064 {
3065 struct ionic_dev *idev = &ionic->idev;
3066 size_t sz;
3067 int err;
3068
3069 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data));
3070
3071 mutex_lock(&ionic->dev_cmd_lock);
3072 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1);
3073 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
3074 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz);
3075 mutex_unlock(&ionic->dev_cmd_lock);
3076 if (err)
3077 return (err);
3078
3079 dev_dbg(ionic->dev, "capabilities 0x%llx\n",
3080 le64_to_cpu(lid->capabilities));
3081
3082 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n",
3083 le32_to_cpu(lid->eth.max_ucast_filters));
3084 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n",
3085 le32_to_cpu(lid->eth.max_mcast_filters));
3086 dev_dbg(ionic->dev, "eth.features 0x%llx\n",
3087 le64_to_cpu(lid->eth.config.features));
3088 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n",
3089 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ]));
3090 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n",
3091 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]));
3092 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n",
3093 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ]));
3094 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n",
3095 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ]));
3096 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name);
3097 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac);
3098 dev_dbg(ionic->dev, "eth.config.mtu %d\n",
3099 le32_to_cpu(lid->eth.config.mtu));
3100
3101 return 0;
3102 }
3103
ionic_lif_size(struct ionic * ionic)3104 int ionic_lif_size(struct ionic *ionic)
3105 {
3106 struct ionic_identity *ident = &ionic->ident;
3107 unsigned int nintrs, dev_nintrs;
3108 union ionic_lif_config *lc;
3109 unsigned int ntxqs_per_lif;
3110 unsigned int nrxqs_per_lif;
3111 unsigned int neqs_per_lif;
3112 unsigned int nnqs_per_lif;
3113 unsigned int nxqs, neqs;
3114 unsigned int min_intrs;
3115 int err;
3116
3117 lc = &ident->lif.eth.config;
3118 dev_nintrs = le32_to_cpu(ident->dev.nintrs);
3119 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count);
3120 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]);
3121 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]);
3122 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]);
3123
3124 nxqs = min(ntxqs_per_lif, nrxqs_per_lif);
3125 nxqs = min(nxqs, num_online_cpus());
3126 neqs = min(neqs_per_lif, num_online_cpus());
3127
3128 try_again:
3129 /* interrupt usage:
3130 * 1 for master lif adminq/notifyq
3131 * 1 for each CPU for master lif TxRx queue pairs
3132 * whatever's left is for RDMA queues
3133 */
3134 nintrs = 1 + nxqs + neqs;
3135 min_intrs = 2; /* adminq + 1 TxRx queue pair */
3136
3137 if (nintrs > dev_nintrs)
3138 goto try_fewer;
3139
3140 err = ionic_bus_alloc_irq_vectors(ionic, nintrs);
3141 if (err < 0 && err != -ENOSPC) {
3142 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err);
3143 return err;
3144 }
3145 if (err == -ENOSPC)
3146 goto try_fewer;
3147
3148 if (err != nintrs) {
3149 ionic_bus_free_irq_vectors(ionic);
3150 goto try_fewer;
3151 }
3152
3153 ionic->nnqs_per_lif = nnqs_per_lif;
3154 ionic->neqs_per_lif = neqs;
3155 ionic->ntxqs_per_lif = nxqs;
3156 ionic->nrxqs_per_lif = nxqs;
3157 ionic->nintrs = nintrs;
3158
3159 ionic_debugfs_add_sizes(ionic);
3160
3161 return 0;
3162
3163 try_fewer:
3164 if (nnqs_per_lif > 1) {
3165 nnqs_per_lif >>= 1;
3166 goto try_again;
3167 }
3168 if (neqs > 1) {
3169 neqs >>= 1;
3170 goto try_again;
3171 }
3172 if (nxqs > 1) {
3173 nxqs >>= 1;
3174 goto try_again;
3175 }
3176 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs);
3177 return -ENOSPC;
3178 }
3179