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1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *
4  *   Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5  *   Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6  *   Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7  */
8 
9 #include <linux/of_device.h>
10 #include <linux/of_mdio.h>
11 #include <linux/of_net.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/regmap.h>
14 #include <linux/clk.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/if_vlan.h>
17 #include <linux/reset.h>
18 #include <linux/tcp.h>
19 #include <linux/interrupt.h>
20 #include <linux/pinctrl/devinfo.h>
21 #include <linux/phylink.h>
22 
23 #include "mtk_eth_soc.h"
24 
25 static int mtk_msg_level = -1;
26 module_param_named(msg_level, mtk_msg_level, int, 0);
27 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
28 
29 #define MTK_ETHTOOL_STAT(x) { #x, \
30 			      offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
31 
32 /* strings used by ethtool */
33 static const struct mtk_ethtool_stats {
34 	char str[ETH_GSTRING_LEN];
35 	u32 offset;
36 } mtk_ethtool_stats[] = {
37 	MTK_ETHTOOL_STAT(tx_bytes),
38 	MTK_ETHTOOL_STAT(tx_packets),
39 	MTK_ETHTOOL_STAT(tx_skip),
40 	MTK_ETHTOOL_STAT(tx_collisions),
41 	MTK_ETHTOOL_STAT(rx_bytes),
42 	MTK_ETHTOOL_STAT(rx_packets),
43 	MTK_ETHTOOL_STAT(rx_overflow),
44 	MTK_ETHTOOL_STAT(rx_fcs_errors),
45 	MTK_ETHTOOL_STAT(rx_short_errors),
46 	MTK_ETHTOOL_STAT(rx_long_errors),
47 	MTK_ETHTOOL_STAT(rx_checksum_errors),
48 	MTK_ETHTOOL_STAT(rx_flow_control_packets),
49 };
50 
51 static const char * const mtk_clks_source_name[] = {
52 	"ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
53 	"sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
54 	"sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
55 	"sgmii_ck", "eth2pll",
56 };
57 
mtk_w32(struct mtk_eth * eth,u32 val,unsigned reg)58 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
59 {
60 	__raw_writel(val, eth->base + reg);
61 }
62 
mtk_r32(struct mtk_eth * eth,unsigned reg)63 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
64 {
65 	return __raw_readl(eth->base + reg);
66 }
67 
mtk_m32(struct mtk_eth * eth,u32 mask,u32 set,unsigned reg)68 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg)
69 {
70 	u32 val;
71 
72 	val = mtk_r32(eth, reg);
73 	val &= ~mask;
74 	val |= set;
75 	mtk_w32(eth, val, reg);
76 	return reg;
77 }
78 
mtk_mdio_busy_wait(struct mtk_eth * eth)79 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
80 {
81 	unsigned long t_start = jiffies;
82 
83 	while (1) {
84 		if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
85 			return 0;
86 		if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
87 			break;
88 		usleep_range(10, 20);
89 	}
90 
91 	dev_err(eth->dev, "mdio: MDIO timeout\n");
92 	return -1;
93 }
94 
_mtk_mdio_write(struct mtk_eth * eth,u32 phy_addr,u32 phy_register,u32 write_data)95 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
96 			   u32 phy_register, u32 write_data)
97 {
98 	if (mtk_mdio_busy_wait(eth))
99 		return -1;
100 
101 	write_data &= 0xffff;
102 
103 	mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
104 		(phy_register << PHY_IAC_REG_SHIFT) |
105 		(phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
106 		MTK_PHY_IAC);
107 
108 	if (mtk_mdio_busy_wait(eth))
109 		return -1;
110 
111 	return 0;
112 }
113 
_mtk_mdio_read(struct mtk_eth * eth,int phy_addr,int phy_reg)114 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
115 {
116 	u32 d;
117 
118 	if (mtk_mdio_busy_wait(eth))
119 		return 0xffff;
120 
121 	mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
122 		(phy_reg << PHY_IAC_REG_SHIFT) |
123 		(phy_addr << PHY_IAC_ADDR_SHIFT),
124 		MTK_PHY_IAC);
125 
126 	if (mtk_mdio_busy_wait(eth))
127 		return 0xffff;
128 
129 	d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
130 
131 	return d;
132 }
133 
mtk_mdio_write(struct mii_bus * bus,int phy_addr,int phy_reg,u16 val)134 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
135 			  int phy_reg, u16 val)
136 {
137 	struct mtk_eth *eth = bus->priv;
138 
139 	return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
140 }
141 
mtk_mdio_read(struct mii_bus * bus,int phy_addr,int phy_reg)142 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
143 {
144 	struct mtk_eth *eth = bus->priv;
145 
146 	return _mtk_mdio_read(eth, phy_addr, phy_reg);
147 }
148 
mt7621_gmac0_rgmii_adjust(struct mtk_eth * eth,phy_interface_t interface)149 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
150 				     phy_interface_t interface)
151 {
152 	u32 val;
153 
154 	/* Check DDR memory type.
155 	 * Currently TRGMII mode with DDR2 memory is not supported.
156 	 */
157 	regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val);
158 	if (interface == PHY_INTERFACE_MODE_TRGMII &&
159 	    val & SYSCFG_DRAM_TYPE_DDR2) {
160 		dev_err(eth->dev,
161 			"TRGMII mode with DDR2 memory is not supported!\n");
162 		return -EOPNOTSUPP;
163 	}
164 
165 	val = (interface == PHY_INTERFACE_MODE_TRGMII) ?
166 		ETHSYS_TRGMII_MT7621_DDR_PLL : 0;
167 
168 	regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
169 			   ETHSYS_TRGMII_MT7621_MASK, val);
170 
171 	return 0;
172 }
173 
mtk_gmac0_rgmii_adjust(struct mtk_eth * eth,phy_interface_t interface,int speed)174 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
175 				   phy_interface_t interface, int speed)
176 {
177 	u32 val;
178 	int ret;
179 
180 	if (interface == PHY_INTERFACE_MODE_TRGMII) {
181 		mtk_w32(eth, TRGMII_MODE, INTF_MODE);
182 		val = 500000000;
183 		ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
184 		if (ret)
185 			dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
186 		return;
187 	}
188 
189 	val = (speed == SPEED_1000) ?
190 		INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
191 	mtk_w32(eth, val, INTF_MODE);
192 
193 	regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
194 			   ETHSYS_TRGMII_CLK_SEL362_5,
195 			   ETHSYS_TRGMII_CLK_SEL362_5);
196 
197 	val = (speed == SPEED_1000) ? 250000000 : 500000000;
198 	ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
199 	if (ret)
200 		dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
201 
202 	val = (speed == SPEED_1000) ?
203 		RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
204 	mtk_w32(eth, val, TRGMII_RCK_CTRL);
205 
206 	val = (speed == SPEED_1000) ?
207 		TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
208 	mtk_w32(eth, val, TRGMII_TCK_CTRL);
209 }
210 
mtk_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)211 static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
212 			   const struct phylink_link_state *state)
213 {
214 	struct mtk_mac *mac = container_of(config, struct mtk_mac,
215 					   phylink_config);
216 	struct mtk_eth *eth = mac->hw;
217 	u32 mcr_cur, mcr_new, sid, i;
218 	int val, ge_mode, err = 0;
219 
220 	/* MT76x8 has no hardware settings between for the MAC */
221 	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
222 	    mac->interface != state->interface) {
223 		/* Setup soc pin functions */
224 		switch (state->interface) {
225 		case PHY_INTERFACE_MODE_TRGMII:
226 			if (mac->id)
227 				goto err_phy;
228 			if (!MTK_HAS_CAPS(mac->hw->soc->caps,
229 					  MTK_GMAC1_TRGMII))
230 				goto err_phy;
231 			fallthrough;
232 		case PHY_INTERFACE_MODE_RGMII_TXID:
233 		case PHY_INTERFACE_MODE_RGMII_RXID:
234 		case PHY_INTERFACE_MODE_RGMII_ID:
235 		case PHY_INTERFACE_MODE_RGMII:
236 		case PHY_INTERFACE_MODE_MII:
237 		case PHY_INTERFACE_MODE_REVMII:
238 		case PHY_INTERFACE_MODE_RMII:
239 			if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {
240 				err = mtk_gmac_rgmii_path_setup(eth, mac->id);
241 				if (err)
242 					goto init_err;
243 			}
244 			break;
245 		case PHY_INTERFACE_MODE_1000BASEX:
246 		case PHY_INTERFACE_MODE_2500BASEX:
247 		case PHY_INTERFACE_MODE_SGMII:
248 			if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
249 				err = mtk_gmac_sgmii_path_setup(eth, mac->id);
250 				if (err)
251 					goto init_err;
252 			}
253 			break;
254 		case PHY_INTERFACE_MODE_GMII:
255 			if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {
256 				err = mtk_gmac_gephy_path_setup(eth, mac->id);
257 				if (err)
258 					goto init_err;
259 			}
260 			break;
261 		default:
262 			goto err_phy;
263 		}
264 
265 		/* Setup clock for 1st gmac */
266 		if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII &&
267 		    !phy_interface_mode_is_8023z(state->interface) &&
268 		    MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) {
269 			if (MTK_HAS_CAPS(mac->hw->soc->caps,
270 					 MTK_TRGMII_MT7621_CLK)) {
271 				if (mt7621_gmac0_rgmii_adjust(mac->hw,
272 							      state->interface))
273 					goto err_phy;
274 			} else {
275 				mtk_gmac0_rgmii_adjust(mac->hw,
276 						       state->interface,
277 						       state->speed);
278 
279 				/* mt7623_pad_clk_setup */
280 				for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
281 					mtk_w32(mac->hw,
282 						TD_DM_DRVP(8) | TD_DM_DRVN(8),
283 						TRGMII_TD_ODT(i));
284 
285 				/* Assert/release MT7623 RXC reset */
286 				mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL,
287 					TRGMII_RCK_CTRL);
288 				mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL);
289 			}
290 		}
291 
292 		ge_mode = 0;
293 		switch (state->interface) {
294 		case PHY_INTERFACE_MODE_MII:
295 		case PHY_INTERFACE_MODE_GMII:
296 			ge_mode = 1;
297 			break;
298 		case PHY_INTERFACE_MODE_REVMII:
299 			ge_mode = 2;
300 			break;
301 		case PHY_INTERFACE_MODE_RMII:
302 			if (mac->id)
303 				goto err_phy;
304 			ge_mode = 3;
305 			break;
306 		default:
307 			break;
308 		}
309 
310 		/* put the gmac into the right mode */
311 		regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
312 		val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
313 		val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
314 		regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
315 
316 		mac->interface = state->interface;
317 	}
318 
319 	/* SGMII */
320 	if (state->interface == PHY_INTERFACE_MODE_SGMII ||
321 	    phy_interface_mode_is_8023z(state->interface)) {
322 		/* The path GMAC to SGMII will be enabled once the SGMIISYS is
323 		 * being setup done.
324 		 */
325 		regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
326 
327 		regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
328 				   SYSCFG0_SGMII_MASK,
329 				   ~(u32)SYSCFG0_SGMII_MASK);
330 
331 		/* Decide how GMAC and SGMIISYS be mapped */
332 		sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
333 		       0 : mac->id;
334 
335 		/* Setup SGMIISYS with the determined property */
336 		if (state->interface != PHY_INTERFACE_MODE_SGMII)
337 			err = mtk_sgmii_setup_mode_force(eth->sgmii, sid,
338 							 state);
339 		else if (phylink_autoneg_inband(mode))
340 			err = mtk_sgmii_setup_mode_an(eth->sgmii, sid);
341 
342 		if (err)
343 			goto init_err;
344 
345 		regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
346 				   SYSCFG0_SGMII_MASK, val);
347 	} else if (phylink_autoneg_inband(mode)) {
348 		dev_err(eth->dev,
349 			"In-band mode not supported in non SGMII mode!\n");
350 		return;
351 	}
352 
353 	/* Setup gmac */
354 	mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
355 	mcr_new = mcr_cur;
356 	mcr_new |= MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |
357 		   MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK;
358 
359 	/* Only update control register when needed! */
360 	if (mcr_new != mcr_cur)
361 		mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
362 
363 	return;
364 
365 err_phy:
366 	dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__,
367 		mac->id, phy_modes(state->interface));
368 	return;
369 
370 init_err:
371 	dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__,
372 		mac->id, phy_modes(state->interface), err);
373 }
374 
mtk_mac_pcs_get_state(struct phylink_config * config,struct phylink_link_state * state)375 static void mtk_mac_pcs_get_state(struct phylink_config *config,
376 				  struct phylink_link_state *state)
377 {
378 	struct mtk_mac *mac = container_of(config, struct mtk_mac,
379 					   phylink_config);
380 	u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id));
381 
382 	state->link = (pmsr & MAC_MSR_LINK);
383 	state->duplex = (pmsr & MAC_MSR_DPX) >> 1;
384 
385 	switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) {
386 	case 0:
387 		state->speed = SPEED_10;
388 		break;
389 	case MAC_MSR_SPEED_100:
390 		state->speed = SPEED_100;
391 		break;
392 	case MAC_MSR_SPEED_1000:
393 		state->speed = SPEED_1000;
394 		break;
395 	default:
396 		state->speed = SPEED_UNKNOWN;
397 		break;
398 	}
399 
400 	state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
401 	if (pmsr & MAC_MSR_RX_FC)
402 		state->pause |= MLO_PAUSE_RX;
403 	if (pmsr & MAC_MSR_TX_FC)
404 		state->pause |= MLO_PAUSE_TX;
405 }
406 
mtk_mac_an_restart(struct phylink_config * config)407 static void mtk_mac_an_restart(struct phylink_config *config)
408 {
409 	struct mtk_mac *mac = container_of(config, struct mtk_mac,
410 					   phylink_config);
411 
412 	mtk_sgmii_restart_an(mac->hw, mac->id);
413 }
414 
mtk_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)415 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
416 			      phy_interface_t interface)
417 {
418 	struct mtk_mac *mac = container_of(config, struct mtk_mac,
419 					   phylink_config);
420 	u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
421 
422 	mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
423 	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
424 }
425 
mtk_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)426 static void mtk_mac_link_up(struct phylink_config *config,
427 			    struct phy_device *phy,
428 			    unsigned int mode, phy_interface_t interface,
429 			    int speed, int duplex, bool tx_pause, bool rx_pause)
430 {
431 	struct mtk_mac *mac = container_of(config, struct mtk_mac,
432 					   phylink_config);
433 	u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
434 
435 	mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 |
436 		 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC |
437 		 MAC_MCR_FORCE_RX_FC);
438 
439 	/* Configure speed */
440 	switch (speed) {
441 	case SPEED_2500:
442 	case SPEED_1000:
443 		mcr |= MAC_MCR_SPEED_1000;
444 		break;
445 	case SPEED_100:
446 		mcr |= MAC_MCR_SPEED_100;
447 		break;
448 	}
449 
450 	/* Configure duplex */
451 	if (duplex == DUPLEX_FULL)
452 		mcr |= MAC_MCR_FORCE_DPX;
453 
454 	/* Configure pause modes - phylink will avoid these for half duplex */
455 	if (tx_pause)
456 		mcr |= MAC_MCR_FORCE_TX_FC;
457 	if (rx_pause)
458 		mcr |= MAC_MCR_FORCE_RX_FC;
459 
460 	mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN;
461 	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
462 }
463 
mtk_validate(struct phylink_config * config,unsigned long * supported,struct phylink_link_state * state)464 static void mtk_validate(struct phylink_config *config,
465 			 unsigned long *supported,
466 			 struct phylink_link_state *state)
467 {
468 	struct mtk_mac *mac = container_of(config, struct mtk_mac,
469 					   phylink_config);
470 	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
471 
472 	if (state->interface != PHY_INTERFACE_MODE_NA &&
473 	    state->interface != PHY_INTERFACE_MODE_MII &&
474 	    state->interface != PHY_INTERFACE_MODE_GMII &&
475 	    !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) &&
476 	      phy_interface_mode_is_rgmii(state->interface)) &&
477 	    !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) &&
478 	      !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII) &&
479 	    !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII) &&
480 	      (state->interface == PHY_INTERFACE_MODE_SGMII ||
481 	       phy_interface_mode_is_8023z(state->interface)))) {
482 		linkmode_zero(supported);
483 		return;
484 	}
485 
486 	phylink_set_port_modes(mask);
487 	phylink_set(mask, Autoneg);
488 
489 	switch (state->interface) {
490 	case PHY_INTERFACE_MODE_TRGMII:
491 		phylink_set(mask, 1000baseT_Full);
492 		break;
493 	case PHY_INTERFACE_MODE_1000BASEX:
494 	case PHY_INTERFACE_MODE_2500BASEX:
495 		phylink_set(mask, 1000baseX_Full);
496 		phylink_set(mask, 2500baseX_Full);
497 		break;
498 	case PHY_INTERFACE_MODE_GMII:
499 	case PHY_INTERFACE_MODE_RGMII:
500 	case PHY_INTERFACE_MODE_RGMII_ID:
501 	case PHY_INTERFACE_MODE_RGMII_RXID:
502 	case PHY_INTERFACE_MODE_RGMII_TXID:
503 		phylink_set(mask, 1000baseT_Half);
504 		fallthrough;
505 	case PHY_INTERFACE_MODE_SGMII:
506 		phylink_set(mask, 1000baseT_Full);
507 		phylink_set(mask, 1000baseX_Full);
508 		fallthrough;
509 	case PHY_INTERFACE_MODE_MII:
510 	case PHY_INTERFACE_MODE_RMII:
511 	case PHY_INTERFACE_MODE_REVMII:
512 	case PHY_INTERFACE_MODE_NA:
513 	default:
514 		phylink_set(mask, 10baseT_Half);
515 		phylink_set(mask, 10baseT_Full);
516 		phylink_set(mask, 100baseT_Half);
517 		phylink_set(mask, 100baseT_Full);
518 		break;
519 	}
520 
521 	if (state->interface == PHY_INTERFACE_MODE_NA) {
522 		if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
523 			phylink_set(mask, 1000baseT_Full);
524 			phylink_set(mask, 1000baseX_Full);
525 			phylink_set(mask, 2500baseX_Full);
526 		}
527 		if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) {
528 			phylink_set(mask, 1000baseT_Full);
529 			phylink_set(mask, 1000baseT_Half);
530 			phylink_set(mask, 1000baseX_Full);
531 		}
532 		if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GEPHY)) {
533 			phylink_set(mask, 1000baseT_Full);
534 			phylink_set(mask, 1000baseT_Half);
535 		}
536 	}
537 
538 	phylink_set(mask, Pause);
539 	phylink_set(mask, Asym_Pause);
540 
541 	linkmode_and(supported, supported, mask);
542 	linkmode_and(state->advertising, state->advertising, mask);
543 
544 	/* We can only operate at 2500BaseX or 1000BaseX. If requested
545 	 * to advertise both, only report advertising at 2500BaseX.
546 	 */
547 	phylink_helper_basex_speed(state);
548 }
549 
550 static const struct phylink_mac_ops mtk_phylink_ops = {
551 	.validate = mtk_validate,
552 	.mac_pcs_get_state = mtk_mac_pcs_get_state,
553 	.mac_an_restart = mtk_mac_an_restart,
554 	.mac_config = mtk_mac_config,
555 	.mac_link_down = mtk_mac_link_down,
556 	.mac_link_up = mtk_mac_link_up,
557 };
558 
mtk_mdio_init(struct mtk_eth * eth)559 static int mtk_mdio_init(struct mtk_eth *eth)
560 {
561 	struct device_node *mii_np;
562 	int ret;
563 
564 	mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
565 	if (!mii_np) {
566 		dev_err(eth->dev, "no %s child node found", "mdio-bus");
567 		return -ENODEV;
568 	}
569 
570 	if (!of_device_is_available(mii_np)) {
571 		ret = -ENODEV;
572 		goto err_put_node;
573 	}
574 
575 	eth->mii_bus = devm_mdiobus_alloc(eth->dev);
576 	if (!eth->mii_bus) {
577 		ret = -ENOMEM;
578 		goto err_put_node;
579 	}
580 
581 	eth->mii_bus->name = "mdio";
582 	eth->mii_bus->read = mtk_mdio_read;
583 	eth->mii_bus->write = mtk_mdio_write;
584 	eth->mii_bus->priv = eth;
585 	eth->mii_bus->parent = eth->dev;
586 
587 	snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
588 	ret = of_mdiobus_register(eth->mii_bus, mii_np);
589 
590 err_put_node:
591 	of_node_put(mii_np);
592 	return ret;
593 }
594 
mtk_mdio_cleanup(struct mtk_eth * eth)595 static void mtk_mdio_cleanup(struct mtk_eth *eth)
596 {
597 	if (!eth->mii_bus)
598 		return;
599 
600 	mdiobus_unregister(eth->mii_bus);
601 }
602 
mtk_tx_irq_disable(struct mtk_eth * eth,u32 mask)603 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
604 {
605 	unsigned long flags;
606 	u32 val;
607 
608 	spin_lock_irqsave(&eth->tx_irq_lock, flags);
609 	val = mtk_r32(eth, eth->tx_int_mask_reg);
610 	mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg);
611 	spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
612 }
613 
mtk_tx_irq_enable(struct mtk_eth * eth,u32 mask)614 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
615 {
616 	unsigned long flags;
617 	u32 val;
618 
619 	spin_lock_irqsave(&eth->tx_irq_lock, flags);
620 	val = mtk_r32(eth, eth->tx_int_mask_reg);
621 	mtk_w32(eth, val | mask, eth->tx_int_mask_reg);
622 	spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
623 }
624 
mtk_rx_irq_disable(struct mtk_eth * eth,u32 mask)625 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
626 {
627 	unsigned long flags;
628 	u32 val;
629 
630 	spin_lock_irqsave(&eth->rx_irq_lock, flags);
631 	val = mtk_r32(eth, MTK_PDMA_INT_MASK);
632 	mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK);
633 	spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
634 }
635 
mtk_rx_irq_enable(struct mtk_eth * eth,u32 mask)636 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
637 {
638 	unsigned long flags;
639 	u32 val;
640 
641 	spin_lock_irqsave(&eth->rx_irq_lock, flags);
642 	val = mtk_r32(eth, MTK_PDMA_INT_MASK);
643 	mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK);
644 	spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
645 }
646 
mtk_set_mac_address(struct net_device * dev,void * p)647 static int mtk_set_mac_address(struct net_device *dev, void *p)
648 {
649 	int ret = eth_mac_addr(dev, p);
650 	struct mtk_mac *mac = netdev_priv(dev);
651 	struct mtk_eth *eth = mac->hw;
652 	const char *macaddr = dev->dev_addr;
653 
654 	if (ret)
655 		return ret;
656 
657 	if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
658 		return -EBUSY;
659 
660 	spin_lock_bh(&mac->hw->page_lock);
661 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
662 		mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
663 			MT7628_SDM_MAC_ADRH);
664 		mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
665 			(macaddr[4] << 8) | macaddr[5],
666 			MT7628_SDM_MAC_ADRL);
667 	} else {
668 		mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
669 			MTK_GDMA_MAC_ADRH(mac->id));
670 		mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
671 			(macaddr[4] << 8) | macaddr[5],
672 			MTK_GDMA_MAC_ADRL(mac->id));
673 	}
674 	spin_unlock_bh(&mac->hw->page_lock);
675 
676 	return 0;
677 }
678 
mtk_stats_update_mac(struct mtk_mac * mac)679 void mtk_stats_update_mac(struct mtk_mac *mac)
680 {
681 	struct mtk_hw_stats *hw_stats = mac->hw_stats;
682 	struct mtk_eth *eth = mac->hw;
683 
684 	u64_stats_update_begin(&hw_stats->syncp);
685 
686 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
687 		hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT);
688 		hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT);
689 		hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT);
690 		hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT);
691 		hw_stats->rx_checksum_errors +=
692 			mtk_r32(mac->hw, MT7628_SDM_CS_ERR);
693 	} else {
694 		unsigned int offs = hw_stats->reg_offset;
695 		u64 stats;
696 
697 		hw_stats->rx_bytes += mtk_r32(mac->hw,
698 					      MTK_GDM1_RX_GBCNT_L + offs);
699 		stats = mtk_r32(mac->hw, MTK_GDM1_RX_GBCNT_H + offs);
700 		if (stats)
701 			hw_stats->rx_bytes += (stats << 32);
702 		hw_stats->rx_packets +=
703 			mtk_r32(mac->hw, MTK_GDM1_RX_GPCNT + offs);
704 		hw_stats->rx_overflow +=
705 			mtk_r32(mac->hw, MTK_GDM1_RX_OERCNT + offs);
706 		hw_stats->rx_fcs_errors +=
707 			mtk_r32(mac->hw, MTK_GDM1_RX_FERCNT + offs);
708 		hw_stats->rx_short_errors +=
709 			mtk_r32(mac->hw, MTK_GDM1_RX_SERCNT + offs);
710 		hw_stats->rx_long_errors +=
711 			mtk_r32(mac->hw, MTK_GDM1_RX_LENCNT + offs);
712 		hw_stats->rx_checksum_errors +=
713 			mtk_r32(mac->hw, MTK_GDM1_RX_CERCNT + offs);
714 		hw_stats->rx_flow_control_packets +=
715 			mtk_r32(mac->hw, MTK_GDM1_RX_FCCNT + offs);
716 		hw_stats->tx_skip +=
717 			mtk_r32(mac->hw, MTK_GDM1_TX_SKIPCNT + offs);
718 		hw_stats->tx_collisions +=
719 			mtk_r32(mac->hw, MTK_GDM1_TX_COLCNT + offs);
720 		hw_stats->tx_bytes +=
721 			mtk_r32(mac->hw, MTK_GDM1_TX_GBCNT_L + offs);
722 		stats =  mtk_r32(mac->hw, MTK_GDM1_TX_GBCNT_H + offs);
723 		if (stats)
724 			hw_stats->tx_bytes += (stats << 32);
725 		hw_stats->tx_packets +=
726 			mtk_r32(mac->hw, MTK_GDM1_TX_GPCNT + offs);
727 	}
728 
729 	u64_stats_update_end(&hw_stats->syncp);
730 }
731 
mtk_stats_update(struct mtk_eth * eth)732 static void mtk_stats_update(struct mtk_eth *eth)
733 {
734 	int i;
735 
736 	for (i = 0; i < MTK_MAC_COUNT; i++) {
737 		if (!eth->mac[i] || !eth->mac[i]->hw_stats)
738 			continue;
739 		if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
740 			mtk_stats_update_mac(eth->mac[i]);
741 			spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
742 		}
743 	}
744 }
745 
mtk_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * storage)746 static void mtk_get_stats64(struct net_device *dev,
747 			    struct rtnl_link_stats64 *storage)
748 {
749 	struct mtk_mac *mac = netdev_priv(dev);
750 	struct mtk_hw_stats *hw_stats = mac->hw_stats;
751 	unsigned int start;
752 
753 	if (netif_running(dev) && netif_device_present(dev)) {
754 		if (spin_trylock_bh(&hw_stats->stats_lock)) {
755 			mtk_stats_update_mac(mac);
756 			spin_unlock_bh(&hw_stats->stats_lock);
757 		}
758 	}
759 
760 	do {
761 		start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
762 		storage->rx_packets = hw_stats->rx_packets;
763 		storage->tx_packets = hw_stats->tx_packets;
764 		storage->rx_bytes = hw_stats->rx_bytes;
765 		storage->tx_bytes = hw_stats->tx_bytes;
766 		storage->collisions = hw_stats->tx_collisions;
767 		storage->rx_length_errors = hw_stats->rx_short_errors +
768 			hw_stats->rx_long_errors;
769 		storage->rx_over_errors = hw_stats->rx_overflow;
770 		storage->rx_crc_errors = hw_stats->rx_fcs_errors;
771 		storage->rx_errors = hw_stats->rx_checksum_errors;
772 		storage->tx_aborted_errors = hw_stats->tx_skip;
773 	} while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
774 
775 	storage->tx_errors = dev->stats.tx_errors;
776 	storage->rx_dropped = dev->stats.rx_dropped;
777 	storage->tx_dropped = dev->stats.tx_dropped;
778 }
779 
mtk_max_frag_size(int mtu)780 static inline int mtk_max_frag_size(int mtu)
781 {
782 	/* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
783 	if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
784 		mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
785 
786 	return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
787 		SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
788 }
789 
mtk_max_buf_size(int frag_size)790 static inline int mtk_max_buf_size(int frag_size)
791 {
792 	int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
793 		       SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
794 
795 	WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
796 
797 	return buf_size;
798 }
799 
mtk_rx_get_desc(struct mtk_rx_dma * rxd,struct mtk_rx_dma * dma_rxd)800 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
801 				   struct mtk_rx_dma *dma_rxd)
802 {
803 	rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
804 	rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
805 	rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
806 	rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
807 }
808 
809 /* the qdma core needs scratch memory to be setup */
mtk_init_fq_dma(struct mtk_eth * eth)810 static int mtk_init_fq_dma(struct mtk_eth *eth)
811 {
812 	dma_addr_t phy_ring_tail;
813 	int cnt = MTK_DMA_SIZE;
814 	dma_addr_t dma_addr;
815 	int i;
816 
817 	eth->scratch_ring = dma_alloc_coherent(eth->dev,
818 					       cnt * sizeof(struct mtk_tx_dma),
819 					       &eth->phy_scratch_ring,
820 					       GFP_ATOMIC);
821 	if (unlikely(!eth->scratch_ring))
822 		return -ENOMEM;
823 
824 	eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
825 				    GFP_KERNEL);
826 	if (unlikely(!eth->scratch_head))
827 		return -ENOMEM;
828 
829 	dma_addr = dma_map_single(eth->dev,
830 				  eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
831 				  DMA_FROM_DEVICE);
832 	if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
833 		return -ENOMEM;
834 
835 	phy_ring_tail = eth->phy_scratch_ring +
836 			(sizeof(struct mtk_tx_dma) * (cnt - 1));
837 
838 	for (i = 0; i < cnt; i++) {
839 		eth->scratch_ring[i].txd1 =
840 					(dma_addr + (i * MTK_QDMA_PAGE_SIZE));
841 		if (i < cnt - 1)
842 			eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
843 				((i + 1) * sizeof(struct mtk_tx_dma)));
844 		eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
845 	}
846 
847 	mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
848 	mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
849 	mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
850 	mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
851 
852 	return 0;
853 }
854 
mtk_qdma_phys_to_virt(struct mtk_tx_ring * ring,u32 desc)855 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
856 {
857 	void *ret = ring->dma;
858 
859 	return ret + (desc - ring->phys);
860 }
861 
mtk_desc_to_tx_buf(struct mtk_tx_ring * ring,struct mtk_tx_dma * txd)862 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
863 						    struct mtk_tx_dma *txd)
864 {
865 	int idx = txd - ring->dma;
866 
867 	return &ring->buf[idx];
868 }
869 
qdma_to_pdma(struct mtk_tx_ring * ring,struct mtk_tx_dma * dma)870 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring,
871 				       struct mtk_tx_dma *dma)
872 {
873 	return ring->dma_pdma - ring->dma + dma;
874 }
875 
txd_to_idx(struct mtk_tx_ring * ring,struct mtk_tx_dma * dma)876 static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma)
877 {
878 	return ((void *)dma - (void *)ring->dma) / sizeof(*dma);
879 }
880 
mtk_tx_unmap(struct mtk_eth * eth,struct mtk_tx_buf * tx_buf)881 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
882 {
883 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
884 		if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
885 			dma_unmap_single(eth->dev,
886 					 dma_unmap_addr(tx_buf, dma_addr0),
887 					 dma_unmap_len(tx_buf, dma_len0),
888 					 DMA_TO_DEVICE);
889 		} else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
890 			dma_unmap_page(eth->dev,
891 				       dma_unmap_addr(tx_buf, dma_addr0),
892 				       dma_unmap_len(tx_buf, dma_len0),
893 				       DMA_TO_DEVICE);
894 		}
895 	} else {
896 		if (dma_unmap_len(tx_buf, dma_len0)) {
897 			dma_unmap_page(eth->dev,
898 				       dma_unmap_addr(tx_buf, dma_addr0),
899 				       dma_unmap_len(tx_buf, dma_len0),
900 				       DMA_TO_DEVICE);
901 		}
902 
903 		if (dma_unmap_len(tx_buf, dma_len1)) {
904 			dma_unmap_page(eth->dev,
905 				       dma_unmap_addr(tx_buf, dma_addr1),
906 				       dma_unmap_len(tx_buf, dma_len1),
907 				       DMA_TO_DEVICE);
908 		}
909 	}
910 
911 	tx_buf->flags = 0;
912 	if (tx_buf->skb &&
913 	    (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
914 		dev_kfree_skb_any(tx_buf->skb);
915 	tx_buf->skb = NULL;
916 }
917 
setup_tx_buf(struct mtk_eth * eth,struct mtk_tx_buf * tx_buf,struct mtk_tx_dma * txd,dma_addr_t mapped_addr,size_t size,int idx)918 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,
919 			 struct mtk_tx_dma *txd, dma_addr_t mapped_addr,
920 			 size_t size, int idx)
921 {
922 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
923 		dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
924 		dma_unmap_len_set(tx_buf, dma_len0, size);
925 	} else {
926 		if (idx & 1) {
927 			txd->txd3 = mapped_addr;
928 			txd->txd2 |= TX_DMA_PLEN1(size);
929 			dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
930 			dma_unmap_len_set(tx_buf, dma_len1, size);
931 		} else {
932 			tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
933 			txd->txd1 = mapped_addr;
934 			txd->txd2 = TX_DMA_PLEN0(size);
935 			dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
936 			dma_unmap_len_set(tx_buf, dma_len0, size);
937 		}
938 	}
939 }
940 
mtk_tx_map(struct sk_buff * skb,struct net_device * dev,int tx_num,struct mtk_tx_ring * ring,bool gso)941 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
942 		      int tx_num, struct mtk_tx_ring *ring, bool gso)
943 {
944 	struct mtk_mac *mac = netdev_priv(dev);
945 	struct mtk_eth *eth = mac->hw;
946 	struct mtk_tx_dma *itxd, *txd;
947 	struct mtk_tx_dma *itxd_pdma, *txd_pdma;
948 	struct mtk_tx_buf *itx_buf, *tx_buf;
949 	dma_addr_t mapped_addr;
950 	unsigned int nr_frags;
951 	int i, n_desc = 1;
952 	u32 txd4 = 0, fport;
953 	int k = 0;
954 
955 	itxd = ring->next_free;
956 	itxd_pdma = qdma_to_pdma(ring, itxd);
957 	if (itxd == ring->last_free)
958 		return -ENOMEM;
959 
960 	/* set the forward port */
961 	fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
962 	txd4 |= fport;
963 
964 	itx_buf = mtk_desc_to_tx_buf(ring, itxd);
965 	memset(itx_buf, 0, sizeof(*itx_buf));
966 
967 	if (gso)
968 		txd4 |= TX_DMA_TSO;
969 
970 	/* TX Checksum offload */
971 	if (skb->ip_summed == CHECKSUM_PARTIAL)
972 		txd4 |= TX_DMA_CHKSUM;
973 
974 	/* VLAN header offload */
975 	if (skb_vlan_tag_present(skb))
976 		txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
977 
978 	mapped_addr = dma_map_single(eth->dev, skb->data,
979 				     skb_headlen(skb), DMA_TO_DEVICE);
980 	if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
981 		return -ENOMEM;
982 
983 	WRITE_ONCE(itxd->txd1, mapped_addr);
984 	itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
985 	itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
986 			  MTK_TX_FLAGS_FPORT1;
987 	setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb),
988 		     k++);
989 
990 	/* TX SG offload */
991 	txd = itxd;
992 	txd_pdma = qdma_to_pdma(ring, txd);
993 	nr_frags = skb_shinfo(skb)->nr_frags;
994 
995 	for (i = 0; i < nr_frags; i++) {
996 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
997 		unsigned int offset = 0;
998 		int frag_size = skb_frag_size(frag);
999 
1000 		while (frag_size) {
1001 			bool last_frag = false;
1002 			unsigned int frag_map_size;
1003 			bool new_desc = true;
1004 
1005 			if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) ||
1006 			    (i & 0x1)) {
1007 				txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
1008 				txd_pdma = qdma_to_pdma(ring, txd);
1009 				if (txd == ring->last_free)
1010 					goto err_dma;
1011 
1012 				n_desc++;
1013 			} else {
1014 				new_desc = false;
1015 			}
1016 
1017 
1018 			frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
1019 			mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
1020 						       frag_map_size,
1021 						       DMA_TO_DEVICE);
1022 			if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
1023 				goto err_dma;
1024 
1025 			if (i == nr_frags - 1 &&
1026 			    (frag_size - frag_map_size) == 0)
1027 				last_frag = true;
1028 
1029 			WRITE_ONCE(txd->txd1, mapped_addr);
1030 			WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
1031 					       TX_DMA_PLEN0(frag_map_size) |
1032 					       last_frag * TX_DMA_LS0));
1033 			WRITE_ONCE(txd->txd4, fport);
1034 
1035 			tx_buf = mtk_desc_to_tx_buf(ring, txd);
1036 			if (new_desc)
1037 				memset(tx_buf, 0, sizeof(*tx_buf));
1038 			tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
1039 			tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
1040 			tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
1041 					 MTK_TX_FLAGS_FPORT1;
1042 
1043 			setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr,
1044 				     frag_map_size, k++);
1045 
1046 			frag_size -= frag_map_size;
1047 			offset += frag_map_size;
1048 		}
1049 	}
1050 
1051 	/* store skb to cleanup */
1052 	itx_buf->skb = skb;
1053 
1054 	WRITE_ONCE(itxd->txd4, txd4);
1055 	WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
1056 				(!nr_frags * TX_DMA_LS0)));
1057 	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1058 		if (k & 0x1)
1059 			txd_pdma->txd2 |= TX_DMA_LS0;
1060 		else
1061 			txd_pdma->txd2 |= TX_DMA_LS1;
1062 	}
1063 
1064 	netdev_sent_queue(dev, skb->len);
1065 	skb_tx_timestamp(skb);
1066 
1067 	ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
1068 	atomic_sub(n_desc, &ring->free_count);
1069 
1070 	/* make sure that all changes to the dma ring are flushed before we
1071 	 * continue
1072 	 */
1073 	wmb();
1074 
1075 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1076 		if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) ||
1077 		    !netdev_xmit_more())
1078 			mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
1079 	} else {
1080 		int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd),
1081 					     ring->dma_size);
1082 		mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
1083 	}
1084 
1085 	return 0;
1086 
1087 err_dma:
1088 	do {
1089 		tx_buf = mtk_desc_to_tx_buf(ring, itxd);
1090 
1091 		/* unmap dma */
1092 		mtk_tx_unmap(eth, tx_buf);
1093 
1094 		itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1095 		if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
1096 			itxd_pdma->txd2 = TX_DMA_DESP2_DEF;
1097 
1098 		itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
1099 		itxd_pdma = qdma_to_pdma(ring, itxd);
1100 	} while (itxd != txd);
1101 
1102 	return -ENOMEM;
1103 }
1104 
mtk_cal_txd_req(struct sk_buff * skb)1105 static inline int mtk_cal_txd_req(struct sk_buff *skb)
1106 {
1107 	int i, nfrags;
1108 	skb_frag_t *frag;
1109 
1110 	nfrags = 1;
1111 	if (skb_is_gso(skb)) {
1112 		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1113 			frag = &skb_shinfo(skb)->frags[i];
1114 			nfrags += DIV_ROUND_UP(skb_frag_size(frag),
1115 						MTK_TX_DMA_BUF_LEN);
1116 		}
1117 	} else {
1118 		nfrags += skb_shinfo(skb)->nr_frags;
1119 	}
1120 
1121 	return nfrags;
1122 }
1123 
mtk_queue_stopped(struct mtk_eth * eth)1124 static int mtk_queue_stopped(struct mtk_eth *eth)
1125 {
1126 	int i;
1127 
1128 	for (i = 0; i < MTK_MAC_COUNT; i++) {
1129 		if (!eth->netdev[i])
1130 			continue;
1131 		if (netif_queue_stopped(eth->netdev[i]))
1132 			return 1;
1133 	}
1134 
1135 	return 0;
1136 }
1137 
mtk_wake_queue(struct mtk_eth * eth)1138 static void mtk_wake_queue(struct mtk_eth *eth)
1139 {
1140 	int i;
1141 
1142 	for (i = 0; i < MTK_MAC_COUNT; i++) {
1143 		if (!eth->netdev[i])
1144 			continue;
1145 		netif_wake_queue(eth->netdev[i]);
1146 	}
1147 }
1148 
mtk_stop_queue(struct mtk_eth * eth)1149 static void mtk_stop_queue(struct mtk_eth *eth)
1150 {
1151 	int i;
1152 
1153 	for (i = 0; i < MTK_MAC_COUNT; i++) {
1154 		if (!eth->netdev[i])
1155 			continue;
1156 		netif_stop_queue(eth->netdev[i]);
1157 	}
1158 }
1159 
mtk_start_xmit(struct sk_buff * skb,struct net_device * dev)1160 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
1161 {
1162 	struct mtk_mac *mac = netdev_priv(dev);
1163 	struct mtk_eth *eth = mac->hw;
1164 	struct mtk_tx_ring *ring = &eth->tx_ring;
1165 	struct net_device_stats *stats = &dev->stats;
1166 	bool gso = false;
1167 	int tx_num;
1168 
1169 	/* normally we can rely on the stack not calling this more than once,
1170 	 * however we have 2 queues running on the same ring so we need to lock
1171 	 * the ring access
1172 	 */
1173 	spin_lock(&eth->page_lock);
1174 
1175 	if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
1176 		goto drop;
1177 
1178 	tx_num = mtk_cal_txd_req(skb);
1179 	if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
1180 		mtk_stop_queue(eth);
1181 		netif_err(eth, tx_queued, dev,
1182 			  "Tx Ring full when queue awake!\n");
1183 		spin_unlock(&eth->page_lock);
1184 		return NETDEV_TX_BUSY;
1185 	}
1186 
1187 	/* TSO: fill MSS info in tcp checksum field */
1188 	if (skb_is_gso(skb)) {
1189 		if (skb_cow_head(skb, 0)) {
1190 			netif_warn(eth, tx_err, dev,
1191 				   "GSO expand head fail.\n");
1192 			goto drop;
1193 		}
1194 
1195 		if (skb_shinfo(skb)->gso_type &
1196 				(SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1197 			gso = true;
1198 			tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
1199 		}
1200 	}
1201 
1202 	if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
1203 		goto drop;
1204 
1205 	if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
1206 		mtk_stop_queue(eth);
1207 
1208 	spin_unlock(&eth->page_lock);
1209 
1210 	return NETDEV_TX_OK;
1211 
1212 drop:
1213 	spin_unlock(&eth->page_lock);
1214 	stats->tx_dropped++;
1215 	dev_kfree_skb_any(skb);
1216 	return NETDEV_TX_OK;
1217 }
1218 
mtk_get_rx_ring(struct mtk_eth * eth)1219 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
1220 {
1221 	int i;
1222 	struct mtk_rx_ring *ring;
1223 	int idx;
1224 
1225 	if (!eth->hwlro)
1226 		return &eth->rx_ring[0];
1227 
1228 	for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1229 		ring = &eth->rx_ring[i];
1230 		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1231 		if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
1232 			ring->calc_idx_update = true;
1233 			return ring;
1234 		}
1235 	}
1236 
1237 	return NULL;
1238 }
1239 
mtk_update_rx_cpu_idx(struct mtk_eth * eth)1240 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
1241 {
1242 	struct mtk_rx_ring *ring;
1243 	int i;
1244 
1245 	if (!eth->hwlro) {
1246 		ring = &eth->rx_ring[0];
1247 		mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1248 	} else {
1249 		for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
1250 			ring = &eth->rx_ring[i];
1251 			if (ring->calc_idx_update) {
1252 				ring->calc_idx_update = false;
1253 				mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
1254 			}
1255 		}
1256 	}
1257 }
1258 
mtk_poll_rx(struct napi_struct * napi,int budget,struct mtk_eth * eth)1259 static int mtk_poll_rx(struct napi_struct *napi, int budget,
1260 		       struct mtk_eth *eth)
1261 {
1262 	struct mtk_rx_ring *ring;
1263 	int idx;
1264 	struct sk_buff *skb;
1265 	u8 *data, *new_data;
1266 	struct mtk_rx_dma *rxd, trxd;
1267 	int done = 0;
1268 
1269 	while (done < budget) {
1270 		struct net_device *netdev;
1271 		unsigned int pktlen;
1272 		dma_addr_t dma_addr;
1273 		int mac;
1274 
1275 		ring = mtk_get_rx_ring(eth);
1276 		if (unlikely(!ring))
1277 			goto rx_done;
1278 
1279 		idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
1280 		rxd = &ring->dma[idx];
1281 		data = ring->data[idx];
1282 
1283 		mtk_rx_get_desc(&trxd, rxd);
1284 		if (!(trxd.rxd2 & RX_DMA_DONE))
1285 			break;
1286 
1287 		/* find out which mac the packet come from. values start at 1 */
1288 		if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
1289 			mac = 0;
1290 		} else {
1291 			mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
1292 				RX_DMA_FPORT_MASK;
1293 			mac--;
1294 		}
1295 
1296 		if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
1297 			     !eth->netdev[mac]))
1298 			goto release_desc;
1299 
1300 		netdev = eth->netdev[mac];
1301 
1302 		if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
1303 			goto release_desc;
1304 
1305 		/* alloc new buffer */
1306 		new_data = napi_alloc_frag(ring->frag_size);
1307 		if (unlikely(!new_data)) {
1308 			netdev->stats.rx_dropped++;
1309 			goto release_desc;
1310 		}
1311 		dma_addr = dma_map_single(eth->dev,
1312 					  new_data + NET_SKB_PAD +
1313 					  eth->ip_align,
1314 					  ring->buf_size,
1315 					  DMA_FROM_DEVICE);
1316 		if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
1317 			skb_free_frag(new_data);
1318 			netdev->stats.rx_dropped++;
1319 			goto release_desc;
1320 		}
1321 
1322 		/* receive data */
1323 		skb = build_skb(data, ring->frag_size);
1324 		if (unlikely(!skb)) {
1325 			skb_free_frag(new_data);
1326 			netdev->stats.rx_dropped++;
1327 			goto release_desc;
1328 		}
1329 		skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1330 
1331 		dma_unmap_single(eth->dev, trxd.rxd1,
1332 				 ring->buf_size, DMA_FROM_DEVICE);
1333 		pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1334 		skb->dev = netdev;
1335 		skb_put(skb, pktlen);
1336 		if (trxd.rxd4 & eth->rx_dma_l4_valid)
1337 			skb->ip_summed = CHECKSUM_UNNECESSARY;
1338 		else
1339 			skb_checksum_none_assert(skb);
1340 		skb->protocol = eth_type_trans(skb, netdev);
1341 
1342 		if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
1343 		    (trxd.rxd2 & RX_DMA_VTAG))
1344 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1345 					       RX_DMA_VID(trxd.rxd3));
1346 		skb_record_rx_queue(skb, 0);
1347 		napi_gro_receive(napi, skb);
1348 
1349 		ring->data[idx] = new_data;
1350 		rxd->rxd1 = (unsigned int)dma_addr;
1351 
1352 release_desc:
1353 		if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
1354 			rxd->rxd2 = RX_DMA_LSO;
1355 		else
1356 			rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
1357 
1358 		ring->calc_idx = idx;
1359 
1360 		done++;
1361 	}
1362 
1363 rx_done:
1364 	if (done) {
1365 		/* make sure that all changes to the dma ring are flushed before
1366 		 * we continue
1367 		 */
1368 		wmb();
1369 		mtk_update_rx_cpu_idx(eth);
1370 	}
1371 
1372 	return done;
1373 }
1374 
mtk_poll_tx_qdma(struct mtk_eth * eth,int budget,unsigned int * done,unsigned int * bytes)1375 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget,
1376 			    unsigned int *done, unsigned int *bytes)
1377 {
1378 	struct mtk_tx_ring *ring = &eth->tx_ring;
1379 	struct mtk_tx_dma *desc;
1380 	struct sk_buff *skb;
1381 	struct mtk_tx_buf *tx_buf;
1382 	u32 cpu, dma;
1383 
1384 	cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
1385 	dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1386 
1387 	desc = mtk_qdma_phys_to_virt(ring, cpu);
1388 
1389 	while ((cpu != dma) && budget) {
1390 		u32 next_cpu = desc->txd2;
1391 		int mac = 0;
1392 
1393 		desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
1394 		if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
1395 			break;
1396 
1397 		tx_buf = mtk_desc_to_tx_buf(ring, desc);
1398 		if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
1399 			mac = 1;
1400 
1401 		skb = tx_buf->skb;
1402 		if (!skb)
1403 			break;
1404 
1405 		if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1406 			bytes[mac] += skb->len;
1407 			done[mac]++;
1408 			budget--;
1409 		}
1410 		mtk_tx_unmap(eth, tx_buf);
1411 
1412 		ring->last_free = desc;
1413 		atomic_inc(&ring->free_count);
1414 
1415 		cpu = next_cpu;
1416 	}
1417 
1418 	mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1419 
1420 	return budget;
1421 }
1422 
mtk_poll_tx_pdma(struct mtk_eth * eth,int budget,unsigned int * done,unsigned int * bytes)1423 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
1424 			    unsigned int *done, unsigned int *bytes)
1425 {
1426 	struct mtk_tx_ring *ring = &eth->tx_ring;
1427 	struct mtk_tx_dma *desc;
1428 	struct sk_buff *skb;
1429 	struct mtk_tx_buf *tx_buf;
1430 	u32 cpu, dma;
1431 
1432 	cpu = ring->cpu_idx;
1433 	dma = mtk_r32(eth, MT7628_TX_DTX_IDX0);
1434 
1435 	while ((cpu != dma) && budget) {
1436 		tx_buf = &ring->buf[cpu];
1437 		skb = tx_buf->skb;
1438 		if (!skb)
1439 			break;
1440 
1441 		if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1442 			bytes[0] += skb->len;
1443 			done[0]++;
1444 			budget--;
1445 		}
1446 
1447 		mtk_tx_unmap(eth, tx_buf);
1448 
1449 		desc = &ring->dma[cpu];
1450 		ring->last_free = desc;
1451 		atomic_inc(&ring->free_count);
1452 
1453 		cpu = NEXT_DESP_IDX(cpu, ring->dma_size);
1454 	}
1455 
1456 	ring->cpu_idx = cpu;
1457 
1458 	return budget;
1459 }
1460 
mtk_poll_tx(struct mtk_eth * eth,int budget)1461 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
1462 {
1463 	struct mtk_tx_ring *ring = &eth->tx_ring;
1464 	unsigned int done[MTK_MAX_DEVS];
1465 	unsigned int bytes[MTK_MAX_DEVS];
1466 	int total = 0, i;
1467 
1468 	memset(done, 0, sizeof(done));
1469 	memset(bytes, 0, sizeof(bytes));
1470 
1471 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
1472 		budget = mtk_poll_tx_qdma(eth, budget, done, bytes);
1473 	else
1474 		budget = mtk_poll_tx_pdma(eth, budget, done, bytes);
1475 
1476 	for (i = 0; i < MTK_MAC_COUNT; i++) {
1477 		if (!eth->netdev[i] || !done[i])
1478 			continue;
1479 		netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1480 		total += done[i];
1481 	}
1482 
1483 	if (mtk_queue_stopped(eth) &&
1484 	    (atomic_read(&ring->free_count) > ring->thresh))
1485 		mtk_wake_queue(eth);
1486 
1487 	return total;
1488 }
1489 
mtk_handle_status_irq(struct mtk_eth * eth)1490 static void mtk_handle_status_irq(struct mtk_eth *eth)
1491 {
1492 	u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
1493 
1494 	if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
1495 		mtk_stats_update(eth);
1496 		mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1497 			MTK_INT_STATUS2);
1498 	}
1499 }
1500 
mtk_napi_tx(struct napi_struct * napi,int budget)1501 static int mtk_napi_tx(struct napi_struct *napi, int budget)
1502 {
1503 	struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
1504 	u32 status, mask;
1505 	int tx_done = 0;
1506 
1507 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
1508 		mtk_handle_status_irq(eth);
1509 	mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg);
1510 	tx_done = mtk_poll_tx(eth, budget);
1511 
1512 	if (unlikely(netif_msg_intr(eth))) {
1513 		status = mtk_r32(eth, eth->tx_int_status_reg);
1514 		mask = mtk_r32(eth, eth->tx_int_mask_reg);
1515 		dev_info(eth->dev,
1516 			 "done tx %d, intr 0x%08x/0x%x\n",
1517 			 tx_done, status, mask);
1518 	}
1519 
1520 	if (tx_done == budget)
1521 		return budget;
1522 
1523 	status = mtk_r32(eth, eth->tx_int_status_reg);
1524 	if (status & MTK_TX_DONE_INT)
1525 		return budget;
1526 
1527 	napi_complete(napi);
1528 	mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1529 
1530 	return tx_done;
1531 }
1532 
mtk_napi_rx(struct napi_struct * napi,int budget)1533 static int mtk_napi_rx(struct napi_struct *napi, int budget)
1534 {
1535 	struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1536 	u32 status, mask;
1537 	int rx_done = 0;
1538 	int remain_budget = budget;
1539 
1540 	mtk_handle_status_irq(eth);
1541 
1542 poll_again:
1543 	mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
1544 	rx_done = mtk_poll_rx(napi, remain_budget, eth);
1545 
1546 	if (unlikely(netif_msg_intr(eth))) {
1547 		status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1548 		mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
1549 		dev_info(eth->dev,
1550 			 "done rx %d, intr 0x%08x/0x%x\n",
1551 			 rx_done, status, mask);
1552 	}
1553 	if (rx_done == remain_budget)
1554 		return budget;
1555 
1556 	status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1557 	if (status & MTK_RX_DONE_INT) {
1558 		remain_budget -= rx_done;
1559 		goto poll_again;
1560 	}
1561 	napi_complete(napi);
1562 	mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1563 
1564 	return rx_done + budget - remain_budget;
1565 }
1566 
mtk_tx_alloc(struct mtk_eth * eth)1567 static int mtk_tx_alloc(struct mtk_eth *eth)
1568 {
1569 	struct mtk_tx_ring *ring = &eth->tx_ring;
1570 	int i, sz = sizeof(*ring->dma);
1571 
1572 	ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1573 			       GFP_KERNEL);
1574 	if (!ring->buf)
1575 		goto no_tx_mem;
1576 
1577 	ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,
1578 				       &ring->phys, GFP_ATOMIC);
1579 	if (!ring->dma)
1580 		goto no_tx_mem;
1581 
1582 	for (i = 0; i < MTK_DMA_SIZE; i++) {
1583 		int next = (i + 1) % MTK_DMA_SIZE;
1584 		u32 next_ptr = ring->phys + next * sz;
1585 
1586 		ring->dma[i].txd2 = next_ptr;
1587 		ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1588 	}
1589 
1590 	/* On MT7688 (PDMA only) this driver uses the ring->dma structs
1591 	 * only as the framework. The real HW descriptors are the PDMA
1592 	 * descriptors in ring->dma_pdma.
1593 	 */
1594 	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1595 		ring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,
1596 						    &ring->phys_pdma,
1597 						    GFP_ATOMIC);
1598 		if (!ring->dma_pdma)
1599 			goto no_tx_mem;
1600 
1601 		for (i = 0; i < MTK_DMA_SIZE; i++) {
1602 			ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF;
1603 			ring->dma_pdma[i].txd4 = 0;
1604 		}
1605 	}
1606 
1607 	ring->dma_size = MTK_DMA_SIZE;
1608 	atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1609 	ring->next_free = &ring->dma[0];
1610 	ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1611 	ring->thresh = MAX_SKB_FRAGS;
1612 
1613 	/* make sure that all changes to the dma ring are flushed before we
1614 	 * continue
1615 	 */
1616 	wmb();
1617 
1618 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
1619 		mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1620 		mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1621 		mtk_w32(eth,
1622 			ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1623 			MTK_QTX_CRX_PTR);
1624 		mtk_w32(eth,
1625 			ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1626 			MTK_QTX_DRX_PTR);
1627 		mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES,
1628 			MTK_QTX_CFG(0));
1629 	} else {
1630 		mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
1631 		mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0);
1632 		mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
1633 		mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX);
1634 	}
1635 
1636 	return 0;
1637 
1638 no_tx_mem:
1639 	return -ENOMEM;
1640 }
1641 
mtk_tx_clean(struct mtk_eth * eth)1642 static void mtk_tx_clean(struct mtk_eth *eth)
1643 {
1644 	struct mtk_tx_ring *ring = &eth->tx_ring;
1645 	int i;
1646 
1647 	if (ring->buf) {
1648 		for (i = 0; i < MTK_DMA_SIZE; i++)
1649 			mtk_tx_unmap(eth, &ring->buf[i]);
1650 		kfree(ring->buf);
1651 		ring->buf = NULL;
1652 	}
1653 
1654 	if (ring->dma) {
1655 		dma_free_coherent(eth->dev,
1656 				  MTK_DMA_SIZE * sizeof(*ring->dma),
1657 				  ring->dma,
1658 				  ring->phys);
1659 		ring->dma = NULL;
1660 	}
1661 
1662 	if (ring->dma_pdma) {
1663 		dma_free_coherent(eth->dev,
1664 				  MTK_DMA_SIZE * sizeof(*ring->dma_pdma),
1665 				  ring->dma_pdma,
1666 				  ring->phys_pdma);
1667 		ring->dma_pdma = NULL;
1668 	}
1669 }
1670 
mtk_rx_alloc(struct mtk_eth * eth,int ring_no,int rx_flag)1671 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
1672 {
1673 	struct mtk_rx_ring *ring;
1674 	int rx_data_len, rx_dma_size;
1675 	int i;
1676 	u32 offset = 0;
1677 
1678 	if (rx_flag == MTK_RX_FLAGS_QDMA) {
1679 		if (ring_no)
1680 			return -EINVAL;
1681 		ring = &eth->rx_ring_qdma;
1682 		offset = 0x1000;
1683 	} else {
1684 		ring = &eth->rx_ring[ring_no];
1685 	}
1686 
1687 	if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1688 		rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1689 		rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1690 	} else {
1691 		rx_data_len = ETH_DATA_LEN;
1692 		rx_dma_size = MTK_DMA_SIZE;
1693 	}
1694 
1695 	ring->frag_size = mtk_max_frag_size(rx_data_len);
1696 	ring->buf_size = mtk_max_buf_size(ring->frag_size);
1697 	ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
1698 			     GFP_KERNEL);
1699 	if (!ring->data)
1700 		return -ENOMEM;
1701 
1702 	for (i = 0; i < rx_dma_size; i++) {
1703 		ring->data[i] = netdev_alloc_frag(ring->frag_size);
1704 		if (!ring->data[i])
1705 			return -ENOMEM;
1706 	}
1707 
1708 	ring->dma = dma_alloc_coherent(eth->dev,
1709 				       rx_dma_size * sizeof(*ring->dma),
1710 				       &ring->phys, GFP_ATOMIC);
1711 	if (!ring->dma)
1712 		return -ENOMEM;
1713 
1714 	for (i = 0; i < rx_dma_size; i++) {
1715 		dma_addr_t dma_addr = dma_map_single(eth->dev,
1716 				ring->data[i] + NET_SKB_PAD + eth->ip_align,
1717 				ring->buf_size,
1718 				DMA_FROM_DEVICE);
1719 		if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1720 			return -ENOMEM;
1721 		ring->dma[i].rxd1 = (unsigned int)dma_addr;
1722 
1723 		if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
1724 			ring->dma[i].rxd2 = RX_DMA_LSO;
1725 		else
1726 			ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1727 	}
1728 	ring->dma_size = rx_dma_size;
1729 	ring->calc_idx_update = false;
1730 	ring->calc_idx = rx_dma_size - 1;
1731 	ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
1732 	/* make sure that all changes to the dma ring are flushed before we
1733 	 * continue
1734 	 */
1735 	wmb();
1736 
1737 	mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
1738 	mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
1739 	mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
1740 	mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
1741 
1742 	return 0;
1743 }
1744 
mtk_rx_clean(struct mtk_eth * eth,struct mtk_rx_ring * ring)1745 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
1746 {
1747 	int i;
1748 
1749 	if (ring->data && ring->dma) {
1750 		for (i = 0; i < ring->dma_size; i++) {
1751 			if (!ring->data[i])
1752 				continue;
1753 			if (!ring->dma[i].rxd1)
1754 				continue;
1755 			dma_unmap_single(eth->dev,
1756 					 ring->dma[i].rxd1,
1757 					 ring->buf_size,
1758 					 DMA_FROM_DEVICE);
1759 			skb_free_frag(ring->data[i]);
1760 		}
1761 		kfree(ring->data);
1762 		ring->data = NULL;
1763 	}
1764 
1765 	if (ring->dma) {
1766 		dma_free_coherent(eth->dev,
1767 				  ring->dma_size * sizeof(*ring->dma),
1768 				  ring->dma,
1769 				  ring->phys);
1770 		ring->dma = NULL;
1771 	}
1772 }
1773 
mtk_hwlro_rx_init(struct mtk_eth * eth)1774 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1775 {
1776 	int i;
1777 	u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1778 	u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1779 
1780 	/* set LRO rings to auto-learn modes */
1781 	ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1782 
1783 	/* validate LRO ring */
1784 	ring_ctrl_dw2 |= MTK_RING_VLD;
1785 
1786 	/* set AGE timer (unit: 20us) */
1787 	ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1788 	ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1789 
1790 	/* set max AGG timer (unit: 20us) */
1791 	ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1792 
1793 	/* set max LRO AGG count */
1794 	ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1795 	ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1796 
1797 	for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1798 		mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1799 		mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1800 		mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1801 	}
1802 
1803 	/* IPv4 checksum update enable */
1804 	lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1805 
1806 	/* switch priority comparison to packet count mode */
1807 	lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1808 
1809 	/* bandwidth threshold setting */
1810 	mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1811 
1812 	/* auto-learn score delta setting */
1813 	mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1814 
1815 	/* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1816 	mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1817 		MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1818 
1819 	/* set HW LRO mode & the max aggregation count for rx packets */
1820 	lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1821 
1822 	/* the minimal remaining room of SDL0 in RXD for lro aggregation */
1823 	lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1824 
1825 	/* enable HW LRO */
1826 	lro_ctrl_dw0 |= MTK_LRO_EN;
1827 
1828 	mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1829 	mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1830 
1831 	return 0;
1832 }
1833 
mtk_hwlro_rx_uninit(struct mtk_eth * eth)1834 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1835 {
1836 	int i;
1837 	u32 val;
1838 
1839 	/* relinquish lro rings, flush aggregated packets */
1840 	mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1841 
1842 	/* wait for relinquishments done */
1843 	for (i = 0; i < 10; i++) {
1844 		val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1845 		if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1846 			msleep(20);
1847 			continue;
1848 		}
1849 		break;
1850 	}
1851 
1852 	/* invalidate lro rings */
1853 	for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1854 		mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1855 
1856 	/* disable HW LRO */
1857 	mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1858 }
1859 
mtk_hwlro_val_ipaddr(struct mtk_eth * eth,int idx,__be32 ip)1860 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1861 {
1862 	u32 reg_val;
1863 
1864 	reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1865 
1866 	/* invalidate the IP setting */
1867 	mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1868 
1869 	mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1870 
1871 	/* validate the IP setting */
1872 	mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1873 }
1874 
mtk_hwlro_inval_ipaddr(struct mtk_eth * eth,int idx)1875 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1876 {
1877 	u32 reg_val;
1878 
1879 	reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1880 
1881 	/* invalidate the IP setting */
1882 	mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1883 
1884 	mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1885 }
1886 
mtk_hwlro_get_ip_cnt(struct mtk_mac * mac)1887 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1888 {
1889 	int cnt = 0;
1890 	int i;
1891 
1892 	for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1893 		if (mac->hwlro_ip[i])
1894 			cnt++;
1895 	}
1896 
1897 	return cnt;
1898 }
1899 
mtk_hwlro_add_ipaddr(struct net_device * dev,struct ethtool_rxnfc * cmd)1900 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1901 				struct ethtool_rxnfc *cmd)
1902 {
1903 	struct ethtool_rx_flow_spec *fsp =
1904 		(struct ethtool_rx_flow_spec *)&cmd->fs;
1905 	struct mtk_mac *mac = netdev_priv(dev);
1906 	struct mtk_eth *eth = mac->hw;
1907 	int hwlro_idx;
1908 
1909 	if ((fsp->flow_type != TCP_V4_FLOW) ||
1910 	    (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1911 	    (fsp->location > 1))
1912 		return -EINVAL;
1913 
1914 	mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1915 	hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1916 
1917 	mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1918 
1919 	mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1920 
1921 	return 0;
1922 }
1923 
mtk_hwlro_del_ipaddr(struct net_device * dev,struct ethtool_rxnfc * cmd)1924 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1925 				struct ethtool_rxnfc *cmd)
1926 {
1927 	struct ethtool_rx_flow_spec *fsp =
1928 		(struct ethtool_rx_flow_spec *)&cmd->fs;
1929 	struct mtk_mac *mac = netdev_priv(dev);
1930 	struct mtk_eth *eth = mac->hw;
1931 	int hwlro_idx;
1932 
1933 	if (fsp->location > 1)
1934 		return -EINVAL;
1935 
1936 	mac->hwlro_ip[fsp->location] = 0;
1937 	hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1938 
1939 	mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1940 
1941 	mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1942 
1943 	return 0;
1944 }
1945 
mtk_hwlro_netdev_disable(struct net_device * dev)1946 static void mtk_hwlro_netdev_disable(struct net_device *dev)
1947 {
1948 	struct mtk_mac *mac = netdev_priv(dev);
1949 	struct mtk_eth *eth = mac->hw;
1950 	int i, hwlro_idx;
1951 
1952 	for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1953 		mac->hwlro_ip[i] = 0;
1954 		hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1955 
1956 		mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1957 	}
1958 
1959 	mac->hwlro_ip_cnt = 0;
1960 }
1961 
mtk_hwlro_get_fdir_entry(struct net_device * dev,struct ethtool_rxnfc * cmd)1962 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1963 				    struct ethtool_rxnfc *cmd)
1964 {
1965 	struct mtk_mac *mac = netdev_priv(dev);
1966 	struct ethtool_rx_flow_spec *fsp =
1967 		(struct ethtool_rx_flow_spec *)&cmd->fs;
1968 
1969 	/* only tcp dst ipv4 is meaningful, others are meaningless */
1970 	fsp->flow_type = TCP_V4_FLOW;
1971 	fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1972 	fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1973 
1974 	fsp->h_u.tcp_ip4_spec.ip4src = 0;
1975 	fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1976 	fsp->h_u.tcp_ip4_spec.psrc = 0;
1977 	fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1978 	fsp->h_u.tcp_ip4_spec.pdst = 0;
1979 	fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
1980 	fsp->h_u.tcp_ip4_spec.tos = 0;
1981 	fsp->m_u.tcp_ip4_spec.tos = 0xff;
1982 
1983 	return 0;
1984 }
1985 
mtk_hwlro_get_fdir_all(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)1986 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
1987 				  struct ethtool_rxnfc *cmd,
1988 				  u32 *rule_locs)
1989 {
1990 	struct mtk_mac *mac = netdev_priv(dev);
1991 	int cnt = 0;
1992 	int i;
1993 
1994 	for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1995 		if (mac->hwlro_ip[i]) {
1996 			rule_locs[cnt] = i;
1997 			cnt++;
1998 		}
1999 	}
2000 
2001 	cmd->rule_cnt = cnt;
2002 
2003 	return 0;
2004 }
2005 
mtk_fix_features(struct net_device * dev,netdev_features_t features)2006 static netdev_features_t mtk_fix_features(struct net_device *dev,
2007 					  netdev_features_t features)
2008 {
2009 	if (!(features & NETIF_F_LRO)) {
2010 		struct mtk_mac *mac = netdev_priv(dev);
2011 		int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
2012 
2013 		if (ip_cnt) {
2014 			netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
2015 
2016 			features |= NETIF_F_LRO;
2017 		}
2018 	}
2019 
2020 	return features;
2021 }
2022 
mtk_set_features(struct net_device * dev,netdev_features_t features)2023 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
2024 {
2025 	int err = 0;
2026 
2027 	if (!((dev->features ^ features) & NETIF_F_LRO))
2028 		return 0;
2029 
2030 	if (!(features & NETIF_F_LRO))
2031 		mtk_hwlro_netdev_disable(dev);
2032 
2033 	return err;
2034 }
2035 
2036 /* wait for DMA to finish whatever it is doing before we start using it again */
mtk_dma_busy_wait(struct mtk_eth * eth)2037 static int mtk_dma_busy_wait(struct mtk_eth *eth)
2038 {
2039 	unsigned long t_start = jiffies;
2040 
2041 	while (1) {
2042 		if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2043 			if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
2044 			      (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
2045 				return 0;
2046 		} else {
2047 			if (!(mtk_r32(eth, MTK_PDMA_GLO_CFG) &
2048 			      (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
2049 				return 0;
2050 		}
2051 
2052 		if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
2053 			break;
2054 	}
2055 
2056 	dev_err(eth->dev, "DMA init timeout\n");
2057 	return -1;
2058 }
2059 
mtk_dma_init(struct mtk_eth * eth)2060 static int mtk_dma_init(struct mtk_eth *eth)
2061 {
2062 	int err;
2063 	u32 i;
2064 
2065 	if (mtk_dma_busy_wait(eth))
2066 		return -EBUSY;
2067 
2068 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2069 		/* QDMA needs scratch memory for internal reordering of the
2070 		 * descriptors
2071 		 */
2072 		err = mtk_init_fq_dma(eth);
2073 		if (err)
2074 			return err;
2075 	}
2076 
2077 	err = mtk_tx_alloc(eth);
2078 	if (err)
2079 		return err;
2080 
2081 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2082 		err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
2083 		if (err)
2084 			return err;
2085 	}
2086 
2087 	err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
2088 	if (err)
2089 		return err;
2090 
2091 	if (eth->hwlro) {
2092 		for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
2093 			err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
2094 			if (err)
2095 				return err;
2096 		}
2097 		err = mtk_hwlro_rx_init(eth);
2098 		if (err)
2099 			return err;
2100 	}
2101 
2102 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2103 		/* Enable random early drop and set drop threshold
2104 		 * automatically
2105 		 */
2106 		mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |
2107 			FC_THRES_MIN, MTK_QDMA_FC_THRES);
2108 		mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
2109 	}
2110 
2111 	return 0;
2112 }
2113 
mtk_dma_free(struct mtk_eth * eth)2114 static void mtk_dma_free(struct mtk_eth *eth)
2115 {
2116 	int i;
2117 
2118 	for (i = 0; i < MTK_MAC_COUNT; i++)
2119 		if (eth->netdev[i])
2120 			netdev_reset_queue(eth->netdev[i]);
2121 	if (eth->scratch_ring) {
2122 		dma_free_coherent(eth->dev,
2123 				  MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
2124 				  eth->scratch_ring,
2125 				  eth->phy_scratch_ring);
2126 		eth->scratch_ring = NULL;
2127 		eth->phy_scratch_ring = 0;
2128 	}
2129 	mtk_tx_clean(eth);
2130 	mtk_rx_clean(eth, &eth->rx_ring[0]);
2131 	mtk_rx_clean(eth, &eth->rx_ring_qdma);
2132 
2133 	if (eth->hwlro) {
2134 		mtk_hwlro_rx_uninit(eth);
2135 		for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
2136 			mtk_rx_clean(eth, &eth->rx_ring[i]);
2137 	}
2138 
2139 	kfree(eth->scratch_head);
2140 }
2141 
mtk_tx_timeout(struct net_device * dev,unsigned int txqueue)2142 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue)
2143 {
2144 	struct mtk_mac *mac = netdev_priv(dev);
2145 	struct mtk_eth *eth = mac->hw;
2146 
2147 	eth->netdev[mac->id]->stats.tx_errors++;
2148 	netif_err(eth, tx_err, dev,
2149 		  "transmit timed out\n");
2150 	schedule_work(&eth->pending_work);
2151 }
2152 
mtk_handle_irq_rx(int irq,void * _eth)2153 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
2154 {
2155 	struct mtk_eth *eth = _eth;
2156 
2157 	if (likely(napi_schedule_prep(&eth->rx_napi))) {
2158 		__napi_schedule(&eth->rx_napi);
2159 		mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
2160 	}
2161 
2162 	return IRQ_HANDLED;
2163 }
2164 
mtk_handle_irq_tx(int irq,void * _eth)2165 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
2166 {
2167 	struct mtk_eth *eth = _eth;
2168 
2169 	if (likely(napi_schedule_prep(&eth->tx_napi))) {
2170 		__napi_schedule(&eth->tx_napi);
2171 		mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2172 	}
2173 
2174 	return IRQ_HANDLED;
2175 }
2176 
mtk_handle_irq(int irq,void * _eth)2177 static irqreturn_t mtk_handle_irq(int irq, void *_eth)
2178 {
2179 	struct mtk_eth *eth = _eth;
2180 
2181 	if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) {
2182 		if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT)
2183 			mtk_handle_irq_rx(irq, _eth);
2184 	}
2185 	if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) {
2186 		if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT)
2187 			mtk_handle_irq_tx(irq, _eth);
2188 	}
2189 
2190 	return IRQ_HANDLED;
2191 }
2192 
2193 #ifdef CONFIG_NET_POLL_CONTROLLER
mtk_poll_controller(struct net_device * dev)2194 static void mtk_poll_controller(struct net_device *dev)
2195 {
2196 	struct mtk_mac *mac = netdev_priv(dev);
2197 	struct mtk_eth *eth = mac->hw;
2198 
2199 	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2200 	mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
2201 	mtk_handle_irq_rx(eth->irq[2], dev);
2202 	mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2203 	mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
2204 }
2205 #endif
2206 
mtk_start_dma(struct mtk_eth * eth)2207 static int mtk_start_dma(struct mtk_eth *eth)
2208 {
2209 	u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;
2210 	int err;
2211 
2212 	err = mtk_dma_init(eth);
2213 	if (err) {
2214 		mtk_dma_free(eth);
2215 		return err;
2216 	}
2217 
2218 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2219 		mtk_w32(eth,
2220 			MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
2221 			MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |
2222 			MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
2223 			MTK_RX_BT_32DWORDS,
2224 			MTK_QDMA_GLO_CFG);
2225 
2226 		mtk_w32(eth,
2227 			MTK_RX_DMA_EN | rx_2b_offset |
2228 			MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
2229 			MTK_PDMA_GLO_CFG);
2230 	} else {
2231 		mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |
2232 			MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS,
2233 			MTK_PDMA_GLO_CFG);
2234 	}
2235 
2236 	return 0;
2237 }
2238 
mtk_gdm_config(struct mtk_eth * eth,u32 config)2239 static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
2240 {
2241 	int i;
2242 
2243 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
2244 		return;
2245 
2246 	for (i = 0; i < MTK_MAC_COUNT; i++) {
2247 		u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
2248 
2249 		/* default setup the forward port to send frame to PDMA */
2250 		val &= ~0xffff;
2251 
2252 		/* Enable RX checksum */
2253 		val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
2254 
2255 		val |= config;
2256 
2257 		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
2258 	}
2259 	/* Reset and enable PSE */
2260 	mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
2261 	mtk_w32(eth, 0, MTK_RST_GL);
2262 }
2263 
mtk_open(struct net_device * dev)2264 static int mtk_open(struct net_device *dev)
2265 {
2266 	struct mtk_mac *mac = netdev_priv(dev);
2267 	struct mtk_eth *eth = mac->hw;
2268 	int err;
2269 
2270 	err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
2271 	if (err) {
2272 		netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
2273 			   err);
2274 		return err;
2275 	}
2276 
2277 	/* we run 2 netdevs on the same dma ring so we only bring it up once */
2278 	if (!refcount_read(&eth->dma_refcnt)) {
2279 		int err = mtk_start_dma(eth);
2280 
2281 		if (err)
2282 			return err;
2283 
2284 		mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
2285 
2286 		napi_enable(&eth->tx_napi);
2287 		napi_enable(&eth->rx_napi);
2288 		mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
2289 		mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
2290 		refcount_set(&eth->dma_refcnt, 1);
2291 	}
2292 	else
2293 		refcount_inc(&eth->dma_refcnt);
2294 
2295 	phylink_start(mac->phylink);
2296 	netif_start_queue(dev);
2297 	return 0;
2298 }
2299 
mtk_stop_dma(struct mtk_eth * eth,u32 glo_cfg)2300 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
2301 {
2302 	u32 val;
2303 	int i;
2304 
2305 	/* stop the dma engine */
2306 	spin_lock_bh(&eth->page_lock);
2307 	val = mtk_r32(eth, glo_cfg);
2308 	mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
2309 		glo_cfg);
2310 	spin_unlock_bh(&eth->page_lock);
2311 
2312 	/* wait for dma stop */
2313 	for (i = 0; i < 10; i++) {
2314 		val = mtk_r32(eth, glo_cfg);
2315 		if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
2316 			msleep(20);
2317 			continue;
2318 		}
2319 		break;
2320 	}
2321 }
2322 
mtk_stop(struct net_device * dev)2323 static int mtk_stop(struct net_device *dev)
2324 {
2325 	struct mtk_mac *mac = netdev_priv(dev);
2326 	struct mtk_eth *eth = mac->hw;
2327 
2328 	phylink_stop(mac->phylink);
2329 
2330 	netif_tx_disable(dev);
2331 
2332 	phylink_disconnect_phy(mac->phylink);
2333 
2334 	/* only shutdown DMA if this is the last user */
2335 	if (!refcount_dec_and_test(&eth->dma_refcnt))
2336 		return 0;
2337 
2338 	mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
2339 
2340 	mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
2341 	mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
2342 	napi_disable(&eth->tx_napi);
2343 	napi_disable(&eth->rx_napi);
2344 
2345 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
2346 		mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
2347 	mtk_stop_dma(eth, MTK_PDMA_GLO_CFG);
2348 
2349 	mtk_dma_free(eth);
2350 
2351 	return 0;
2352 }
2353 
ethsys_reset(struct mtk_eth * eth,u32 reset_bits)2354 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
2355 {
2356 	regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
2357 			   reset_bits,
2358 			   reset_bits);
2359 
2360 	usleep_range(1000, 1100);
2361 	regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
2362 			   reset_bits,
2363 			   ~reset_bits);
2364 	mdelay(10);
2365 }
2366 
mtk_clk_disable(struct mtk_eth * eth)2367 static void mtk_clk_disable(struct mtk_eth *eth)
2368 {
2369 	int clk;
2370 
2371 	for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
2372 		clk_disable_unprepare(eth->clks[clk]);
2373 }
2374 
mtk_clk_enable(struct mtk_eth * eth)2375 static int mtk_clk_enable(struct mtk_eth *eth)
2376 {
2377 	int clk, ret;
2378 
2379 	for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
2380 		ret = clk_prepare_enable(eth->clks[clk]);
2381 		if (ret)
2382 			goto err_disable_clks;
2383 	}
2384 
2385 	return 0;
2386 
2387 err_disable_clks:
2388 	while (--clk >= 0)
2389 		clk_disable_unprepare(eth->clks[clk]);
2390 
2391 	return ret;
2392 }
2393 
mtk_hw_init(struct mtk_eth * eth)2394 static int mtk_hw_init(struct mtk_eth *eth)
2395 {
2396 	int i, val, ret;
2397 
2398 	if (test_and_set_bit(MTK_HW_INIT, &eth->state))
2399 		return 0;
2400 
2401 	pm_runtime_enable(eth->dev);
2402 	pm_runtime_get_sync(eth->dev);
2403 
2404 	ret = mtk_clk_enable(eth);
2405 	if (ret)
2406 		goto err_disable_pm;
2407 
2408 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
2409 		ret = device_reset(eth->dev);
2410 		if (ret) {
2411 			dev_err(eth->dev, "MAC reset failed!\n");
2412 			goto err_disable_pm;
2413 		}
2414 
2415 		/* enable interrupt delay for RX */
2416 		mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
2417 
2418 		/* disable delay and normal interrupt */
2419 		mtk_tx_irq_disable(eth, ~0);
2420 		mtk_rx_irq_disable(eth, ~0);
2421 
2422 		return 0;
2423 	}
2424 
2425 	/* Non-MT7628 handling... */
2426 	ethsys_reset(eth, RSTCTRL_FE);
2427 	ethsys_reset(eth, RSTCTRL_PPE);
2428 
2429 	if (eth->pctl) {
2430 		/* Set GE2 driving and slew rate */
2431 		regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
2432 
2433 		/* set GE2 TDSEL */
2434 		regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
2435 
2436 		/* set GE2 TUNE */
2437 		regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
2438 	}
2439 
2440 	/* Set linkdown as the default for each GMAC. Its own MCR would be set
2441 	 * up with the more appropriate value when mtk_mac_config call is being
2442 	 * invoked.
2443 	 */
2444 	for (i = 0; i < MTK_MAC_COUNT; i++)
2445 		mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));
2446 
2447 	/* Indicates CDM to parse the MTK special tag from CPU
2448 	 * which also is working out for untag packets.
2449 	 */
2450 	val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
2451 	mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
2452 
2453 	/* Enable RX VLan Offloading */
2454 	mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
2455 
2456 	/* enable interrupt delay for RX */
2457 	mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
2458 
2459 	/* disable delay and normal interrupt */
2460 	mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
2461 	mtk_tx_irq_disable(eth, ~0);
2462 	mtk_rx_irq_disable(eth, ~0);
2463 
2464 	/* FE int grouping */
2465 	mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
2466 	mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
2467 	mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
2468 	mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
2469 	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
2470 
2471 	return 0;
2472 
2473 err_disable_pm:
2474 	pm_runtime_put_sync(eth->dev);
2475 	pm_runtime_disable(eth->dev);
2476 
2477 	return ret;
2478 }
2479 
mtk_hw_deinit(struct mtk_eth * eth)2480 static int mtk_hw_deinit(struct mtk_eth *eth)
2481 {
2482 	if (!test_and_clear_bit(MTK_HW_INIT, &eth->state))
2483 		return 0;
2484 
2485 	mtk_clk_disable(eth);
2486 
2487 	pm_runtime_put_sync(eth->dev);
2488 	pm_runtime_disable(eth->dev);
2489 
2490 	return 0;
2491 }
2492 
mtk_init(struct net_device * dev)2493 static int __init mtk_init(struct net_device *dev)
2494 {
2495 	struct mtk_mac *mac = netdev_priv(dev);
2496 	struct mtk_eth *eth = mac->hw;
2497 	const char *mac_addr;
2498 
2499 	mac_addr = of_get_mac_address(mac->of_node);
2500 	if (!IS_ERR(mac_addr))
2501 		ether_addr_copy(dev->dev_addr, mac_addr);
2502 
2503 	/* If the mac address is invalid, use random mac address  */
2504 	if (!is_valid_ether_addr(dev->dev_addr)) {
2505 		eth_hw_addr_random(dev);
2506 		dev_err(eth->dev, "generated random MAC address %pM\n",
2507 			dev->dev_addr);
2508 	}
2509 
2510 	return 0;
2511 }
2512 
mtk_uninit(struct net_device * dev)2513 static void mtk_uninit(struct net_device *dev)
2514 {
2515 	struct mtk_mac *mac = netdev_priv(dev);
2516 	struct mtk_eth *eth = mac->hw;
2517 
2518 	phylink_disconnect_phy(mac->phylink);
2519 	mtk_tx_irq_disable(eth, ~0);
2520 	mtk_rx_irq_disable(eth, ~0);
2521 }
2522 
mtk_do_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)2523 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2524 {
2525 	struct mtk_mac *mac = netdev_priv(dev);
2526 
2527 	switch (cmd) {
2528 	case SIOCGMIIPHY:
2529 	case SIOCGMIIREG:
2530 	case SIOCSMIIREG:
2531 		return phylink_mii_ioctl(mac->phylink, ifr, cmd);
2532 	default:
2533 		break;
2534 	}
2535 
2536 	return -EOPNOTSUPP;
2537 }
2538 
mtk_pending_work(struct work_struct * work)2539 static void mtk_pending_work(struct work_struct *work)
2540 {
2541 	struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
2542 	int err, i;
2543 	unsigned long restart = 0;
2544 
2545 	rtnl_lock();
2546 
2547 	dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
2548 
2549 	while (test_and_set_bit_lock(MTK_RESETTING, &eth->state))
2550 		cpu_relax();
2551 
2552 	dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
2553 	/* stop all devices to make sure that dma is properly shut down */
2554 	for (i = 0; i < MTK_MAC_COUNT; i++) {
2555 		if (!eth->netdev[i])
2556 			continue;
2557 		mtk_stop(eth->netdev[i]);
2558 		__set_bit(i, &restart);
2559 	}
2560 	dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
2561 
2562 	/* restart underlying hardware such as power, clock, pin mux
2563 	 * and the connected phy
2564 	 */
2565 	mtk_hw_deinit(eth);
2566 
2567 	if (eth->dev->pins)
2568 		pinctrl_select_state(eth->dev->pins->p,
2569 				     eth->dev->pins->default_state);
2570 	mtk_hw_init(eth);
2571 
2572 	/* restart DMA and enable IRQs */
2573 	for (i = 0; i < MTK_MAC_COUNT; i++) {
2574 		if (!test_bit(i, &restart))
2575 			continue;
2576 		err = mtk_open(eth->netdev[i]);
2577 		if (err) {
2578 			netif_alert(eth, ifup, eth->netdev[i],
2579 			      "Driver up/down cycle failed, closing device.\n");
2580 			dev_close(eth->netdev[i]);
2581 		}
2582 	}
2583 
2584 	dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
2585 
2586 	clear_bit_unlock(MTK_RESETTING, &eth->state);
2587 
2588 	rtnl_unlock();
2589 }
2590 
mtk_free_dev(struct mtk_eth * eth)2591 static int mtk_free_dev(struct mtk_eth *eth)
2592 {
2593 	int i;
2594 
2595 	for (i = 0; i < MTK_MAC_COUNT; i++) {
2596 		if (!eth->netdev[i])
2597 			continue;
2598 		free_netdev(eth->netdev[i]);
2599 	}
2600 
2601 	return 0;
2602 }
2603 
mtk_unreg_dev(struct mtk_eth * eth)2604 static int mtk_unreg_dev(struct mtk_eth *eth)
2605 {
2606 	int i;
2607 
2608 	for (i = 0; i < MTK_MAC_COUNT; i++) {
2609 		if (!eth->netdev[i])
2610 			continue;
2611 		unregister_netdev(eth->netdev[i]);
2612 	}
2613 
2614 	return 0;
2615 }
2616 
mtk_cleanup(struct mtk_eth * eth)2617 static int mtk_cleanup(struct mtk_eth *eth)
2618 {
2619 	mtk_unreg_dev(eth);
2620 	mtk_free_dev(eth);
2621 	cancel_work_sync(&eth->pending_work);
2622 
2623 	return 0;
2624 }
2625 
mtk_get_link_ksettings(struct net_device * ndev,struct ethtool_link_ksettings * cmd)2626 static int mtk_get_link_ksettings(struct net_device *ndev,
2627 				  struct ethtool_link_ksettings *cmd)
2628 {
2629 	struct mtk_mac *mac = netdev_priv(ndev);
2630 
2631 	if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2632 		return -EBUSY;
2633 
2634 	return phylink_ethtool_ksettings_get(mac->phylink, cmd);
2635 }
2636 
mtk_set_link_ksettings(struct net_device * ndev,const struct ethtool_link_ksettings * cmd)2637 static int mtk_set_link_ksettings(struct net_device *ndev,
2638 				  const struct ethtool_link_ksettings *cmd)
2639 {
2640 	struct mtk_mac *mac = netdev_priv(ndev);
2641 
2642 	if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2643 		return -EBUSY;
2644 
2645 	return phylink_ethtool_ksettings_set(mac->phylink, cmd);
2646 }
2647 
mtk_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)2648 static void mtk_get_drvinfo(struct net_device *dev,
2649 			    struct ethtool_drvinfo *info)
2650 {
2651 	struct mtk_mac *mac = netdev_priv(dev);
2652 
2653 	strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2654 	strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2655 	info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2656 }
2657 
mtk_get_msglevel(struct net_device * dev)2658 static u32 mtk_get_msglevel(struct net_device *dev)
2659 {
2660 	struct mtk_mac *mac = netdev_priv(dev);
2661 
2662 	return mac->hw->msg_enable;
2663 }
2664 
mtk_set_msglevel(struct net_device * dev,u32 value)2665 static void mtk_set_msglevel(struct net_device *dev, u32 value)
2666 {
2667 	struct mtk_mac *mac = netdev_priv(dev);
2668 
2669 	mac->hw->msg_enable = value;
2670 }
2671 
mtk_nway_reset(struct net_device * dev)2672 static int mtk_nway_reset(struct net_device *dev)
2673 {
2674 	struct mtk_mac *mac = netdev_priv(dev);
2675 
2676 	if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2677 		return -EBUSY;
2678 
2679 	if (!mac->phylink)
2680 		return -ENOTSUPP;
2681 
2682 	return phylink_ethtool_nway_reset(mac->phylink);
2683 }
2684 
mtk_get_strings(struct net_device * dev,u32 stringset,u8 * data)2685 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2686 {
2687 	int i;
2688 
2689 	switch (stringset) {
2690 	case ETH_SS_STATS:
2691 		for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2692 			memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2693 			data += ETH_GSTRING_LEN;
2694 		}
2695 		break;
2696 	}
2697 }
2698 
mtk_get_sset_count(struct net_device * dev,int sset)2699 static int mtk_get_sset_count(struct net_device *dev, int sset)
2700 {
2701 	switch (sset) {
2702 	case ETH_SS_STATS:
2703 		return ARRAY_SIZE(mtk_ethtool_stats);
2704 	default:
2705 		return -EOPNOTSUPP;
2706 	}
2707 }
2708 
mtk_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)2709 static void mtk_get_ethtool_stats(struct net_device *dev,
2710 				  struct ethtool_stats *stats, u64 *data)
2711 {
2712 	struct mtk_mac *mac = netdev_priv(dev);
2713 	struct mtk_hw_stats *hwstats = mac->hw_stats;
2714 	u64 *data_src, *data_dst;
2715 	unsigned int start;
2716 	int i;
2717 
2718 	if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2719 		return;
2720 
2721 	if (netif_running(dev) && netif_device_present(dev)) {
2722 		if (spin_trylock_bh(&hwstats->stats_lock)) {
2723 			mtk_stats_update_mac(mac);
2724 			spin_unlock_bh(&hwstats->stats_lock);
2725 		}
2726 	}
2727 
2728 	data_src = (u64 *)hwstats;
2729 
2730 	do {
2731 		data_dst = data;
2732 		start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2733 
2734 		for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2735 			*data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2736 	} while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2737 }
2738 
mtk_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)2739 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2740 			 u32 *rule_locs)
2741 {
2742 	int ret = -EOPNOTSUPP;
2743 
2744 	switch (cmd->cmd) {
2745 	case ETHTOOL_GRXRINGS:
2746 		if (dev->hw_features & NETIF_F_LRO) {
2747 			cmd->data = MTK_MAX_RX_RING_NUM;
2748 			ret = 0;
2749 		}
2750 		break;
2751 	case ETHTOOL_GRXCLSRLCNT:
2752 		if (dev->hw_features & NETIF_F_LRO) {
2753 			struct mtk_mac *mac = netdev_priv(dev);
2754 
2755 			cmd->rule_cnt = mac->hwlro_ip_cnt;
2756 			ret = 0;
2757 		}
2758 		break;
2759 	case ETHTOOL_GRXCLSRULE:
2760 		if (dev->hw_features & NETIF_F_LRO)
2761 			ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2762 		break;
2763 	case ETHTOOL_GRXCLSRLALL:
2764 		if (dev->hw_features & NETIF_F_LRO)
2765 			ret = mtk_hwlro_get_fdir_all(dev, cmd,
2766 						     rule_locs);
2767 		break;
2768 	default:
2769 		break;
2770 	}
2771 
2772 	return ret;
2773 }
2774 
mtk_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)2775 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2776 {
2777 	int ret = -EOPNOTSUPP;
2778 
2779 	switch (cmd->cmd) {
2780 	case ETHTOOL_SRXCLSRLINS:
2781 		if (dev->hw_features & NETIF_F_LRO)
2782 			ret = mtk_hwlro_add_ipaddr(dev, cmd);
2783 		break;
2784 	case ETHTOOL_SRXCLSRLDEL:
2785 		if (dev->hw_features & NETIF_F_LRO)
2786 			ret = mtk_hwlro_del_ipaddr(dev, cmd);
2787 		break;
2788 	default:
2789 		break;
2790 	}
2791 
2792 	return ret;
2793 }
2794 
2795 static const struct ethtool_ops mtk_ethtool_ops = {
2796 	.get_link_ksettings	= mtk_get_link_ksettings,
2797 	.set_link_ksettings	= mtk_set_link_ksettings,
2798 	.get_drvinfo		= mtk_get_drvinfo,
2799 	.get_msglevel		= mtk_get_msglevel,
2800 	.set_msglevel		= mtk_set_msglevel,
2801 	.nway_reset		= mtk_nway_reset,
2802 	.get_link		= ethtool_op_get_link,
2803 	.get_strings		= mtk_get_strings,
2804 	.get_sset_count		= mtk_get_sset_count,
2805 	.get_ethtool_stats	= mtk_get_ethtool_stats,
2806 	.get_rxnfc		= mtk_get_rxnfc,
2807 	.set_rxnfc              = mtk_set_rxnfc,
2808 };
2809 
2810 static const struct net_device_ops mtk_netdev_ops = {
2811 	.ndo_init		= mtk_init,
2812 	.ndo_uninit		= mtk_uninit,
2813 	.ndo_open		= mtk_open,
2814 	.ndo_stop		= mtk_stop,
2815 	.ndo_start_xmit		= mtk_start_xmit,
2816 	.ndo_set_mac_address	= mtk_set_mac_address,
2817 	.ndo_validate_addr	= eth_validate_addr,
2818 	.ndo_do_ioctl		= mtk_do_ioctl,
2819 	.ndo_tx_timeout		= mtk_tx_timeout,
2820 	.ndo_get_stats64        = mtk_get_stats64,
2821 	.ndo_fix_features	= mtk_fix_features,
2822 	.ndo_set_features	= mtk_set_features,
2823 #ifdef CONFIG_NET_POLL_CONTROLLER
2824 	.ndo_poll_controller	= mtk_poll_controller,
2825 #endif
2826 };
2827 
mtk_add_mac(struct mtk_eth * eth,struct device_node * np)2828 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2829 {
2830 	const __be32 *_id = of_get_property(np, "reg", NULL);
2831 	phy_interface_t phy_mode;
2832 	struct phylink *phylink;
2833 	struct mtk_mac *mac;
2834 	int id, err;
2835 
2836 	if (!_id) {
2837 		dev_err(eth->dev, "missing mac id\n");
2838 		return -EINVAL;
2839 	}
2840 
2841 	id = be32_to_cpup(_id);
2842 	if (id >= MTK_MAC_COUNT) {
2843 		dev_err(eth->dev, "%d is not a valid mac id\n", id);
2844 		return -EINVAL;
2845 	}
2846 
2847 	if (eth->netdev[id]) {
2848 		dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2849 		return -EINVAL;
2850 	}
2851 
2852 	eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2853 	if (!eth->netdev[id]) {
2854 		dev_err(eth->dev, "alloc_etherdev failed\n");
2855 		return -ENOMEM;
2856 	}
2857 	mac = netdev_priv(eth->netdev[id]);
2858 	eth->mac[id] = mac;
2859 	mac->id = id;
2860 	mac->hw = eth;
2861 	mac->of_node = np;
2862 
2863 	memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2864 	mac->hwlro_ip_cnt = 0;
2865 
2866 	mac->hw_stats = devm_kzalloc(eth->dev,
2867 				     sizeof(*mac->hw_stats),
2868 				     GFP_KERNEL);
2869 	if (!mac->hw_stats) {
2870 		dev_err(eth->dev, "failed to allocate counter memory\n");
2871 		err = -ENOMEM;
2872 		goto free_netdev;
2873 	}
2874 	spin_lock_init(&mac->hw_stats->stats_lock);
2875 	u64_stats_init(&mac->hw_stats->syncp);
2876 	mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2877 
2878 	/* phylink create */
2879 	err = of_get_phy_mode(np, &phy_mode);
2880 	if (err) {
2881 		dev_err(eth->dev, "incorrect phy-mode\n");
2882 		goto free_netdev;
2883 	}
2884 
2885 	/* mac config is not set */
2886 	mac->interface = PHY_INTERFACE_MODE_NA;
2887 	mac->mode = MLO_AN_PHY;
2888 	mac->speed = SPEED_UNKNOWN;
2889 
2890 	mac->phylink_config.dev = &eth->netdev[id]->dev;
2891 	mac->phylink_config.type = PHYLINK_NETDEV;
2892 
2893 	phylink = phylink_create(&mac->phylink_config,
2894 				 of_fwnode_handle(mac->of_node),
2895 				 phy_mode, &mtk_phylink_ops);
2896 	if (IS_ERR(phylink)) {
2897 		err = PTR_ERR(phylink);
2898 		goto free_netdev;
2899 	}
2900 
2901 	mac->phylink = phylink;
2902 
2903 	SET_NETDEV_DEV(eth->netdev[id], eth->dev);
2904 	eth->netdev[id]->watchdog_timeo = 5 * HZ;
2905 	eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2906 	eth->netdev[id]->base_addr = (unsigned long)eth->base;
2907 
2908 	eth->netdev[id]->hw_features = eth->soc->hw_features;
2909 	if (eth->hwlro)
2910 		eth->netdev[id]->hw_features |= NETIF_F_LRO;
2911 
2912 	eth->netdev[id]->vlan_features = eth->soc->hw_features &
2913 		~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2914 	eth->netdev[id]->features |= eth->soc->hw_features;
2915 	eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
2916 
2917 	eth->netdev[id]->irq = eth->irq[0];
2918 	eth->netdev[id]->dev.of_node = np;
2919 
2920 	eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
2921 
2922 	return 0;
2923 
2924 free_netdev:
2925 	free_netdev(eth->netdev[id]);
2926 	return err;
2927 }
2928 
mtk_probe(struct platform_device * pdev)2929 static int mtk_probe(struct platform_device *pdev)
2930 {
2931 	struct device_node *mac_np;
2932 	struct mtk_eth *eth;
2933 	int err, i;
2934 
2935 	eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2936 	if (!eth)
2937 		return -ENOMEM;
2938 
2939 	eth->soc = of_device_get_match_data(&pdev->dev);
2940 
2941 	eth->dev = &pdev->dev;
2942 	eth->base = devm_platform_ioremap_resource(pdev, 0);
2943 	if (IS_ERR(eth->base))
2944 		return PTR_ERR(eth->base);
2945 
2946 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
2947 		eth->tx_int_mask_reg = MTK_QDMA_INT_MASK;
2948 		eth->tx_int_status_reg = MTK_QDMA_INT_STATUS;
2949 	} else {
2950 		eth->tx_int_mask_reg = MTK_PDMA_INT_MASK;
2951 		eth->tx_int_status_reg = MTK_PDMA_INT_STATUS;
2952 	}
2953 
2954 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
2955 		eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA;
2956 		eth->ip_align = NET_IP_ALIGN;
2957 	} else {
2958 		eth->rx_dma_l4_valid = RX_DMA_L4_VALID;
2959 	}
2960 
2961 	spin_lock_init(&eth->page_lock);
2962 	spin_lock_init(&eth->tx_irq_lock);
2963 	spin_lock_init(&eth->rx_irq_lock);
2964 
2965 	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
2966 		eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2967 							      "mediatek,ethsys");
2968 		if (IS_ERR(eth->ethsys)) {
2969 			dev_err(&pdev->dev, "no ethsys regmap found\n");
2970 			return PTR_ERR(eth->ethsys);
2971 		}
2972 	}
2973 
2974 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) {
2975 		eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2976 							     "mediatek,infracfg");
2977 		if (IS_ERR(eth->infra)) {
2978 			dev_err(&pdev->dev, "no infracfg regmap found\n");
2979 			return PTR_ERR(eth->infra);
2980 		}
2981 	}
2982 
2983 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
2984 		eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
2985 					  GFP_KERNEL);
2986 		if (!eth->sgmii)
2987 			return -ENOMEM;
2988 
2989 		err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node,
2990 				     eth->soc->ana_rgc3);
2991 
2992 		if (err)
2993 			return err;
2994 	}
2995 
2996 	if (eth->soc->required_pctl) {
2997 		eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2998 							    "mediatek,pctl");
2999 		if (IS_ERR(eth->pctl)) {
3000 			dev_err(&pdev->dev, "no pctl regmap found\n");
3001 			return PTR_ERR(eth->pctl);
3002 		}
3003 	}
3004 
3005 	for (i = 0; i < 3; i++) {
3006 		if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
3007 			eth->irq[i] = eth->irq[0];
3008 		else
3009 			eth->irq[i] = platform_get_irq(pdev, i);
3010 		if (eth->irq[i] < 0) {
3011 			dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
3012 			return -ENXIO;
3013 		}
3014 	}
3015 	for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
3016 		eth->clks[i] = devm_clk_get(eth->dev,
3017 					    mtk_clks_source_name[i]);
3018 		if (IS_ERR(eth->clks[i])) {
3019 			if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
3020 				return -EPROBE_DEFER;
3021 			if (eth->soc->required_clks & BIT(i)) {
3022 				dev_err(&pdev->dev, "clock %s not found\n",
3023 					mtk_clks_source_name[i]);
3024 				return -EINVAL;
3025 			}
3026 			eth->clks[i] = NULL;
3027 		}
3028 	}
3029 
3030 	eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
3031 	INIT_WORK(&eth->pending_work, mtk_pending_work);
3032 
3033 	err = mtk_hw_init(eth);
3034 	if (err)
3035 		return err;
3036 
3037 	eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
3038 
3039 	for_each_child_of_node(pdev->dev.of_node, mac_np) {
3040 		if (!of_device_is_compatible(mac_np,
3041 					     "mediatek,eth-mac"))
3042 			continue;
3043 
3044 		if (!of_device_is_available(mac_np))
3045 			continue;
3046 
3047 		err = mtk_add_mac(eth, mac_np);
3048 		if (err) {
3049 			of_node_put(mac_np);
3050 			goto err_deinit_hw;
3051 		}
3052 	}
3053 
3054 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
3055 		err = devm_request_irq(eth->dev, eth->irq[0],
3056 				       mtk_handle_irq, 0,
3057 				       dev_name(eth->dev), eth);
3058 	} else {
3059 		err = devm_request_irq(eth->dev, eth->irq[1],
3060 				       mtk_handle_irq_tx, 0,
3061 				       dev_name(eth->dev), eth);
3062 		if (err)
3063 			goto err_free_dev;
3064 
3065 		err = devm_request_irq(eth->dev, eth->irq[2],
3066 				       mtk_handle_irq_rx, 0,
3067 				       dev_name(eth->dev), eth);
3068 	}
3069 	if (err)
3070 		goto err_free_dev;
3071 
3072 	/* No MT7628/88 support yet */
3073 	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
3074 		err = mtk_mdio_init(eth);
3075 		if (err)
3076 			goto err_free_dev;
3077 	}
3078 
3079 	for (i = 0; i < MTK_MAX_DEVS; i++) {
3080 		if (!eth->netdev[i])
3081 			continue;
3082 
3083 		err = register_netdev(eth->netdev[i]);
3084 		if (err) {
3085 			dev_err(eth->dev, "error bringing up device\n");
3086 			goto err_deinit_mdio;
3087 		} else
3088 			netif_info(eth, probe, eth->netdev[i],
3089 				   "mediatek frame engine at 0x%08lx, irq %d\n",
3090 				   eth->netdev[i]->base_addr, eth->irq[0]);
3091 	}
3092 
3093 	/* we run 2 devices on the same DMA ring so we need a dummy device
3094 	 * for NAPI to work
3095 	 */
3096 	init_dummy_netdev(&eth->dummy_dev);
3097 	netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
3098 		       MTK_NAPI_WEIGHT);
3099 	netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
3100 		       MTK_NAPI_WEIGHT);
3101 
3102 	platform_set_drvdata(pdev, eth);
3103 
3104 	return 0;
3105 
3106 err_deinit_mdio:
3107 	mtk_mdio_cleanup(eth);
3108 err_free_dev:
3109 	mtk_free_dev(eth);
3110 err_deinit_hw:
3111 	mtk_hw_deinit(eth);
3112 
3113 	return err;
3114 }
3115 
mtk_remove(struct platform_device * pdev)3116 static int mtk_remove(struct platform_device *pdev)
3117 {
3118 	struct mtk_eth *eth = platform_get_drvdata(pdev);
3119 	struct mtk_mac *mac;
3120 	int i;
3121 
3122 	/* stop all devices to make sure that dma is properly shut down */
3123 	for (i = 0; i < MTK_MAC_COUNT; i++) {
3124 		if (!eth->netdev[i])
3125 			continue;
3126 		mtk_stop(eth->netdev[i]);
3127 		mac = netdev_priv(eth->netdev[i]);
3128 		phylink_disconnect_phy(mac->phylink);
3129 	}
3130 
3131 	mtk_hw_deinit(eth);
3132 
3133 	netif_napi_del(&eth->tx_napi);
3134 	netif_napi_del(&eth->rx_napi);
3135 	mtk_cleanup(eth);
3136 	mtk_mdio_cleanup(eth);
3137 
3138 	return 0;
3139 }
3140 
3141 static const struct mtk_soc_data mt2701_data = {
3142 	.caps = MT7623_CAPS | MTK_HWLRO,
3143 	.hw_features = MTK_HW_FEATURES,
3144 	.required_clks = MT7623_CLKS_BITMAP,
3145 	.required_pctl = true,
3146 };
3147 
3148 static const struct mtk_soc_data mt7621_data = {
3149 	.caps = MT7621_CAPS,
3150 	.hw_features = MTK_HW_FEATURES,
3151 	.required_clks = MT7621_CLKS_BITMAP,
3152 	.required_pctl = false,
3153 };
3154 
3155 static const struct mtk_soc_data mt7622_data = {
3156 	.ana_rgc3 = 0x2028,
3157 	.caps = MT7622_CAPS | MTK_HWLRO,
3158 	.hw_features = MTK_HW_FEATURES,
3159 	.required_clks = MT7622_CLKS_BITMAP,
3160 	.required_pctl = false,
3161 };
3162 
3163 static const struct mtk_soc_data mt7623_data = {
3164 	.caps = MT7623_CAPS | MTK_HWLRO,
3165 	.hw_features = MTK_HW_FEATURES,
3166 	.required_clks = MT7623_CLKS_BITMAP,
3167 	.required_pctl = true,
3168 };
3169 
3170 static const struct mtk_soc_data mt7629_data = {
3171 	.ana_rgc3 = 0x128,
3172 	.caps = MT7629_CAPS | MTK_HWLRO,
3173 	.hw_features = MTK_HW_FEATURES,
3174 	.required_clks = MT7629_CLKS_BITMAP,
3175 	.required_pctl = false,
3176 };
3177 
3178 static const struct mtk_soc_data rt5350_data = {
3179 	.caps = MT7628_CAPS,
3180 	.hw_features = MTK_HW_FEATURES_MT7628,
3181 	.required_clks = MT7628_CLKS_BITMAP,
3182 	.required_pctl = false,
3183 };
3184 
3185 const struct of_device_id of_mtk_match[] = {
3186 	{ .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
3187 	{ .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
3188 	{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
3189 	{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
3190 	{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
3191 	{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
3192 	{},
3193 };
3194 MODULE_DEVICE_TABLE(of, of_mtk_match);
3195 
3196 static struct platform_driver mtk_driver = {
3197 	.probe = mtk_probe,
3198 	.remove = mtk_remove,
3199 	.driver = {
3200 		.name = "mtk_soc_eth",
3201 		.of_match_table = of_mtk_match,
3202 	},
3203 };
3204 
3205 module_platform_driver(mtk_driver);
3206 
3207 MODULE_LICENSE("GPL");
3208 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
3209 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
3210