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1 /*
2  * Copyright 2010 Christoph Bumiller
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
28 #include "util/format_srgb.h"
29 
30 #include "tgsi/tgsi_parse.h"
31 #include "compiler/nir/nir.h"
32 
33 #include "nv50/nv50_stateobj.h"
34 #include "nv50/nv50_context.h"
35 #include "nv50/nv50_query_hw.h"
36 
37 #include "nv50/nv50_3d.xml.h"
38 #include "nv50/g80_texture.xml.h"
39 
40 #include "nouveau_gldefs.h"
41 
42 /* Caveats:
43  *  ! pipe_sampler_state.normalized_coords is ignored - rectangle textures will
44  *     use non-normalized coordinates, everything else won't
45  *    (The relevant bit is in the TIC entry and not the TSC entry.)
46  *
47  *  ! pipe_sampler_state.seamless_cube_map is ignored - seamless filtering is
48  *     always activated on NVA0 +
49  *    (Give me the global bit, otherwise it's not worth the CPU work.)
50  *
51  *  ! pipe_sampler_state.border_color is not swizzled according to the texture
52  *     swizzle in pipe_sampler_view
53  *    (This will be ugly with indirect independent texture/sampler access,
54  *     we'd have to emulate the logic in the shader. GL doesn't have that,
55  *     D3D doesn't have swizzle, if we knew what we were implementing we'd be
56  *     good.)
57  *
58  *  ! pipe_rasterizer_state.line_last_pixel is ignored - it is never drawn
59  *
60  *  ! pipe_rasterizer_state.flatshade_first also applies to QUADS
61  *    (There's a GL query for that, forcing an exception is just ridiculous.)
62  *
63  *  ! pipe_rasterizer_state.sprite_coord_enable is masked with 0xff on NVC0
64  *    (The hardware only has 8 slots meant for TexCoord and we have to assign
65  *     in advance to maintain elegant separate shader objects.)
66  */
67 
68 static inline uint32_t
nv50_colormask(unsigned mask)69 nv50_colormask(unsigned mask)
70 {
71    uint32_t ret = 0;
72 
73    if (mask & PIPE_MASK_R)
74       ret |= 0x0001;
75    if (mask & PIPE_MASK_G)
76       ret |= 0x0010;
77    if (mask & PIPE_MASK_B)
78       ret |= 0x0100;
79    if (mask & PIPE_MASK_A)
80       ret |= 0x1000;
81 
82    return ret;
83 }
84 
85 #define NV50_BLEND_FACTOR_CASE(a, b) \
86    case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
87 
88 static inline uint32_t
nv50_blend_fac(unsigned factor)89 nv50_blend_fac(unsigned factor)
90 {
91    switch (factor) {
92    NV50_BLEND_FACTOR_CASE(ONE, ONE);
93    NV50_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
94    NV50_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
95    NV50_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
96    NV50_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
97    NV50_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
98    NV50_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
99    NV50_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
100    NV50_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
101    NV50_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
102    NV50_BLEND_FACTOR_CASE(ZERO, ZERO);
103    NV50_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
104    NV50_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
105    NV50_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
106    NV50_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
107    NV50_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
108    NV50_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
109    NV50_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
110    NV50_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
111    default:
112       return NV50_BLEND_FACTOR_ZERO;
113    }
114 }
115 
116 static void *
nv50_blend_state_create(struct pipe_context * pipe,const struct pipe_blend_state * cso)117 nv50_blend_state_create(struct pipe_context *pipe,
118                         const struct pipe_blend_state *cso)
119 {
120    struct nv50_blend_stateobj *so = CALLOC_STRUCT(nv50_blend_stateobj);
121    int i;
122    bool emit_common_func = cso->rt[0].blend_enable;
123    uint32_t ms;
124 
125    if (nv50_context(pipe)->screen->tesla->oclass >= NVA3_3D_CLASS) {
126       SB_BEGIN_3D(so, BLEND_INDEPENDENT, 1);
127       SB_DATA    (so, cso->independent_blend_enable);
128    }
129 
130    so->pipe = *cso;
131 
132    SB_BEGIN_3D(so, COLOR_MASK_COMMON, 1);
133    SB_DATA    (so, !cso->independent_blend_enable);
134 
135    SB_BEGIN_3D(so, BLEND_ENABLE_COMMON, 1);
136    SB_DATA    (so, !cso->independent_blend_enable);
137 
138    if (cso->independent_blend_enable) {
139       SB_BEGIN_3D(so, BLEND_ENABLE(0), 8);
140       for (i = 0; i < 8; ++i) {
141          SB_DATA(so, cso->rt[i].blend_enable);
142          if (cso->rt[i].blend_enable)
143             emit_common_func = true;
144       }
145 
146       if (nv50_context(pipe)->screen->tesla->oclass >= NVA3_3D_CLASS) {
147          emit_common_func = false;
148 
149          for (i = 0; i < 8; ++i) {
150             if (!cso->rt[i].blend_enable)
151                continue;
152             SB_BEGIN_3D_(so, NVA3_3D_IBLEND_EQUATION_RGB(i), 6);
153             SB_DATA     (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
154             SB_DATA     (so, nv50_blend_fac(cso->rt[i].rgb_src_factor));
155             SB_DATA     (so, nv50_blend_fac(cso->rt[i].rgb_dst_factor));
156             SB_DATA     (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
157             SB_DATA     (so, nv50_blend_fac(cso->rt[i].alpha_src_factor));
158             SB_DATA     (so, nv50_blend_fac(cso->rt[i].alpha_dst_factor));
159          }
160       }
161    } else {
162       SB_BEGIN_3D(so, BLEND_ENABLE(0), 1);
163       SB_DATA    (so, cso->rt[0].blend_enable);
164    }
165 
166    if (emit_common_func) {
167       SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
168       SB_DATA    (so, nvgl_blend_eqn(cso->rt[0].rgb_func));
169       SB_DATA    (so, nv50_blend_fac(cso->rt[0].rgb_src_factor));
170       SB_DATA    (so, nv50_blend_fac(cso->rt[0].rgb_dst_factor));
171       SB_DATA    (so, nvgl_blend_eqn(cso->rt[0].alpha_func));
172       SB_DATA    (so, nv50_blend_fac(cso->rt[0].alpha_src_factor));
173       SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
174       SB_DATA    (so, nv50_blend_fac(cso->rt[0].alpha_dst_factor));
175    }
176 
177    if (cso->logicop_enable) {
178       SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
179       SB_DATA    (so, 1);
180       SB_DATA    (so, nvgl_logicop_func(cso->logicop_func));
181    } else {
182       SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 1);
183       SB_DATA    (so, 0);
184    }
185 
186    if (cso->independent_blend_enable) {
187       SB_BEGIN_3D(so, COLOR_MASK(0), 8);
188       for (i = 0; i < 8; ++i)
189          SB_DATA(so, nv50_colormask(cso->rt[i].colormask));
190    } else {
191       SB_BEGIN_3D(so, COLOR_MASK(0), 1);
192       SB_DATA    (so, nv50_colormask(cso->rt[0].colormask));
193    }
194 
195    ms = 0;
196    if (cso->alpha_to_coverage)
197       ms |= NV50_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
198    if (cso->alpha_to_one)
199       ms |= NV50_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
200 
201    SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
202    SB_DATA    (so, ms);
203 
204    assert(so->size <= ARRAY_SIZE(so->state));
205    return so;
206 }
207 
208 static void
nv50_blend_state_bind(struct pipe_context * pipe,void * hwcso)209 nv50_blend_state_bind(struct pipe_context *pipe, void *hwcso)
210 {
211    struct nv50_context *nv50 = nv50_context(pipe);
212 
213    nv50->blend = hwcso;
214    nv50->dirty_3d |= NV50_NEW_3D_BLEND;
215 }
216 
217 static void
nv50_blend_state_delete(struct pipe_context * pipe,void * hwcso)218 nv50_blend_state_delete(struct pipe_context *pipe, void *hwcso)
219 {
220    FREE(hwcso);
221 }
222 
223 /* NOTE: ignoring line_last_pixel */
224 static void *
nv50_rasterizer_state_create(struct pipe_context * pipe,const struct pipe_rasterizer_state * cso)225 nv50_rasterizer_state_create(struct pipe_context *pipe,
226                              const struct pipe_rasterizer_state *cso)
227 {
228    struct nv50_rasterizer_stateobj *so;
229    uint32_t reg;
230 
231    so = CALLOC_STRUCT(nv50_rasterizer_stateobj);
232    if (!so)
233       return NULL;
234    so->pipe = *cso;
235 
236 #ifndef NV50_SCISSORS_CLIPPING
237    for (int i = 0; i < NV50_MAX_VIEWPORTS; i++) {
238       SB_BEGIN_3D(so, SCISSOR_ENABLE(i), 1);
239       SB_DATA    (so, cso->scissor);
240    }
241 #endif
242 
243    SB_BEGIN_3D(so, SHADE_MODEL, 1);
244    SB_DATA    (so, cso->flatshade ? NV50_3D_SHADE_MODEL_FLAT :
245                                     NV50_3D_SHADE_MODEL_SMOOTH);
246    SB_BEGIN_3D(so, PROVOKING_VERTEX_LAST, 1);
247    SB_DATA    (so, !cso->flatshade_first);
248    SB_BEGIN_3D(so, VERTEX_TWO_SIDE_ENABLE, 1);
249    SB_DATA    (so, cso->light_twoside);
250 
251    SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
252    SB_DATA    (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
253 
254    SB_BEGIN_3D(so, MULTISAMPLE_ENABLE, 1);
255    SB_DATA    (so, cso->multisample);
256 
257    SB_BEGIN_3D(so, LINE_WIDTH, 1);
258    SB_DATA    (so, fui(cso->line_width));
259    SB_BEGIN_3D(so, LINE_SMOOTH_ENABLE, 1);
260    SB_DATA    (so, cso->line_smooth);
261 
262    SB_BEGIN_3D(so, LINE_STIPPLE_ENABLE, 1);
263    if (cso->line_stipple_enable) {
264       SB_DATA    (so, 1);
265       SB_BEGIN_3D(so, LINE_STIPPLE, 1);
266       SB_DATA    (so, (cso->line_stipple_pattern << 8) |
267                   cso->line_stipple_factor);
268    } else {
269       SB_DATA    (so, 0);
270    }
271 
272    if (!cso->point_size_per_vertex) {
273       SB_BEGIN_3D(so, POINT_SIZE, 1);
274       SB_DATA    (so, fui(cso->point_size));
275    }
276    SB_BEGIN_3D(so, POINT_SPRITE_ENABLE, 1);
277    SB_DATA    (so, cso->point_quad_rasterization);
278    SB_BEGIN_3D(so, POINT_SMOOTH_ENABLE, 1);
279    SB_DATA    (so, cso->point_smooth);
280 
281    SB_BEGIN_3D(so, POLYGON_MODE_FRONT, 3);
282    SB_DATA    (so, nvgl_polygon_mode(cso->fill_front));
283    SB_DATA    (so, nvgl_polygon_mode(cso->fill_back));
284    SB_DATA    (so, cso->poly_smooth);
285 
286    SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
287    SB_DATA    (so, cso->cull_face != PIPE_FACE_NONE);
288    SB_DATA    (so, cso->front_ccw ? NV50_3D_FRONT_FACE_CCW :
289                                     NV50_3D_FRONT_FACE_CW);
290    switch (cso->cull_face) {
291    case PIPE_FACE_FRONT_AND_BACK:
292       SB_DATA(so, NV50_3D_CULL_FACE_FRONT_AND_BACK);
293       break;
294    case PIPE_FACE_FRONT:
295       SB_DATA(so, NV50_3D_CULL_FACE_FRONT);
296       break;
297    case PIPE_FACE_BACK:
298    default:
299      SB_DATA(so, NV50_3D_CULL_FACE_BACK);
300      break;
301    }
302 
303    SB_BEGIN_3D(so, POLYGON_STIPPLE_ENABLE, 1);
304    SB_DATA    (so, cso->poly_stipple_enable);
305    SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
306    SB_DATA    (so, cso->offset_point);
307    SB_DATA    (so, cso->offset_line);
308    SB_DATA    (so, cso->offset_tri);
309 
310    if (cso->offset_point || cso->offset_line || cso->offset_tri) {
311       SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
312       SB_DATA    (so, fui(cso->offset_scale));
313       SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
314       SB_DATA    (so, fui(cso->offset_units * 2.0f));
315       SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
316       SB_DATA    (so, fui(cso->offset_clamp));
317    }
318 
319    if (cso->depth_clip_near) {
320       reg = 0;
321    } else {
322       reg =
323          NV50_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
324          NV50_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
325          NV50_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK1;
326    }
327 #ifndef NV50_SCISSORS_CLIPPING
328    reg |=
329       NV50_3D_VIEW_VOLUME_CLIP_CTRL_UNK7 |
330       NV50_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK1;
331 #endif
332    SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
333    SB_DATA    (so, reg);
334 
335    SB_BEGIN_3D(so, DEPTH_CLIP_NEGATIVE_Z, 1);
336    SB_DATA    (so, cso->clip_halfz);
337 
338    SB_BEGIN_3D(so, PIXEL_CENTER_INTEGER, 1);
339    SB_DATA    (so, !cso->half_pixel_center);
340 
341    assert(so->size <= ARRAY_SIZE(so->state));
342    return (void *)so;
343 }
344 
345 static void
nv50_rasterizer_state_bind(struct pipe_context * pipe,void * hwcso)346 nv50_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
347 {
348    struct nv50_context *nv50 = nv50_context(pipe);
349 
350    nv50->rast = hwcso;
351    nv50->dirty_3d |= NV50_NEW_3D_RASTERIZER;
352 }
353 
354 static void
nv50_rasterizer_state_delete(struct pipe_context * pipe,void * hwcso)355 nv50_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
356 {
357    FREE(hwcso);
358 }
359 
360 static void *
nv50_zsa_state_create(struct pipe_context * pipe,const struct pipe_depth_stencil_alpha_state * cso)361 nv50_zsa_state_create(struct pipe_context *pipe,
362                       const struct pipe_depth_stencil_alpha_state *cso)
363 {
364    struct nv50_zsa_stateobj *so = CALLOC_STRUCT(nv50_zsa_stateobj);
365 
366    so->pipe = *cso;
367 
368    SB_BEGIN_3D(so, DEPTH_WRITE_ENABLE, 1);
369    SB_DATA    (so, cso->depth_writemask);
370    SB_BEGIN_3D(so, DEPTH_TEST_ENABLE, 1);
371    if (cso->depth_enabled) {
372       SB_DATA    (so, 1);
373       SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
374       SB_DATA    (so, nvgl_comparison_op(cso->depth_func));
375    } else {
376       SB_DATA    (so, 0);
377    }
378 
379    SB_BEGIN_3D(so, DEPTH_BOUNDS_EN, 1);
380    if (cso->depth_bounds_test) {
381       SB_DATA    (so, 1);
382       SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
383       SB_DATA    (so, fui(cso->depth_bounds_min));
384       SB_DATA    (so, fui(cso->depth_bounds_max));
385    } else {
386       SB_DATA    (so, 0);
387    }
388 
389    if (cso->stencil[0].enabled) {
390       SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
391       SB_DATA    (so, 1);
392       SB_DATA    (so, nvgl_stencil_op(cso->stencil[0].fail_op));
393       SB_DATA    (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
394       SB_DATA    (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
395       SB_DATA    (so, nvgl_comparison_op(cso->stencil[0].func));
396       SB_BEGIN_3D(so, STENCIL_FRONT_MASK, 2);
397       SB_DATA    (so, cso->stencil[0].writemask);
398       SB_DATA    (so, cso->stencil[0].valuemask);
399    } else {
400       SB_BEGIN_3D(so, STENCIL_ENABLE, 1);
401       SB_DATA    (so, 0);
402    }
403 
404    if (cso->stencil[1].enabled) {
405       assert(cso->stencil[0].enabled);
406       SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
407       SB_DATA    (so, 1);
408       SB_DATA    (so, nvgl_stencil_op(cso->stencil[1].fail_op));
409       SB_DATA    (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
410       SB_DATA    (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
411       SB_DATA    (so, nvgl_comparison_op(cso->stencil[1].func));
412       SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
413       SB_DATA    (so, cso->stencil[1].writemask);
414       SB_DATA    (so, cso->stencil[1].valuemask);
415    } else {
416       SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 1);
417       SB_DATA    (so, 0);
418    }
419 
420    SB_BEGIN_3D(so, ALPHA_TEST_ENABLE, 1);
421    if (cso->alpha_enabled) {
422       SB_DATA    (so, 1);
423       SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
424       SB_DATA    (so, fui(cso->alpha_ref_value));
425       SB_DATA    (so, nvgl_comparison_op(cso->alpha_func));
426    } else {
427       SB_DATA    (so, 0);
428    }
429 
430    SB_BEGIN_3D(so, CB_ADDR, 1);
431    SB_DATA    (so, NV50_CB_AUX_ALPHATEST_OFFSET << (8 - 2) | NV50_CB_AUX);
432    SB_BEGIN_3D(so, CB_DATA(0), 1);
433    SB_DATA    (so, fui(cso->alpha_ref_value));
434 
435    assert(so->size <= ARRAY_SIZE(so->state));
436    return (void *)so;
437 }
438 
439 static void
nv50_zsa_state_bind(struct pipe_context * pipe,void * hwcso)440 nv50_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
441 {
442    struct nv50_context *nv50 = nv50_context(pipe);
443 
444    nv50->zsa = hwcso;
445    nv50->dirty_3d |= NV50_NEW_3D_ZSA;
446 }
447 
448 static void
nv50_zsa_state_delete(struct pipe_context * pipe,void * hwcso)449 nv50_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
450 {
451    FREE(hwcso);
452 }
453 
454 /* ====================== SAMPLERS AND TEXTURES ================================
455  */
456 
457 static inline unsigned
nv50_tsc_wrap_mode(unsigned wrap)458 nv50_tsc_wrap_mode(unsigned wrap)
459 {
460    switch (wrap) {
461    case PIPE_TEX_WRAP_REPEAT:
462       return G80_TSC_WRAP_WRAP;
463    case PIPE_TEX_WRAP_MIRROR_REPEAT:
464       return G80_TSC_WRAP_MIRROR;
465    case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
466       return G80_TSC_WRAP_CLAMP_TO_EDGE;
467    case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
468       return G80_TSC_WRAP_BORDER;
469    case PIPE_TEX_WRAP_CLAMP:
470       return G80_TSC_WRAP_CLAMP_OGL;
471    case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
472       return G80_TSC_WRAP_MIRROR_ONCE_CLAMP_TO_EDGE;
473    case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
474       return G80_TSC_WRAP_MIRROR_ONCE_BORDER;
475    case PIPE_TEX_WRAP_MIRROR_CLAMP:
476       return G80_TSC_WRAP_MIRROR_ONCE_CLAMP_OGL;
477    default:
478        NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
479        return G80_TSC_WRAP_WRAP;
480    }
481 }
482 
483 void *
nv50_sampler_state_create(struct pipe_context * pipe,const struct pipe_sampler_state * cso)484 nv50_sampler_state_create(struct pipe_context *pipe,
485                           const struct pipe_sampler_state *cso)
486 {
487    struct nv50_tsc_entry *so = MALLOC_STRUCT(nv50_tsc_entry);
488    float f[2];
489 
490    so->id = -1;
491 
492    so->tsc[0] = (0x00026000 |
493                  (nv50_tsc_wrap_mode(cso->wrap_s) << 0) |
494                  (nv50_tsc_wrap_mode(cso->wrap_t) << 3) |
495                  (nv50_tsc_wrap_mode(cso->wrap_r) << 6));
496 
497    switch (cso->mag_img_filter) {
498    case PIPE_TEX_FILTER_LINEAR:
499       so->tsc[1] = G80_TSC_1_MAG_FILTER_LINEAR;
500       break;
501    case PIPE_TEX_FILTER_NEAREST:
502    default:
503       so->tsc[1] = G80_TSC_1_MAG_FILTER_NEAREST;
504       break;
505    }
506 
507    switch (cso->min_img_filter) {
508    case PIPE_TEX_FILTER_LINEAR:
509       so->tsc[1] |= G80_TSC_1_MIN_FILTER_LINEAR;
510       break;
511    case PIPE_TEX_FILTER_NEAREST:
512    default:
513       so->tsc[1] |= G80_TSC_1_MIN_FILTER_NEAREST;
514       break;
515    }
516 
517    switch (cso->min_mip_filter) {
518    case PIPE_TEX_MIPFILTER_LINEAR:
519       so->tsc[1] |= G80_TSC_1_MIP_FILTER_LINEAR;
520       break;
521    case PIPE_TEX_MIPFILTER_NEAREST:
522       so->tsc[1] |= G80_TSC_1_MIP_FILTER_NEAREST;
523       break;
524    case PIPE_TEX_MIPFILTER_NONE:
525    default:
526       so->tsc[1] |= G80_TSC_1_MIP_FILTER_NONE;
527       break;
528    }
529 
530    if (nouveau_screen(pipe->screen)->class_3d >= NVE4_3D_CLASS) {
531       if (cso->seamless_cube_map)
532          so->tsc[1] |= GK104_TSC_1_CUBEMAP_INTERFACE_FILTERING;
533       if (!cso->normalized_coords)
534          so->tsc[1] |= GK104_TSC_1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS;
535    } else {
536       so->seamless_cube_map = cso->seamless_cube_map;
537    }
538 
539    if (nouveau_screen(pipe->screen)->class_3d >= GM200_3D_CLASS) {
540       if (cso->reduction_mode == PIPE_TEX_REDUCTION_MIN)
541          so->tsc[1] |= GM204_TSC_1_REDUCTION_MODE_MIN;
542       if (cso->reduction_mode == PIPE_TEX_REDUCTION_MAX)
543          so->tsc[1] |= GM204_TSC_1_REDUCTION_MODE_MAX;
544    }
545 
546    if (cso->max_anisotropy >= 16)
547       so->tsc[0] |= (7 << 20);
548    else
549    if (cso->max_anisotropy >= 12)
550       so->tsc[0] |= (6 << 20);
551    else {
552       so->tsc[0] |= (cso->max_anisotropy >> 1) << 20;
553 
554       if (cso->max_anisotropy >= 4)
555          so->tsc[1] |= 6 << G80_TSC_1_TRILIN_OPT__SHIFT;
556       else
557       if (cso->max_anisotropy >= 2)
558          so->tsc[1] |= 4 << G80_TSC_1_TRILIN_OPT__SHIFT;
559    }
560 
561    if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
562       /* NOTE: must be deactivated for non-shadow textures */
563       so->tsc[0] |= (1 << 9);
564       so->tsc[0] |= (nvgl_comparison_op(cso->compare_func) & 0x7) << 10;
565    }
566 
567    f[0] = CLAMP(cso->lod_bias, -16.0f, 15.0f);
568    so->tsc[1] |= ((int)(f[0] * 256.0f) & 0x1fff) << 12;
569 
570    f[0] = CLAMP(cso->min_lod, 0.0f, 15.0f);
571    f[1] = CLAMP(cso->max_lod, 0.0f, 15.0f);
572    so->tsc[2] =
573       (((int)(f[1] * 256.0f) & 0xfff) << 12) | ((int)(f[0] * 256.0f) & 0xfff);
574 
575    so->tsc[2] |=
576       util_format_linear_float_to_srgb_8unorm(cso->border_color.f[0]) << 24;
577    so->tsc[3] =
578       util_format_linear_float_to_srgb_8unorm(cso->border_color.f[1]) << 12;
579    so->tsc[3] |=
580       util_format_linear_float_to_srgb_8unorm(cso->border_color.f[2]) << 20;
581 
582    so->tsc[4] = fui(cso->border_color.f[0]);
583    so->tsc[5] = fui(cso->border_color.f[1]);
584    so->tsc[6] = fui(cso->border_color.f[2]);
585    so->tsc[7] = fui(cso->border_color.f[3]);
586 
587    return (void *)so;
588 }
589 
590 static void
nv50_sampler_state_delete(struct pipe_context * pipe,void * hwcso)591 nv50_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
592 {
593    unsigned s, i;
594 
595    for (s = 0; s < NV50_MAX_SHADER_STAGES; ++s) {
596       assert(nv50_context(pipe)->num_samplers[s] <= PIPE_MAX_SAMPLERS);
597       for (i = 0; i < nv50_context(pipe)->num_samplers[s]; ++i)
598          if (nv50_context(pipe)->samplers[s][i] == hwcso)
599             nv50_context(pipe)->samplers[s][i] = NULL;
600    }
601 
602    nv50_screen_tsc_free(nv50_context(pipe)->screen, nv50_tsc_entry(hwcso));
603 
604    FREE(hwcso);
605 }
606 
607 static inline void
nv50_stage_sampler_states_bind(struct nv50_context * nv50,int s,unsigned nr,void ** hwcsos)608 nv50_stage_sampler_states_bind(struct nv50_context *nv50, int s,
609                                unsigned nr, void **hwcsos)
610 {
611    unsigned highest_found = 0;
612    unsigned i;
613 
614    assert(nr <= PIPE_MAX_SAMPLERS);
615    for (i = 0; i < nr; ++i) {
616       struct nv50_tsc_entry *hwcso = hwcsos ? nv50_tsc_entry(hwcsos[i]) : NULL;
617       struct nv50_tsc_entry *old = nv50->samplers[s][i];
618 
619       if (hwcso)
620          highest_found = i;
621 
622       nv50->samplers[s][i] = hwcso;
623       if (old)
624          nv50_screen_tsc_unlock(nv50->screen, old);
625    }
626    assert(nv50->num_samplers[s] <= PIPE_MAX_SAMPLERS);
627    if (nr >= nv50->num_samplers[s])
628       nv50->num_samplers[s] = highest_found + 1;
629 }
630 
631 static void
nv50_bind_sampler_states(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned num_samplers,void ** samplers)632 nv50_bind_sampler_states(struct pipe_context *pipe,
633                          enum pipe_shader_type shader, unsigned start,
634                          unsigned num_samplers, void **samplers)
635 {
636    unsigned s = nv50_context_shader_stage(shader);
637 
638    assert(start == 0);
639    nv50_stage_sampler_states_bind(nv50_context(pipe), s, num_samplers,
640                                   samplers);
641 
642    if (unlikely(s == NV50_SHADER_STAGE_COMPUTE))
643       nv50_context(pipe)->dirty_cp |= NV50_NEW_CP_SAMPLERS;
644    else
645       nv50_context(pipe)->dirty_3d |= NV50_NEW_3D_SAMPLERS;
646 }
647 
648 
649 
650 /* NOTE: only called when not referenced anywhere, won't be bound */
651 static void
nv50_sampler_view_destroy(struct pipe_context * pipe,struct pipe_sampler_view * view)652 nv50_sampler_view_destroy(struct pipe_context *pipe,
653                           struct pipe_sampler_view *view)
654 {
655    pipe_resource_reference(&view->texture, NULL);
656 
657    nv50_screen_tic_free(nv50_context(pipe)->screen, nv50_tic_entry(view));
658 
659    FREE(nv50_tic_entry(view));
660 }
661 
662 static inline void
nv50_stage_set_sampler_views(struct nv50_context * nv50,int s,unsigned nr,bool take_ownership,struct pipe_sampler_view ** views)663 nv50_stage_set_sampler_views(struct nv50_context *nv50, int s,
664                              unsigned nr, bool take_ownership,
665                              struct pipe_sampler_view **views)
666 {
667    unsigned i;
668 
669    assert(nr <= PIPE_MAX_SAMPLERS);
670    for (i = 0; i < nr; ++i) {
671       struct pipe_sampler_view *view = views ? views[i] : NULL;
672       struct nv50_tic_entry *old = nv50_tic_entry(nv50->textures[s][i]);
673       if (old)
674          nv50_screen_tic_unlock(nv50->screen, old);
675 
676       if (view && view->texture) {
677          struct pipe_resource *res = view->texture;
678          if (res->target == PIPE_BUFFER &&
679              (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
680             nv50->textures_coherent[s] |= 1 << i;
681          else
682             nv50->textures_coherent[s] &= ~(1 << i);
683       } else {
684          nv50->textures_coherent[s] &= ~(1 << i);
685       }
686 
687       if (take_ownership) {
688          pipe_sampler_view_reference(&nv50->textures[s][i], NULL);
689          nv50->textures[s][i] = view;
690       } else {
691          pipe_sampler_view_reference(&nv50->textures[s][i], view);
692       }
693    }
694 
695    assert(nv50->num_textures[s] <= PIPE_MAX_SAMPLERS);
696    for (i = nr; i < nv50->num_textures[s]; ++i) {
697       struct nv50_tic_entry *old = nv50_tic_entry(nv50->textures[s][i]);
698       if (!old)
699          continue;
700       nv50_screen_tic_unlock(nv50->screen, old);
701 
702       pipe_sampler_view_reference(&nv50->textures[s][i], NULL);
703    }
704 
705    nv50->num_textures[s] = nr;
706 }
707 
708 static void
nv50_set_sampler_views(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned nr,unsigned unbind_num_trailing_slots,bool take_ownership,struct pipe_sampler_view ** views)709 nv50_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
710                        unsigned start, unsigned nr,
711                        unsigned unbind_num_trailing_slots,
712                        bool take_ownership,
713                        struct pipe_sampler_view **views)
714 {
715    struct nv50_context *nv50 = nv50_context(pipe);
716    unsigned s = nv50_context_shader_stage(shader);
717 
718    assert(start == 0);
719    nv50_stage_set_sampler_views(nv50, s, nr, take_ownership, views);
720 
721    if (unlikely(s == NV50_SHADER_STAGE_COMPUTE)) {
722       nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_TEXTURES);
723 
724       nv50->dirty_cp |= NV50_NEW_CP_TEXTURES;
725    } else {
726       nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_TEXTURES);
727 
728       nv50->dirty_3d |= NV50_NEW_3D_TEXTURES;
729    }
730 }
731 
732 
733 
734 /* ============================= SHADERS =======================================
735  */
736 
737 static void *
nv50_sp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso,enum pipe_shader_type type)738 nv50_sp_state_create(struct pipe_context *pipe,
739                      const struct pipe_shader_state *cso,
740                      enum pipe_shader_type type)
741 {
742    struct nv50_program *prog;
743 
744    prog = CALLOC_STRUCT(nv50_program);
745    if (!prog)
746       return NULL;
747 
748    prog->type = type;
749    prog->pipe.type = cso->type;
750 
751    switch (cso->type) {
752    case PIPE_SHADER_IR_TGSI:
753       prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
754       break;
755    case PIPE_SHADER_IR_NIR:
756       prog->pipe.ir.nir = cso->ir.nir;
757       break;
758    default:
759       assert(!"unsupported IR!");
760       free(prog);
761       return NULL;
762    }
763 
764    if (cso->stream_output.num_outputs)
765       prog->pipe.stream_output = cso->stream_output;
766 
767    prog->translated = nv50_program_translate(
768          prog, nv50_context(pipe)->screen->base.device->chipset,
769          &nouveau_context(pipe)->debug);
770 
771    return (void *)prog;
772 }
773 
774 static void
nv50_sp_state_delete(struct pipe_context * pipe,void * hwcso)775 nv50_sp_state_delete(struct pipe_context *pipe, void *hwcso)
776 {
777    struct nv50_program *prog = (struct nv50_program *)hwcso;
778 
779    nv50_program_destroy(nv50_context(pipe), prog);
780 
781    if (prog->pipe.type == PIPE_SHADER_IR_TGSI)
782       FREE((void *)prog->pipe.tokens);
783    else if (prog->pipe.type == PIPE_SHADER_IR_NIR)
784       ralloc_free(prog->pipe.ir.nir);
785    FREE(prog);
786 }
787 
788 static void *
nv50_vp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)789 nv50_vp_state_create(struct pipe_context *pipe,
790                      const struct pipe_shader_state *cso)
791 {
792    return nv50_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
793 }
794 
795 static void
nv50_vp_state_bind(struct pipe_context * pipe,void * hwcso)796 nv50_vp_state_bind(struct pipe_context *pipe, void *hwcso)
797 {
798     struct nv50_context *nv50 = nv50_context(pipe);
799 
800     nv50->vertprog = hwcso;
801     nv50->dirty_3d |= NV50_NEW_3D_VERTPROG;
802 }
803 
804 static void *
nv50_fp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)805 nv50_fp_state_create(struct pipe_context *pipe,
806                      const struct pipe_shader_state *cso)
807 {
808    return nv50_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
809 }
810 
811 static void
nv50_fp_state_bind(struct pipe_context * pipe,void * hwcso)812 nv50_fp_state_bind(struct pipe_context *pipe, void *hwcso)
813 {
814     struct nv50_context *nv50 = nv50_context(pipe);
815 
816     nv50->fragprog = hwcso;
817     nv50->dirty_3d |= NV50_NEW_3D_FRAGPROG;
818 }
819 
820 static void *
nv50_gp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)821 nv50_gp_state_create(struct pipe_context *pipe,
822                      const struct pipe_shader_state *cso)
823 {
824    return nv50_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
825 }
826 
827 static void
nv50_gp_state_bind(struct pipe_context * pipe,void * hwcso)828 nv50_gp_state_bind(struct pipe_context *pipe, void *hwcso)
829 {
830     struct nv50_context *nv50 = nv50_context(pipe);
831 
832     nv50->gmtyprog = hwcso;
833     nv50->dirty_3d |= NV50_NEW_3D_GMTYPROG;
834 }
835 
836 static void *
nv50_cp_state_create(struct pipe_context * pipe,const struct pipe_compute_state * cso)837 nv50_cp_state_create(struct pipe_context *pipe,
838                      const struct pipe_compute_state *cso)
839 {
840    struct nv50_program *prog;
841 
842    prog = CALLOC_STRUCT(nv50_program);
843    if (!prog)
844       return NULL;
845    prog->type = PIPE_SHADER_COMPUTE;
846    prog->pipe.type = cso->ir_type;
847 
848    switch(cso->ir_type) {
849    case PIPE_SHADER_IR_TGSI:
850       prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
851       break;
852    case PIPE_SHADER_IR_NIR:
853       prog->pipe.ir.nir = (nir_shader *)cso->prog;
854       break;
855    default:
856       assert(!"unsupported IR!");
857       free(prog);
858       return NULL;
859    }
860 
861    prog->cp.smem_size = cso->req_local_mem;
862    prog->cp.lmem_size = cso->req_private_mem;
863    prog->parm_size = cso->req_input_mem;
864 
865    return (void *)prog;
866 }
867 
868 static void
nv50_cp_state_bind(struct pipe_context * pipe,void * hwcso)869 nv50_cp_state_bind(struct pipe_context *pipe, void *hwcso)
870 {
871    struct nv50_context *nv50 = nv50_context(pipe);
872 
873    nv50->compprog = hwcso;
874    nv50->dirty_cp |= NV50_NEW_CP_PROGRAM;
875 }
876 
877 static void
nv50_set_constant_buffer(struct pipe_context * pipe,enum pipe_shader_type shader,uint index,bool take_ownership,const struct pipe_constant_buffer * cb)878 nv50_set_constant_buffer(struct pipe_context *pipe,
879                          enum pipe_shader_type shader, uint index,
880                          bool take_ownership,
881                          const struct pipe_constant_buffer *cb)
882 {
883    struct nv50_context *nv50 = nv50_context(pipe);
884    struct pipe_resource *res = cb ? cb->buffer : NULL;
885    const unsigned s = nv50_context_shader_stage(shader);
886    const unsigned i = index;
887 
888    if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
889       if (nv50->constbuf[s][i].user)
890          nv50->constbuf[s][i].u.buf = NULL;
891       else
892       if (nv50->constbuf[s][i].u.buf)
893          nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_CB(i));
894 
895       nv50->dirty_cp |= NV50_NEW_CP_CONSTBUF;
896    } else {
897       if (nv50->constbuf[s][i].user)
898          nv50->constbuf[s][i].u.buf = NULL;
899       else
900       if (nv50->constbuf[s][i].u.buf)
901          nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_CB(s, i));
902 
903       nv50->dirty_3d |= NV50_NEW_3D_CONSTBUF;
904    }
905    nv50->constbuf_dirty[s] |= 1 << i;
906 
907    if (nv50->constbuf[s][i].u.buf)
908       nv04_resource(nv50->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
909 
910    if (take_ownership) {
911       pipe_resource_reference(&nv50->constbuf[s][i].u.buf, NULL);
912       nv50->constbuf[s][i].u.buf = res;
913    } else {
914       pipe_resource_reference(&nv50->constbuf[s][i].u.buf, res);
915    }
916 
917    nv50->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
918    if (nv50->constbuf[s][i].user) {
919       nv50->constbuf[s][i].u.data = cb->user_buffer;
920       nv50->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
921       nv50->constbuf_valid[s] |= 1 << i;
922       nv50->constbuf_coherent[s] &= ~(1 << i);
923    } else
924    if (cb) {
925       nv50->constbuf[s][i].offset = cb->buffer_offset;
926       nv50->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
927       nv50->constbuf_valid[s] |= 1 << i;
928       if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
929          nv50->constbuf_coherent[s] |= 1 << i;
930       else
931          nv50->constbuf_coherent[s] &= ~(1 << i);
932    }
933    else {
934       nv50->constbuf_valid[s] &= ~(1 << i);
935       nv50->constbuf_coherent[s] &= ~(1 << i);
936    }
937 }
938 
939 /* =============================================================================
940  */
941 
942 static void
nv50_set_blend_color(struct pipe_context * pipe,const struct pipe_blend_color * bcol)943 nv50_set_blend_color(struct pipe_context *pipe,
944                      const struct pipe_blend_color *bcol)
945 {
946    struct nv50_context *nv50 = nv50_context(pipe);
947 
948    nv50->blend_colour = *bcol;
949    nv50->dirty_3d |= NV50_NEW_3D_BLEND_COLOUR;
950 }
951 
952 static void
nv50_set_stencil_ref(struct pipe_context * pipe,const struct pipe_stencil_ref sr)953 nv50_set_stencil_ref(struct pipe_context *pipe,
954                      const struct pipe_stencil_ref sr)
955 {
956    struct nv50_context *nv50 = nv50_context(pipe);
957 
958    nv50->stencil_ref = sr;
959    nv50->dirty_3d |= NV50_NEW_3D_STENCIL_REF;
960 }
961 
962 static void
nv50_set_clip_state(struct pipe_context * pipe,const struct pipe_clip_state * clip)963 nv50_set_clip_state(struct pipe_context *pipe,
964                     const struct pipe_clip_state *clip)
965 {
966    struct nv50_context *nv50 = nv50_context(pipe);
967 
968    memcpy(nv50->clip.ucp, clip->ucp, sizeof(clip->ucp));
969 
970    nv50->dirty_3d |= NV50_NEW_3D_CLIP;
971 }
972 
973 static void
nv50_set_sample_mask(struct pipe_context * pipe,unsigned sample_mask)974 nv50_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
975 {
976    struct nv50_context *nv50 = nv50_context(pipe);
977 
978    nv50->sample_mask = sample_mask;
979    nv50->dirty_3d |= NV50_NEW_3D_SAMPLE_MASK;
980 }
981 
982 static void
nv50_set_min_samples(struct pipe_context * pipe,unsigned min_samples)983 nv50_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
984 {
985    struct nv50_context *nv50 = nv50_context(pipe);
986 
987    if (nv50->min_samples != min_samples) {
988       nv50->min_samples = min_samples;
989       nv50->dirty_3d |= NV50_NEW_3D_MIN_SAMPLES;
990    }
991 }
992 
993 static void
nv50_set_framebuffer_state(struct pipe_context * pipe,const struct pipe_framebuffer_state * fb)994 nv50_set_framebuffer_state(struct pipe_context *pipe,
995                            const struct pipe_framebuffer_state *fb)
996 {
997    struct nv50_context *nv50 = nv50_context(pipe);
998 
999    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_FB);
1000 
1001    util_copy_framebuffer_state(&nv50->framebuffer, fb);
1002 
1003    nv50->dirty_3d |= NV50_NEW_3D_FRAMEBUFFER | NV50_NEW_3D_TEXTURES;
1004 }
1005 
1006 static void
nv50_set_polygon_stipple(struct pipe_context * pipe,const struct pipe_poly_stipple * stipple)1007 nv50_set_polygon_stipple(struct pipe_context *pipe,
1008                          const struct pipe_poly_stipple *stipple)
1009 {
1010    struct nv50_context *nv50 = nv50_context(pipe);
1011 
1012    nv50->stipple = *stipple;
1013    nv50->dirty_3d |= NV50_NEW_3D_STIPPLE;
1014 }
1015 
1016 static void
nv50_set_scissor_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_scissors,const struct pipe_scissor_state * scissor)1017 nv50_set_scissor_states(struct pipe_context *pipe,
1018                         unsigned start_slot,
1019                         unsigned num_scissors,
1020                         const struct pipe_scissor_state *scissor)
1021 {
1022    struct nv50_context *nv50 = nv50_context(pipe);
1023    int i;
1024 
1025    assert(start_slot + num_scissors <= NV50_MAX_VIEWPORTS);
1026    for (i = 0; i < num_scissors; i++) {
1027       if (!memcmp(&nv50->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
1028          continue;
1029       nv50->scissors[start_slot + i] = scissor[i];
1030       nv50->scissors_dirty |= 1 << (start_slot + i);
1031       nv50->dirty_3d |= NV50_NEW_3D_SCISSOR;
1032    }
1033 }
1034 
1035 static void
nv50_set_viewport_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_viewports,const struct pipe_viewport_state * vpt)1036 nv50_set_viewport_states(struct pipe_context *pipe,
1037                          unsigned start_slot,
1038                          unsigned num_viewports,
1039                          const struct pipe_viewport_state *vpt)
1040 {
1041    struct nv50_context *nv50 = nv50_context(pipe);
1042    int i;
1043 
1044    assert(start_slot + num_viewports <= NV50_MAX_VIEWPORTS);
1045    for (i = 0; i < num_viewports; i++) {
1046       if (!memcmp(&nv50->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
1047          continue;
1048       nv50->viewports[start_slot + i] = vpt[i];
1049       nv50->viewports_dirty |= 1 << (start_slot + i);
1050       nv50->dirty_3d |= NV50_NEW_3D_VIEWPORT;
1051    }
1052 }
1053 
1054 static void
nv50_set_window_rectangles(struct pipe_context * pipe,bool include,unsigned num_rectangles,const struct pipe_scissor_state * rectangles)1055 nv50_set_window_rectangles(struct pipe_context *pipe,
1056                            bool include,
1057                            unsigned num_rectangles,
1058                            const struct pipe_scissor_state *rectangles)
1059 {
1060    struct nv50_context *nv50 = nv50_context(pipe);
1061 
1062    nv50->window_rect.inclusive = include;
1063    nv50->window_rect.rects = MIN2(num_rectangles, NV50_MAX_WINDOW_RECTANGLES);
1064    memcpy(nv50->window_rect.rect, rectangles,
1065           sizeof(struct pipe_scissor_state) * nv50->window_rect.rects);
1066 
1067    nv50->dirty_3d |= NV50_NEW_3D_WINDOW_RECTS;
1068 }
1069 
1070 static void
nv50_set_vertex_buffers(struct pipe_context * pipe,unsigned start_slot,unsigned count,unsigned unbind_num_trailing_slots,bool take_ownership,const struct pipe_vertex_buffer * vb)1071 nv50_set_vertex_buffers(struct pipe_context *pipe,
1072                         unsigned start_slot, unsigned count,
1073                         unsigned unbind_num_trailing_slots,
1074                         bool take_ownership,
1075                         const struct pipe_vertex_buffer *vb)
1076 {
1077    struct nv50_context *nv50 = nv50_context(pipe);
1078    unsigned i;
1079 
1080    nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_VERTEX);
1081    nv50->dirty_3d |= NV50_NEW_3D_ARRAYS;
1082 
1083    util_set_vertex_buffers_count(nv50->vtxbuf, &nv50->num_vtxbufs, vb,
1084                                  start_slot, count,
1085                                  unbind_num_trailing_slots,
1086                                  take_ownership);
1087 
1088    unsigned clear_mask = ~u_bit_consecutive(start_slot + count, unbind_num_trailing_slots);
1089    nv50->vbo_user &= clear_mask;
1090    nv50->vbo_constant &= clear_mask;
1091    nv50->vtxbufs_coherent &= clear_mask;
1092 
1093    if (!vb) {
1094       clear_mask = ~u_bit_consecutive(start_slot, count);
1095       nv50->vbo_user &= clear_mask;
1096       nv50->vbo_constant &= clear_mask;
1097       nv50->vtxbufs_coherent &= clear_mask;
1098       return;
1099    }
1100 
1101    for (i = 0; i < count; ++i) {
1102       unsigned dst_index = start_slot + i;
1103 
1104       if (vb[i].is_user_buffer) {
1105          nv50->vbo_user |= 1 << dst_index;
1106          if (!vb[i].stride)
1107             nv50->vbo_constant |= 1 << dst_index;
1108          else
1109             nv50->vbo_constant &= ~(1 << dst_index);
1110          nv50->vtxbufs_coherent &= ~(1 << dst_index);
1111       } else {
1112          nv50->vbo_user &= ~(1 << dst_index);
1113          nv50->vbo_constant &= ~(1 << dst_index);
1114 
1115          if (vb[i].buffer.resource &&
1116              vb[i].buffer.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1117             nv50->vtxbufs_coherent |= (1 << dst_index);
1118          else
1119             nv50->vtxbufs_coherent &= ~(1 << dst_index);
1120       }
1121    }
1122 }
1123 
1124 static void
nv50_vertex_state_bind(struct pipe_context * pipe,void * hwcso)1125 nv50_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1126 {
1127    struct nv50_context *nv50 = nv50_context(pipe);
1128 
1129    nv50->vertex = hwcso;
1130    nv50->dirty_3d |= NV50_NEW_3D_VERTEX;
1131 }
1132 
1133 static struct pipe_stream_output_target *
nv50_so_target_create(struct pipe_context * pipe,struct pipe_resource * res,unsigned offset,unsigned size)1134 nv50_so_target_create(struct pipe_context *pipe,
1135                       struct pipe_resource *res,
1136                       unsigned offset, unsigned size)
1137 {
1138    struct nv04_resource *buf = (struct nv04_resource *)res;
1139    struct nv50_so_target *targ = MALLOC_STRUCT(nv50_so_target);
1140    if (!targ)
1141       return NULL;
1142 
1143    if (nouveau_context(pipe)->screen->class_3d >= NVA0_3D_CLASS) {
1144       targ->pq = pipe->create_query(pipe,
1145                                     NVA0_HW_QUERY_STREAM_OUTPUT_BUFFER_OFFSET, 0);
1146       if (!targ->pq) {
1147          FREE(targ);
1148          return NULL;
1149       }
1150    } else {
1151       targ->pq = NULL;
1152    }
1153    targ->clean = true;
1154 
1155    targ->pipe.buffer_size = size;
1156    targ->pipe.buffer_offset = offset;
1157    targ->pipe.context = pipe;
1158    targ->pipe.buffer = NULL;
1159    pipe_resource_reference(&targ->pipe.buffer, res);
1160    pipe_reference_init(&targ->pipe.reference, 1);
1161 
1162    assert(buf->base.target == PIPE_BUFFER);
1163    util_range_add(&buf->base, &buf->valid_buffer_range, offset, offset + size);
1164 
1165    return &targ->pipe;
1166 }
1167 
1168 static void
nva0_so_target_save_offset(struct pipe_context * pipe,struct pipe_stream_output_target * ptarg,unsigned index,bool serialize)1169 nva0_so_target_save_offset(struct pipe_context *pipe,
1170                            struct pipe_stream_output_target *ptarg,
1171                            unsigned index, bool serialize)
1172 {
1173    struct nv50_so_target *targ = nv50_so_target(ptarg);
1174 
1175    if (serialize) {
1176       struct nouveau_pushbuf *push = nv50_context(pipe)->base.pushbuf;
1177       PUSH_SPACE(push, 2);
1178       BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
1179       PUSH_DATA (push, 0);
1180    }
1181 
1182    nv50_query(targ->pq)->index = index;
1183    pipe->end_query(pipe, targ->pq);
1184 }
1185 
1186 static void
nv50_so_target_destroy(struct pipe_context * pipe,struct pipe_stream_output_target * ptarg)1187 nv50_so_target_destroy(struct pipe_context *pipe,
1188                        struct pipe_stream_output_target *ptarg)
1189 {
1190    struct nv50_so_target *targ = nv50_so_target(ptarg);
1191    if (targ->pq)
1192       pipe->destroy_query(pipe, targ->pq);
1193    pipe_resource_reference(&targ->pipe.buffer, NULL);
1194    FREE(targ);
1195 }
1196 
1197 static void
nv50_set_stream_output_targets(struct pipe_context * pipe,unsigned num_targets,struct pipe_stream_output_target ** targets,const unsigned * offsets)1198 nv50_set_stream_output_targets(struct pipe_context *pipe,
1199                                unsigned num_targets,
1200                                struct pipe_stream_output_target **targets,
1201                                const unsigned *offsets)
1202 {
1203    struct nv50_context *nv50 = nv50_context(pipe);
1204    unsigned i;
1205    bool serialize = true;
1206    const bool can_resume = nv50->screen->base.class_3d >= NVA0_3D_CLASS;
1207 
1208    assert(num_targets <= 4);
1209 
1210    for (i = 0; i < num_targets; ++i) {
1211       const bool changed = nv50->so_target[i] != targets[i];
1212       const bool append = (offsets[i] == (unsigned)-1);
1213       if (!changed && append)
1214          continue;
1215       nv50->so_targets_dirty |= 1 << i;
1216 
1217       if (can_resume && changed && nv50->so_target[i]) {
1218          nva0_so_target_save_offset(pipe, nv50->so_target[i], i, serialize);
1219          serialize = false;
1220       }
1221 
1222       if (targets[i] && !append) {
1223          nv50_so_target(targets[i])->clean = true;
1224          nv50->so_used[i] = 0;
1225       }
1226 
1227       pipe_so_target_reference(&nv50->so_target[i], targets[i]);
1228    }
1229    for (; i < nv50->num_so_targets; ++i) {
1230       if (can_resume && nv50->so_target[i]) {
1231          nva0_so_target_save_offset(pipe, nv50->so_target[i], i, serialize);
1232          serialize = false;
1233       }
1234       pipe_so_target_reference(&nv50->so_target[i], NULL);
1235       nv50->so_targets_dirty |= 1 << i;
1236    }
1237    nv50->num_so_targets = num_targets;
1238 
1239    if (nv50->so_targets_dirty) {
1240       nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_SO);
1241       nv50->dirty_3d |= NV50_NEW_3D_STRMOUT;
1242    }
1243 }
1244 
1245 static bool
nv50_bind_images_range(struct nv50_context * nv50,unsigned start,unsigned nr,const struct pipe_image_view * pimages)1246 nv50_bind_images_range(struct nv50_context *nv50,
1247                        unsigned start, unsigned nr,
1248                        const struct pipe_image_view *pimages)
1249 {
1250    const unsigned end = start + nr;
1251    unsigned mask = 0;
1252    unsigned i;
1253 
1254    if (pimages) {
1255       for (i = start; i < end; ++i) {
1256          struct pipe_image_view *img = &nv50->images[i];
1257          const unsigned p = i - start;
1258 
1259          if (img->resource == pimages[p].resource &&
1260              img->format == pimages[p].format &&
1261              img->access == pimages[p].access) {
1262             if (img->resource == NULL)
1263                continue;
1264             if (img->resource->target == PIPE_BUFFER &&
1265                 img->u.buf.offset == pimages[p].u.buf.offset &&
1266                 img->u.buf.size == pimages[p].u.buf.size)
1267                continue;
1268             if (img->resource->target != PIPE_BUFFER &&
1269                 img->u.tex.first_layer == pimages[p].u.tex.first_layer &&
1270                 img->u.tex.last_layer == pimages[p].u.tex.last_layer &&
1271                 img->u.tex.level == pimages[p].u.tex.level)
1272                continue;
1273          }
1274 
1275          mask |= (1 << i);
1276          if (pimages[p].resource)
1277             nv50->images_valid |= (1 << i);
1278          else
1279             nv50->images_valid &= ~(1 << i);
1280 
1281          img->format = pimages[p].format;
1282          img->access = pimages[p].access;
1283          if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER)
1284             img->u.buf = pimages[p].u.buf;
1285          else
1286             img->u.tex = pimages[p].u.tex;
1287 
1288          pipe_resource_reference(
1289                &img->resource, pimages[p].resource);
1290       }
1291       if (!mask)
1292          return false;
1293    } else {
1294       mask = ((1 << nr) - 1) << start;
1295       if (!(nv50->images_valid & mask))
1296          return false;
1297       for (i = start; i < end; ++i) {
1298          pipe_resource_reference(&nv50->images[i].resource, NULL);
1299       }
1300       nv50->images_valid &= ~mask;
1301    }
1302    nv50->images_dirty |= mask;
1303 
1304    nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_SUF);
1305 
1306    return true;
1307 }
1308 
1309 static void
nv50_set_shader_images(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned nr,unsigned unbind_num_trailing_slots,const struct pipe_image_view * images)1310 nv50_set_shader_images(struct pipe_context *pipe,
1311                        enum pipe_shader_type shader,
1312                        unsigned start, unsigned nr,
1313                        unsigned unbind_num_trailing_slots,
1314                        const struct pipe_image_view *images)
1315 {
1316    const unsigned s = nv50_context_shader_stage(shader);
1317 
1318    if (s != NV50_SHADER_STAGE_COMPUTE)
1319       return;
1320 
1321    nv50_bind_images_range(nv50_context(pipe), start + nr,
1322                           unbind_num_trailing_slots, NULL);
1323 
1324    if (!nv50_bind_images_range(nv50_context(pipe), start, nr, images))
1325       return;
1326 
1327    nv50_context(pipe)->dirty_cp |= NV50_NEW_CP_SURFACES;
1328 }
1329 
1330 static void
nv50_set_compute_resources(struct pipe_context * pipe,unsigned start,unsigned nr,struct pipe_surface ** resources)1331 nv50_set_compute_resources(struct pipe_context *pipe,
1332                            unsigned start, unsigned nr,
1333                            struct pipe_surface **resources)
1334 {
1335    /* TODO: bind surfaces */
1336 }
1337 
1338 static bool
nv50_bind_buffers_range(struct nv50_context * nv50,unsigned start,unsigned nr,const struct pipe_shader_buffer * pbuffers)1339 nv50_bind_buffers_range(struct nv50_context *nv50,
1340                         unsigned start, unsigned nr,
1341                         const struct pipe_shader_buffer *pbuffers)
1342 {
1343    const unsigned end = start + nr;
1344    unsigned mask = 0;
1345    unsigned i;
1346 
1347    if (pbuffers) {
1348       for (i = start; i < end; ++i) {
1349          struct pipe_shader_buffer *buf = &nv50->buffers[i];
1350          const unsigned p = i - start;
1351          if (buf->buffer == pbuffers[p].buffer &&
1352              buf->buffer_offset == pbuffers[p].buffer_offset &&
1353              buf->buffer_size == pbuffers[p].buffer_size)
1354             continue;
1355 
1356          mask |= (1 << i);
1357          if (pbuffers[p].buffer)
1358             nv50->buffers_valid |= (1 << i);
1359          else
1360             nv50->buffers_valid &= ~(1 << i);
1361          buf->buffer_offset = pbuffers[p].buffer_offset;
1362          buf->buffer_size = pbuffers[p].buffer_size;
1363          pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1364       }
1365       if (!mask)
1366          return false;
1367    } else {
1368       mask = ((1 << nr) - 1) << start;
1369       if (!(nv50->buffers_valid & mask))
1370          return false;
1371       for (i = start; i < end; ++i)
1372          pipe_resource_reference(&nv50->buffers[i].buffer, NULL);
1373       nv50->buffers_valid &= ~mask;
1374    }
1375    nv50->buffers_dirty |= mask;
1376 
1377    nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_BUF);
1378 
1379    return true;
1380 }
1381 
1382 static void
nv50_set_shader_buffers(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned nr,const struct pipe_shader_buffer * buffers,unsigned writable_bitmask)1383 nv50_set_shader_buffers(struct pipe_context *pipe,
1384                         enum pipe_shader_type shader,
1385                         unsigned start, unsigned nr,
1386                         const struct pipe_shader_buffer *buffers,
1387                         unsigned writable_bitmask)
1388 {
1389    const unsigned s = nv50_context_shader_stage(shader);
1390 
1391    if (s != NV50_SHADER_STAGE_COMPUTE)
1392       return;
1393 
1394    if (!nv50_bind_buffers_range(nv50_context(pipe), start, nr, buffers))
1395       return;
1396 
1397    nv50_context(pipe)->dirty_cp |= NV50_NEW_CP_BUFFERS;
1398 }
1399 
1400 static inline void
nv50_set_global_handle(uint32_t * phandle,struct pipe_resource * res)1401 nv50_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1402 {
1403    struct nv04_resource *buf = nv04_resource(res);
1404    if (buf) {
1405       uint64_t limit = (buf->address + buf->base.width0) - 1;
1406       if (limit < (1ULL << 32)) {
1407          *phandle = (uint32_t)buf->address;
1408       } else {
1409          NOUVEAU_ERR("Cannot map into TGSI_RESOURCE_GLOBAL: "
1410                      "resource not contained within 32-bit address space !\n");
1411          *phandle = 0;
1412       }
1413    } else {
1414       *phandle = 0;
1415    }
1416 }
1417 
1418 static void
nv50_set_global_bindings(struct pipe_context * pipe,unsigned start,unsigned nr,struct pipe_resource ** resources,uint32_t ** handles)1419 nv50_set_global_bindings(struct pipe_context *pipe,
1420                          unsigned start, unsigned nr,
1421                          struct pipe_resource **resources,
1422                          uint32_t **handles)
1423 {
1424    struct nv50_context *nv50 = nv50_context(pipe);
1425    struct pipe_resource **ptr;
1426    unsigned i;
1427    const unsigned end = start + nr;
1428 
1429    if (nv50->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1430       const unsigned old_size = nv50->global_residents.size;
1431       if (util_dynarray_resize(&nv50->global_residents, struct pipe_resource *, end)) {
1432          memset((uint8_t *)nv50->global_residents.data + old_size, 0,
1433                 nv50->global_residents.size - old_size);
1434       } else {
1435          NOUVEAU_ERR("Could not resize global residents array\n");
1436          return;
1437       }
1438    }
1439 
1440    if (resources) {
1441       ptr = util_dynarray_element(
1442          &nv50->global_residents, struct pipe_resource *, start);
1443       for (i = 0; i < nr; ++i) {
1444          pipe_resource_reference(&ptr[i], resources[i]);
1445          nv50_set_global_handle(handles[i], resources[i]);
1446       }
1447    } else {
1448       ptr = util_dynarray_element(
1449          &nv50->global_residents, struct pipe_resource *, start);
1450       for (i = 0; i < nr; ++i)
1451          pipe_resource_reference(&ptr[i], NULL);
1452    }
1453 
1454    nouveau_bufctx_reset(nv50->bufctx_cp, NV50_BIND_CP_GLOBAL);
1455 
1456    nv50->dirty_cp |= NV50_NEW_CP_GLOBALS;
1457 }
1458 
1459 void
nv50_init_state_functions(struct nv50_context * nv50)1460 nv50_init_state_functions(struct nv50_context *nv50)
1461 {
1462    struct pipe_context *pipe = &nv50->base.pipe;
1463 
1464    pipe->create_blend_state = nv50_blend_state_create;
1465    pipe->bind_blend_state = nv50_blend_state_bind;
1466    pipe->delete_blend_state = nv50_blend_state_delete;
1467 
1468    pipe->create_rasterizer_state = nv50_rasterizer_state_create;
1469    pipe->bind_rasterizer_state = nv50_rasterizer_state_bind;
1470    pipe->delete_rasterizer_state = nv50_rasterizer_state_delete;
1471 
1472    pipe->create_depth_stencil_alpha_state = nv50_zsa_state_create;
1473    pipe->bind_depth_stencil_alpha_state = nv50_zsa_state_bind;
1474    pipe->delete_depth_stencil_alpha_state = nv50_zsa_state_delete;
1475 
1476    pipe->create_sampler_state = nv50_sampler_state_create;
1477    pipe->delete_sampler_state = nv50_sampler_state_delete;
1478    pipe->bind_sampler_states   = nv50_bind_sampler_states;
1479 
1480    pipe->create_sampler_view = nv50_create_sampler_view;
1481    pipe->sampler_view_destroy = nv50_sampler_view_destroy;
1482    pipe->set_sampler_views = nv50_set_sampler_views;
1483 
1484    pipe->create_vs_state = nv50_vp_state_create;
1485    pipe->create_fs_state = nv50_fp_state_create;
1486    pipe->create_gs_state = nv50_gp_state_create;
1487    pipe->create_compute_state = nv50_cp_state_create;
1488    pipe->bind_vs_state = nv50_vp_state_bind;
1489    pipe->bind_fs_state = nv50_fp_state_bind;
1490    pipe->bind_gs_state = nv50_gp_state_bind;
1491    pipe->bind_compute_state = nv50_cp_state_bind;
1492    pipe->delete_vs_state = nv50_sp_state_delete;
1493    pipe->delete_fs_state = nv50_sp_state_delete;
1494    pipe->delete_gs_state = nv50_sp_state_delete;
1495    pipe->delete_compute_state = nv50_sp_state_delete;
1496 
1497    pipe->set_blend_color = nv50_set_blend_color;
1498    pipe->set_stencil_ref = nv50_set_stencil_ref;
1499    pipe->set_clip_state = nv50_set_clip_state;
1500    pipe->set_sample_mask = nv50_set_sample_mask;
1501    pipe->set_min_samples = nv50_set_min_samples;
1502    pipe->set_constant_buffer = nv50_set_constant_buffer;
1503    pipe->set_framebuffer_state = nv50_set_framebuffer_state;
1504    pipe->set_polygon_stipple = nv50_set_polygon_stipple;
1505    pipe->set_scissor_states = nv50_set_scissor_states;
1506    pipe->set_viewport_states = nv50_set_viewport_states;
1507    pipe->set_window_rectangles = nv50_set_window_rectangles;
1508 
1509    pipe->create_vertex_elements_state = nv50_vertex_state_create;
1510    pipe->delete_vertex_elements_state = nv50_vertex_state_delete;
1511    pipe->bind_vertex_elements_state = nv50_vertex_state_bind;
1512 
1513    pipe->set_vertex_buffers = nv50_set_vertex_buffers;
1514 
1515    pipe->create_stream_output_target = nv50_so_target_create;
1516    pipe->stream_output_target_destroy = nv50_so_target_destroy;
1517    pipe->set_stream_output_targets = nv50_set_stream_output_targets;
1518 
1519    pipe->set_global_binding = nv50_set_global_bindings;
1520    pipe->set_compute_resources = nv50_set_compute_resources;
1521    pipe->set_shader_images = nv50_set_shader_images;
1522    pipe->set_shader_buffers = nv50_set_shader_buffers;
1523 
1524    nv50->sample_mask = ~0;
1525    nv50->min_samples = 1;
1526 }
1527