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1 /*
2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
3 
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7 
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15 
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19 
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 
28 **************************************************************************/
29 
30 /*
31  * Authors:
32  *   Keith Whitwell <keithw@vmware.com>
33  */
34 
35 #include <stdbool.h>
36 #include "main/glheader.h"
37 #include "main/api_arrayelt.h"
38 #include "main/api_exec.h"
39 #include "main/context.h"
40 
41 #include "main/extensions.h"
42 #include "main/version.h"
43 #include "main/vtxfmt.h"
44 
45 #include "swrast/swrast.h"
46 #include "swrast_setup/swrast_setup.h"
47 #include "vbo/vbo.h"
48 
49 #include "tnl/tnl.h"
50 #include "tnl/t_pipeline.h"
51 
52 #include "drivers/common/driverfuncs.h"
53 
54 #include "r200_context.h"
55 #include "r200_ioctl.h"
56 #include "r200_state.h"
57 #include "r200_tex.h"
58 #include "r200_swtcl.h"
59 #include "r200_tcl.h"
60 #include "r200_vertprog.h"
61 #include "radeon_queryobj.h"
62 #include "r200_blit.h"
63 #include "radeon_fog.h"
64 
65 #include "radeon_span.h"
66 
67 #include "utils.h"
68 #include "util/driconf.h" /* for symbolic values of enum-type options */
69 #include "util/u_memory.h"
70 
71 /* Return various strings for glGetString().
72  */
r200GetString(struct gl_context * ctx,GLenum name)73 static const GLubyte *r200GetString( struct gl_context *ctx, GLenum name )
74 {
75    r200ContextPtr rmesa = R200_CONTEXT(ctx);
76    static char buffer[128];
77    unsigned   offset;
78    GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type == RADEON_CARD_PCI)? 0 :
79       rmesa->radeon.radeonScreen->AGPMode;
80 
81    switch ( name ) {
82    case GL_VENDOR:
83       return (GLubyte *)"Mesa Project";
84 
85    case GL_RENDERER:
86       offset = driGetRendererString( buffer, "R200", agp_mode );
87 
88       sprintf( & buffer[ offset ], " %sTCL",
89 	       !(rmesa->radeon.TclFallback & R200_TCL_FALLBACK_TCL_DISABLE)
90 	       ? "" : "NO-" );
91 
92       return (GLubyte *)buffer;
93 
94    default:
95       return NULL;
96    }
97 }
98 
99 
100 extern const struct tnl_pipeline_stage _r200_render_stage;
101 extern const struct tnl_pipeline_stage _r200_tcl_stage;
102 
103 static const struct tnl_pipeline_stage *r200_pipeline[] = {
104 
105    /* Try and go straight to t&l
106     */
107    &_r200_tcl_stage,
108 
109    /* Catch any t&l fallbacks
110     */
111    &_tnl_vertex_transform_stage,
112    &_tnl_normal_transform_stage,
113    &_tnl_lighting_stage,
114    &_tnl_fog_coordinate_stage,
115    &_tnl_texgen_stage,
116    &_tnl_texture_transform_stage,
117    &_tnl_point_attenuation_stage,
118    &_tnl_vertex_program_stage,
119    /* Try again to go to tcl?
120     *     - no good for asymmetric-twoside (do with multipass)
121     *     - no good for asymmetric-unfilled (do with multipass)
122     *     - good for material
123     *     - good for texgen
124     *     - need to manipulate a bit of state
125     *
126     * - worth it/not worth it?
127     */
128 
129    /* Else do them here.
130     */
131 /*    &_r200_render_stage,  */ /* FIXME: bugs with ut2003 */
132    &_tnl_render_stage,		/* FALLBACK:  */
133    NULL,
134 };
135 
136 
137 
138 /* Initialize the driver's misc functions.
139  */
r200InitDriverFuncs(struct dd_function_table * functions)140 static void r200InitDriverFuncs( struct dd_function_table *functions )
141 {
142     functions->GetString		= r200GetString;
143 }
144 
145 
r200_emit_query_finish(radeonContextPtr radeon)146 static void r200_emit_query_finish(radeonContextPtr radeon)
147 {
148    BATCH_LOCALS(radeon);
149    struct radeon_query_object *query = radeon->query.current;
150 
151    BEGIN_BATCH(4);
152    OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
153    OUT_BATCH_RELOC(query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
154    END_BATCH();
155    query->curr_offset += sizeof(uint32_t);
156    assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
157    query->emitted_begin = GL_FALSE;
158 }
159 
r200_init_vtbl(radeonContextPtr radeon)160 static void r200_init_vtbl(radeonContextPtr radeon)
161 {
162    radeon->vtbl.swtcl_flush = r200_swtcl_flush;
163    radeon->vtbl.fallback = r200Fallback;
164    radeon->vtbl.update_scissor = r200_vtbl_update_scissor;
165    radeon->vtbl.emit_query_finish = r200_emit_query_finish;
166    radeon->vtbl.check_blit = r200_check_blit;
167    radeon->vtbl.blit = r200_blit;
168    radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
169    radeon->vtbl.revalidate_all_buffers = r200ValidateBuffers;
170 }
171 
172 
173 /* Create the device specific rendering context.
174  */
r200CreateContext(gl_api api,const struct gl_config * glVisual,__DRIcontext * driContextPriv,const struct __DriverContextConfig * ctx_config,unsigned * error,void * sharedContextPrivate)175 GLboolean r200CreateContext( gl_api api,
176 			     const struct gl_config *glVisual,
177 			     __DRIcontext *driContextPriv,
178 			     const struct __DriverContextConfig *ctx_config,
179 			     unsigned *error,
180 			     void *sharedContextPrivate)
181 {
182    __DRIscreen *sPriv = driContextPriv->driScreenPriv;
183    radeonScreenPtr screen = (radeonScreenPtr)(sPriv->driverPrivate);
184    struct dd_function_table functions;
185    r200ContextPtr rmesa;
186    struct gl_context *ctx;
187    int i;
188    int tcl_mode;
189 
190    if (ctx_config->flags & ~(__DRI_CTX_FLAG_DEBUG | __DRI_CTX_FLAG_NO_ERROR)) {
191       *error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
192       return false;
193    }
194 
195    if (ctx_config->attribute_mask) {
196       *error = __DRI_CTX_ERROR_UNKNOWN_ATTRIBUTE;
197       return false;
198    }
199 
200    assert(driContextPriv);
201    assert(screen);
202 
203    /* Allocate the R200 context */
204    rmesa = align_calloc(sizeof(*rmesa), 16);
205    if ( !rmesa ) {
206       *error = __DRI_CTX_ERROR_NO_MEMORY;
207       return GL_FALSE;
208    }
209 
210    rmesa->radeon.radeonScreen = screen;
211    r200_init_vtbl(&rmesa->radeon);
212    /* init exp fog table data */
213    radeonInitStaticFogData();
214 
215    /* Parse configuration files.
216     * Do this here so that initialMaxAnisotropy is set before we create
217     * the default textures.
218     */
219    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
220 			screen->driScreen->myNum, "r200", NULL, NULL, NULL, 0, NULL, 0);
221    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
222 							"def_max_anisotropy");
223 
224    if (driQueryOptionb( &rmesa->radeon.optionCache, "hyperz"))
225       rmesa->using_hyperz = GL_TRUE;
226 
227    /* Init default driver functions then plug in our R200-specific functions
228     * (the texture functions are especially important)
229     */
230    _mesa_init_driver_functions(&functions);
231    _tnl_init_driver_draw_function(&functions);
232    r200InitDriverFuncs(&functions);
233    r200InitIoctlFuncs(&functions);
234    r200InitStateFuncs(&rmesa->radeon, &functions);
235    r200InitTextureFuncs(&rmesa->radeon, &functions);
236    r200InitShaderFuncs(&functions);
237    radeonInitQueryObjFunctions(&functions);
238 
239    if (!radeonInitContext(&rmesa->radeon, api, &functions,
240 			  glVisual, driContextPriv,
241 			  sharedContextPrivate)) {
242      align_free(rmesa);
243      *error = __DRI_CTX_ERROR_NO_MEMORY;
244      return GL_FALSE;
245    }
246 
247    rmesa->radeon.swtcl.RenderIndex = ~0;
248    rmesa->radeon.hw.all_dirty = 1;
249 
250    ctx = &rmesa->radeon.glCtx;
251 
252    driContextSetFlags(ctx, ctx_config->flags);
253 
254    /* Initialize the software rasterizer and helper modules.
255     */
256    _swrast_CreateContext( ctx );
257    _vbo_CreateContext( ctx, false );
258    _tnl_CreateContext( ctx );
259    _swsetup_CreateContext( ctx );
260 
261    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
262 						 "texture_units");
263    ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits = ctx->Const.MaxTextureUnits;
264    ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits;
265 
266    ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits;
267 
268    ctx->Const.StripTextureBorder = GL_TRUE;
269 
270    /* FIXME: When no memory manager is available we should set this
271     * to some reasonable value based on texture memory pool size */
272    ctx->Const.MaxTextureSize = 2048;
273    ctx->Const.Max3DTextureLevels = 9;
274    ctx->Const.MaxCubeTextureLevels = 12;
275    ctx->Const.MaxTextureRectSize = 2048;
276    ctx->Const.MaxRenderbufferSize = 2048;
277 
278    ctx->Const.MaxTextureMaxAnisotropy = 16.0;
279 
280    /* No wide AA points.
281     */
282    ctx->Const.MinPointSize = 1.0;
283    ctx->Const.MinPointSizeAA = 1.0;
284    ctx->Const.MaxPointSizeAA = 1.0;
285    ctx->Const.PointSizeGranularity = 0.0625;
286    ctx->Const.MaxPointSize = 2047.0;
287 
288    /* mesa initialization problem - _mesa_init_point was already called */
289    ctx->Point.MaxSize = ctx->Const.MaxPointSize;
290 
291    ctx->Const.MinLineWidth = 1.0;
292    ctx->Const.MinLineWidthAA = 1.0;
293    ctx->Const.MaxLineWidth = 10.0;
294    ctx->Const.MaxLineWidthAA = 10.0;
295    ctx->Const.LineWidthGranularity = 0.0625;
296 
297    ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeInstructions = R200_VSF_MAX_INST;
298    ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeAttribs = 12;
299    ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeTemps = R200_VSF_MAX_TEMPS;
300    ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeParameters = R200_VSF_MAX_PARAM;
301    ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeAddressRegs = 1;
302 
303    ctx->Const.MaxDrawBuffers = 1;
304    ctx->Const.MaxColorAttachments = 1;
305 
306    ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].OptimizeForAOS = GL_TRUE;
307 
308    /* Install the customized pipeline:
309     */
310    _tnl_destroy_pipeline( ctx );
311    _tnl_install_pipeline( ctx, r200_pipeline );
312 
313    /* Try and keep materials and vertices separate:
314     */
315 /*    _tnl_isolate_materials( ctx, GL_TRUE ); */
316 
317 
318    /* Configure swrast and TNL to match hardware characteristics:
319     */
320    _swrast_allow_pixel_fog( ctx, GL_FALSE );
321    _swrast_allow_vertex_fog( ctx, GL_TRUE );
322    _tnl_allow_pixel_fog( ctx, GL_FALSE );
323    _tnl_allow_vertex_fog( ctx, GL_TRUE );
324 
325 
326    for ( i = 0 ; i < R200_MAX_TEXTURE_UNITS ; i++ ) {
327       _math_matrix_ctr( &rmesa->TexGenMatrix[i] );
328       _math_matrix_set_identity( &rmesa->TexGenMatrix[i] );
329    }
330    _math_matrix_ctr( &rmesa->tmpmat );
331    _math_matrix_set_identity( &rmesa->tmpmat );
332 
333    ctx->Extensions.ARB_occlusion_query = true;
334    ctx->Extensions.ARB_point_sprite = true;
335    ctx->Extensions.ARB_texture_border_clamp = true;
336    ctx->Extensions.ARB_texture_cube_map = true;
337    ctx->Extensions.ARB_texture_env_combine = true;
338    ctx->Extensions.ARB_texture_env_dot3 = true;
339    ctx->Extensions.ARB_texture_env_crossbar = true;
340    ctx->Extensions.ARB_texture_filter_anisotropic = true;
341    ctx->Extensions.ARB_texture_mirror_clamp_to_edge = true;
342    ctx->Extensions.ARB_vertex_program = true;
343    ctx->Extensions.ATI_fragment_shader = (ctx->Const.MaxTextureUnits == 6);
344    ctx->Extensions.ATI_texture_env_combine3 = true;
345    ctx->Extensions.ATI_texture_mirror_once = true;
346    ctx->Extensions.EXT_blend_color = true;
347    ctx->Extensions.EXT_blend_equation_separate = true;
348    ctx->Extensions.EXT_blend_func_separate = true;
349    ctx->Extensions.EXT_blend_minmax = true;
350    ctx->Extensions.EXT_gpu_program_parameters = true;
351    ctx->Extensions.EXT_point_parameters = true;
352    ctx->Extensions.EXT_texture_env_dot3 = true;
353    ctx->Extensions.EXT_texture_filter_anisotropic = true;
354    ctx->Extensions.EXT_texture_mirror_clamp = true;
355    ctx->Extensions.NV_fog_distance = true;
356    ctx->Extensions.NV_texture_rectangle = true;
357    ctx->Extensions.OES_EGL_image = true;
358 
359    if (!(rmesa->radeon.radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) {
360      /* yuv textures don't work with some chips - R200 / rv280 okay so far
361 	others get the bit ordering right but don't actually do YUV-RGB conversion */
362       ctx->Extensions.MESA_ycbcr_texture = true;
363    }
364    ctx->Extensions.EXT_texture_compression_s3tc = true;
365    ctx->Extensions.ANGLE_texture_compression_dxt = true;
366 
367 #if 0
368    r200InitDriverFuncs( ctx );
369    r200InitIoctlFuncs( ctx );
370    r200InitStateFuncs( ctx );
371    r200InitTextureFuncs( ctx );
372 #endif
373    /* plug in a few more device driver functions */
374    /* XXX these should really go right after _mesa_init_driver_functions() */
375    radeon_fbo_init(&rmesa->radeon);
376    radeonInitSpanFuncs( ctx );
377    r200InitTnlFuncs( ctx );
378    r200InitState( rmesa );
379    r200InitSwtcl( ctx );
380 
381    rmesa->prefer_gart_client_texturing =
382       (getenv("R200_GART_CLIENT_TEXTURES") != 0);
383 
384    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
385    if (getenv("R200_NO_RAST")) {
386       fprintf(stderr, "disabling 3D acceleration\n");
387       FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1);
388    }
389    else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") ||
390 	    !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
391       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
392 	 rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
393 	 fprintf(stderr, "Disabling HW TCL support\n");
394       }
395       TCL_FALLBACK(&rmesa->radeon.glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1);
396    }
397 
398    _mesa_override_extensions(ctx);
399    _mesa_compute_version(ctx);
400 
401    /* Exec table initialization requires the version to be computed */
402    _mesa_initialize_dispatch_tables(ctx);
403    _mesa_initialize_vbo_vtxfmt(ctx);
404 
405    *error = __DRI_CTX_ERROR_SUCCESS;
406    return GL_TRUE;
407 }
408 
409 
r200DestroyContext(__DRIcontext * driContextPriv)410 void r200DestroyContext( __DRIcontext *driContextPriv )
411 {
412 	radeonDestroyContext(driContextPriv);
413 }
414