1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include "radeon_vcn_enc.h"
29
30 #include "pipe/p_video_codec.h"
31 #include "radeon_video.h"
32 #include "radeonsi/si_pipe.h"
33 #include "util/u_memory.h"
34 #include "util/u_video.h"
35 #include "vl/vl_video_buffer.h"
36
37 #include <stdio.h>
38
39 static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
40
radeon_vcn_enc_get_param(struct radeon_encoder * enc,struct pipe_picture_desc * picture)41 static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
42 {
43 if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
44 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
45 enc->enc_pic.picture_type = pic->picture_type;
46 enc->enc_pic.frame_num = pic->frame_num;
47 enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
48 enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
49 enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
50 enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
51 enc->enc_pic.not_referenced = pic->not_referenced;
52 enc->enc_pic.is_idr = (pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR);
53 if (pic->pic_ctrl.enc_frame_cropping_flag) {
54 enc->enc_pic.crop_left = pic->pic_ctrl.enc_frame_crop_left_offset;
55 enc->enc_pic.crop_right = pic->pic_ctrl.enc_frame_crop_right_offset;
56 enc->enc_pic.crop_top = pic->pic_ctrl.enc_frame_crop_top_offset;
57 enc->enc_pic.crop_bottom = pic->pic_ctrl.enc_frame_crop_bottom_offset;
58 } else {
59 enc->enc_pic.crop_left = 0;
60 enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
61 enc->enc_pic.crop_top = 0;
62 enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
63 }
64 enc->enc_pic.num_temporal_layers = pic->num_temporal_layers ? pic->num_temporal_layers : 1;
65 enc->enc_pic.temporal_id = 0;
66 for (int i = 0; i < enc->enc_pic.num_temporal_layers; i++)
67 {
68 enc->enc_pic.rc_layer_init[i].target_bit_rate = pic->rate_ctrl[i].target_bitrate;
69 enc->enc_pic.rc_layer_init[i].peak_bit_rate = pic->rate_ctrl[i].peak_bitrate;
70 enc->enc_pic.rc_layer_init[i].frame_rate_num = pic->rate_ctrl[i].frame_rate_num;
71 enc->enc_pic.rc_layer_init[i].frame_rate_den = pic->rate_ctrl[i].frame_rate_den;
72 enc->enc_pic.rc_layer_init[i].vbv_buffer_size = pic->rate_ctrl[i].vbv_buffer_size;
73 enc->enc_pic.rc_layer_init[i].avg_target_bits_per_picture = pic->rate_ctrl[i].target_bits_picture;
74 enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_integer =
75 pic->rate_ctrl[i].peak_bits_picture_integer;
76 enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_fractional =
77 pic->rate_ctrl[i].peak_bits_picture_fraction;
78 }
79 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rate_ctrl[0].vbv_buf_lv;
80 enc->enc_pic.rc_per_pic.qp = pic->quant_i_frames;
81 enc->enc_pic.rc_per_pic.min_qp_app = 0;
82 enc->enc_pic.rc_per_pic.max_qp_app = 51;
83 enc->enc_pic.rc_per_pic.max_au_size = 0;
84 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rate_ctrl[0].fill_data_enable;
85 enc->enc_pic.rc_per_pic.skip_frame_enable = false;
86 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rate_ctrl[0].enforce_hrd;
87
88 switch (pic->rate_ctrl[0].rate_ctrl_method) {
89 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_DISABLE:
90 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
91 break;
92 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
93 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT:
94 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
95 break;
96 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
97 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE:
98 enc->enc_pic.rc_session_init.rate_control_method =
99 RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
100 break;
101 default:
102 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
103 }
104 } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
105 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
106 enc->enc_pic.picture_type = pic->picture_type;
107 enc->enc_pic.frame_num = pic->frame_num;
108 enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
109 enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
110 enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
111 enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
112 enc->enc_pic.not_referenced = pic->not_referenced;
113 enc->enc_pic.is_idr = (pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR) ||
114 (pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_I);
115
116 if (pic->seq.conformance_window_flag) {
117 enc->enc_pic.crop_left = pic->seq.conf_win_left_offset;
118 enc->enc_pic.crop_right = pic->seq.conf_win_right_offset;
119 enc->enc_pic.crop_top = pic->seq.conf_win_top_offset;
120 enc->enc_pic.crop_bottom = pic->seq.conf_win_bottom_offset;
121 } else {
122 enc->enc_pic.crop_left = 0;
123 enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
124 enc->enc_pic.crop_top = 0;
125 enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
126 }
127
128 enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
129 enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
130 enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
131 enc->enc_pic.max_poc = MAX2(16, util_next_power_of_two(pic->seq.intra_period));
132 enc->enc_pic.log2_max_poc = 0;
133 enc->enc_pic.num_temporal_layers = 1;
134 for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
135 i = (i >> 1);
136 enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
137 enc->enc_pic.pic_width_in_luma_samples = pic->seq.pic_width_in_luma_samples;
138 enc->enc_pic.pic_height_in_luma_samples = pic->seq.pic_height_in_luma_samples;
139 enc->enc_pic.log2_diff_max_min_luma_coding_block_size =
140 pic->seq.log2_diff_max_min_luma_coding_block_size;
141 enc->enc_pic.log2_min_transform_block_size_minus2 =
142 pic->seq.log2_min_transform_block_size_minus2;
143 enc->enc_pic.log2_diff_max_min_transform_block_size =
144 pic->seq.log2_diff_max_min_transform_block_size;
145 enc->enc_pic.max_transform_hierarchy_depth_inter =
146 pic->seq.max_transform_hierarchy_depth_inter;
147 enc->enc_pic.max_transform_hierarchy_depth_intra =
148 pic->seq.max_transform_hierarchy_depth_intra;
149 enc->enc_pic.log2_parallel_merge_level_minus2 = pic->pic.log2_parallel_merge_level_minus2;
150 enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
151 enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
152 enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
153 enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand;
154 enc->enc_pic.sample_adaptive_offset_enabled_flag =
155 pic->seq.sample_adaptive_offset_enabled_flag;
156 enc->enc_pic.pcm_enabled_flag = pic->seq.pcm_enabled_flag;
157 enc->enc_pic.sps_temporal_mvp_enabled_flag = pic->seq.sps_temporal_mvp_enabled_flag;
158 enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled =
159 pic->slice.slice_loop_filter_across_slices_enabled_flag;
160 enc->enc_pic.hevc_deblock.deblocking_filter_disabled =
161 pic->slice.slice_deblocking_filter_disabled_flag;
162 enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
163 enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
164 enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
165 enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
166 enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 =
167 pic->seq.log2_min_luma_coding_block_size_minus3;
168 enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
169 enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled =
170 pic->seq.strong_intra_smoothing_enabled_flag;
171 enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag =
172 pic->pic.constrained_intra_pred_flag;
173 enc->enc_pic.hevc_spec_misc.cabac_init_flag = pic->slice.cabac_init_flag;
174 enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
175 enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
176 enc->enc_pic.rc_layer_init[0].target_bit_rate = pic->rc.target_bitrate;
177 enc->enc_pic.rc_layer_init[0].peak_bit_rate = pic->rc.peak_bitrate;
178 enc->enc_pic.rc_layer_init[0].frame_rate_num = pic->rc.frame_rate_num;
179 enc->enc_pic.rc_layer_init[0].frame_rate_den = pic->rc.frame_rate_den;
180 enc->enc_pic.rc_layer_init[0].vbv_buffer_size = pic->rc.vbv_buffer_size;
181 enc->enc_pic.rc_layer_init[0].avg_target_bits_per_picture = pic->rc.target_bits_picture;
182 enc->enc_pic.rc_layer_init[0].peak_bits_per_picture_integer = pic->rc.peak_bits_picture_integer;
183 enc->enc_pic.rc_layer_init[0].peak_bits_per_picture_fractional =
184 pic->rc.peak_bits_picture_fraction;
185 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rc.vbv_buf_lv;
186 enc->enc_pic.rc_per_pic.qp = pic->rc.quant_i_frames;
187 enc->enc_pic.rc_per_pic.min_qp_app = 0;
188 enc->enc_pic.rc_per_pic.max_qp_app = 51;
189 enc->enc_pic.rc_per_pic.max_au_size = 0;
190 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rc.fill_data_enable;
191 enc->enc_pic.rc_per_pic.skip_frame_enable = false;
192 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rc.enforce_hrd;
193 switch (pic->rc.rate_ctrl_method) {
194 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_DISABLE:
195 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
196 break;
197 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
198 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT:
199 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
200 break;
201 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
202 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE:
203 enc->enc_pic.rc_session_init.rate_control_method =
204 RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
205 break;
206 default:
207 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
208 }
209 }
210 }
211
flush(struct radeon_encoder * enc)212 static void flush(struct radeon_encoder *enc)
213 {
214 enc->ws->cs_flush(&enc->cs, PIPE_FLUSH_ASYNC, NULL);
215 }
216
radeon_enc_flush(struct pipe_video_codec * encoder)217 static void radeon_enc_flush(struct pipe_video_codec *encoder)
218 {
219 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
220 flush(enc);
221 }
222
radeon_enc_cs_flush(void * ctx,unsigned flags,struct pipe_fence_handle ** fence)223 static void radeon_enc_cs_flush(void *ctx, unsigned flags, struct pipe_fence_handle **fence)
224 {
225 // just ignored
226 }
227
get_cpb_num(struct radeon_encoder * enc)228 static unsigned get_cpb_num(struct radeon_encoder *enc)
229 {
230 unsigned w = align(enc->base.width, 16) / 16;
231 unsigned h = align(enc->base.height, 16) / 16;
232 unsigned dpb;
233
234 switch (enc->base.level) {
235 case 10:
236 dpb = 396;
237 break;
238 case 11:
239 dpb = 900;
240 break;
241 case 12:
242 case 13:
243 case 20:
244 dpb = 2376;
245 break;
246 case 21:
247 dpb = 4752;
248 break;
249 case 22:
250 case 30:
251 dpb = 8100;
252 break;
253 case 31:
254 dpb = 18000;
255 break;
256 case 32:
257 dpb = 20480;
258 break;
259 case 40:
260 case 41:
261 dpb = 32768;
262 break;
263 case 42:
264 dpb = 34816;
265 break;
266 case 50:
267 dpb = 110400;
268 break;
269 default:
270 case 51:
271 case 52:
272 dpb = 184320;
273 break;
274 }
275
276 return MIN2(dpb / (w * h), 16);
277 }
278
radeon_enc_begin_frame(struct pipe_video_codec * encoder,struct pipe_video_buffer * source,struct pipe_picture_desc * picture)279 static void radeon_enc_begin_frame(struct pipe_video_codec *encoder,
280 struct pipe_video_buffer *source,
281 struct pipe_picture_desc *picture)
282 {
283 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
284 struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
285 bool need_rate_control = false;
286
287 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
288 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
289 need_rate_control =
290 (enc->enc_pic.rc_layer_init[0].target_bit_rate != pic->rate_ctrl[0].target_bitrate) ||
291 (enc->enc_pic.rc_layer_init[0].frame_rate_num != pic->rate_ctrl[0].frame_rate_num) ||
292 (enc->enc_pic.rc_layer_init[0].frame_rate_den != pic->rate_ctrl[0].frame_rate_den);
293 } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
294 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
295 need_rate_control = enc->enc_pic.rc_layer_init[0].target_bit_rate != pic->rc.target_bitrate;
296 }
297
298 radeon_vcn_enc_get_param(enc, picture);
299
300 enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
301 enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma);
302
303 enc->need_feedback = false;
304
305 if (!enc->stream_handle) {
306 struct rvid_buffer fb;
307 enc->stream_handle = si_vid_alloc_stream_handle();
308 enc->si = CALLOC_STRUCT(rvid_buffer);
309 si_vid_create_buffer(enc->screen, enc->si, 128 * 1024, PIPE_USAGE_STAGING);
310 si_vid_create_buffer(enc->screen, &fb, 4096, PIPE_USAGE_STAGING);
311 enc->fb = &fb;
312 enc->begin(enc);
313 flush(enc);
314 si_vid_destroy_buffer(&fb);
315 }
316 if (need_rate_control) {
317 enc->begin(enc);
318 flush(enc);
319 }
320 }
321
radeon_enc_encode_bitstream(struct pipe_video_codec * encoder,struct pipe_video_buffer * source,struct pipe_resource * destination,void ** fb)322 static void radeon_enc_encode_bitstream(struct pipe_video_codec *encoder,
323 struct pipe_video_buffer *source,
324 struct pipe_resource *destination, void **fb)
325 {
326 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
327 enc->get_buffer(destination, &enc->bs_handle, NULL);
328 enc->bs_size = destination->width0;
329
330 *fb = enc->fb = CALLOC_STRUCT(rvid_buffer);
331
332 if (!si_vid_create_buffer(enc->screen, enc->fb, 4096, PIPE_USAGE_STAGING)) {
333 RVID_ERR("Can't create feedback buffer.\n");
334 return;
335 }
336
337 enc->need_feedback = true;
338 enc->encode(enc);
339 }
340
radeon_enc_end_frame(struct pipe_video_codec * encoder,struct pipe_video_buffer * source,struct pipe_picture_desc * picture)341 static void radeon_enc_end_frame(struct pipe_video_codec *encoder, struct pipe_video_buffer *source,
342 struct pipe_picture_desc *picture)
343 {
344 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
345 flush(enc);
346 }
347
radeon_enc_destroy(struct pipe_video_codec * encoder)348 static void radeon_enc_destroy(struct pipe_video_codec *encoder)
349 {
350 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
351
352 if (enc->stream_handle) {
353 struct rvid_buffer fb;
354 enc->need_feedback = false;
355 si_vid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
356 enc->fb = &fb;
357 enc->destroy(enc);
358 flush(enc);
359 if (enc->si) {
360 si_vid_destroy_buffer(enc->si);
361 FREE(enc->si);
362 enc->si = NULL;
363 }
364 si_vid_destroy_buffer(&fb);
365 }
366
367 si_vid_destroy_buffer(&enc->cpb);
368 enc->ws->cs_destroy(&enc->cs);
369 FREE(enc);
370 }
371
radeon_enc_get_feedback(struct pipe_video_codec * encoder,void * feedback,unsigned * size)372 static void radeon_enc_get_feedback(struct pipe_video_codec *encoder, void *feedback,
373 unsigned *size)
374 {
375 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
376 struct rvid_buffer *fb = feedback;
377
378 if (size) {
379 uint32_t *ptr = enc->ws->buffer_map(enc->ws, fb->res->buf, &enc->cs,
380 PIPE_MAP_READ_WRITE | RADEON_MAP_TEMPORARY);
381 if (ptr[1])
382 *size = ptr[6];
383 else
384 *size = 0;
385 enc->ws->buffer_unmap(enc->ws, fb->res->buf);
386 }
387
388 si_vid_destroy_buffer(fb);
389 FREE(fb);
390 }
391
radeon_create_encoder(struct pipe_context * context,const struct pipe_video_codec * templ,struct radeon_winsys * ws,radeon_enc_get_buffer get_buffer)392 struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
393 const struct pipe_video_codec *templ,
394 struct radeon_winsys *ws,
395 radeon_enc_get_buffer get_buffer)
396 {
397 struct si_screen *sscreen = (struct si_screen *)context->screen;
398 struct si_context *sctx = (struct si_context *)context;
399 struct radeon_encoder *enc;
400 struct pipe_video_buffer *tmp_buf, templat = {};
401 struct radeon_surf *tmp_surf;
402 unsigned cpb_size;
403
404 enc = CALLOC_STRUCT(radeon_encoder);
405
406 if (!enc)
407 return NULL;
408
409 enc->alignment = 256;
410 enc->base = *templ;
411 enc->base.context = context;
412 enc->base.destroy = radeon_enc_destroy;
413 enc->base.begin_frame = radeon_enc_begin_frame;
414 enc->base.encode_bitstream = radeon_enc_encode_bitstream;
415 enc->base.end_frame = radeon_enc_end_frame;
416 enc->base.flush = radeon_enc_flush;
417 enc->base.get_feedback = radeon_enc_get_feedback;
418 enc->get_buffer = get_buffer;
419 enc->bits_in_shifter = 0;
420 enc->screen = context->screen;
421 enc->ws = ws;
422
423 if (!ws->cs_create(&enc->cs, sctx->ctx, RING_VCN_ENC, radeon_enc_cs_flush, enc, false)) {
424 RVID_ERR("Can't get command submission context.\n");
425 goto error;
426 }
427
428 templat.buffer_format = PIPE_FORMAT_NV12;
429 if (enc->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
430 templat.buffer_format = PIPE_FORMAT_P010;
431 templat.width = enc->base.width;
432 templat.height = enc->base.height;
433 templat.interlaced = false;
434
435 if (!(tmp_buf = context->create_video_buffer(context, &templat))) {
436 RVID_ERR("Can't create video buffer.\n");
437 goto error;
438 }
439
440 enc->cpb_num = get_cpb_num(enc);
441
442 if (!enc->cpb_num)
443 goto error;
444
445 get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
446
447 cpb_size = (sscreen->info.chip_class < GFX9)
448 ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
449 align(tmp_surf->u.legacy.level[0].nblk_y, 32)
450 : align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
451 align(tmp_surf->u.gfx9.surf_height, 32);
452
453 cpb_size = cpb_size * 3 / 2;
454 cpb_size = cpb_size * enc->cpb_num;
455 tmp_buf->destroy(tmp_buf);
456
457 if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
458 RVID_ERR("Can't create CPB buffer.\n");
459 goto error;
460 }
461
462 if (sscreen->info.family >= CHIP_SIENNA_CICHLID)
463 radeon_enc_3_0_init(enc);
464 else if (sscreen->info.family >= CHIP_RENOIR)
465 radeon_enc_2_0_init(enc);
466 else
467 radeon_enc_1_2_init(enc);
468
469 return &enc->base;
470
471 error:
472 enc->ws->cs_destroy(&enc->cs);
473
474 si_vid_destroy_buffer(&enc->cpb);
475
476 FREE(enc);
477 return NULL;
478 }
479
radeon_enc_add_buffer(struct radeon_encoder * enc,struct pb_buffer * buf,enum radeon_bo_usage usage,enum radeon_bo_domain domain,signed offset)480 void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf,
481 enum radeon_bo_usage usage, enum radeon_bo_domain domain, signed offset)
482 {
483 enc->ws->cs_add_buffer(&enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
484 uint64_t addr;
485 addr = enc->ws->buffer_get_virtual_address(buf);
486 addr = addr + offset;
487 RADEON_ENC_CS(addr >> 32);
488 RADEON_ENC_CS(addr);
489 }
490
radeon_enc_set_emulation_prevention(struct radeon_encoder * enc,bool set)491 void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set)
492 {
493 if (set != enc->emulation_prevention) {
494 enc->emulation_prevention = set;
495 enc->num_zeros = 0;
496 }
497 }
498
radeon_enc_output_one_byte(struct radeon_encoder * enc,unsigned char byte)499 void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte)
500 {
501 if (enc->byte_index == 0)
502 enc->cs.current.buf[enc->cs.current.cdw] = 0;
503 enc->cs.current.buf[enc->cs.current.cdw] |=
504 ((unsigned int)(byte) << index_to_shifts[enc->byte_index]);
505 enc->byte_index++;
506
507 if (enc->byte_index >= 4) {
508 enc->byte_index = 0;
509 enc->cs.current.cdw++;
510 }
511 }
512
radeon_enc_emulation_prevention(struct radeon_encoder * enc,unsigned char byte)513 void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte)
514 {
515 if (enc->emulation_prevention) {
516 if ((enc->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) ||
517 (byte == 0x02) || (byte == 0x03))) {
518 radeon_enc_output_one_byte(enc, 0x03);
519 enc->bits_output += 8;
520 enc->num_zeros = 0;
521 }
522 enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
523 }
524 }
525
radeon_enc_code_fixed_bits(struct radeon_encoder * enc,unsigned int value,unsigned int num_bits)526 void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value,
527 unsigned int num_bits)
528 {
529 unsigned int bits_to_pack = 0;
530 enc->bits_size += num_bits;
531
532 while (num_bits > 0) {
533 unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
534 bits_to_pack =
535 num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
536
537 if (bits_to_pack < num_bits)
538 value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
539
540 enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
541 num_bits -= bits_to_pack;
542 enc->bits_in_shifter += bits_to_pack;
543
544 while (enc->bits_in_shifter >= 8) {
545 unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
546 enc->shifter <<= 8;
547 radeon_enc_emulation_prevention(enc, output_byte);
548 radeon_enc_output_one_byte(enc, output_byte);
549 enc->bits_in_shifter -= 8;
550 enc->bits_output += 8;
551 }
552 }
553 }
554
radeon_enc_reset(struct radeon_encoder * enc)555 void radeon_enc_reset(struct radeon_encoder *enc)
556 {
557 enc->emulation_prevention = false;
558 enc->shifter = 0;
559 enc->bits_in_shifter = 0;
560 enc->bits_output = 0;
561 enc->num_zeros = 0;
562 enc->byte_index = 0;
563 enc->bits_size = 0;
564 }
565
radeon_enc_byte_align(struct radeon_encoder * enc)566 void radeon_enc_byte_align(struct radeon_encoder *enc)
567 {
568 unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8;
569
570 if (num_padding_zeros > 0)
571 radeon_enc_code_fixed_bits(enc, 0, num_padding_zeros);
572 }
573
radeon_enc_flush_headers(struct radeon_encoder * enc)574 void radeon_enc_flush_headers(struct radeon_encoder *enc)
575 {
576 if (enc->bits_in_shifter != 0) {
577 unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
578 radeon_enc_emulation_prevention(enc, output_byte);
579 radeon_enc_output_one_byte(enc, output_byte);
580 enc->bits_output += enc->bits_in_shifter;
581 enc->shifter = 0;
582 enc->bits_in_shifter = 0;
583 enc->num_zeros = 0;
584 }
585
586 if (enc->byte_index > 0) {
587 enc->cs.current.cdw++;
588 enc->byte_index = 0;
589 }
590 }
591
radeon_enc_code_ue(struct radeon_encoder * enc,unsigned int value)592 void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value)
593 {
594 int x = -1;
595 unsigned int ue_code = value + 1;
596 value += 1;
597
598 while (value) {
599 value = (value >> 1);
600 x += 1;
601 }
602
603 unsigned int ue_length = (x << 1) + 1;
604 radeon_enc_code_fixed_bits(enc, ue_code, ue_length);
605 }
606
radeon_enc_code_se(struct radeon_encoder * enc,int value)607 void radeon_enc_code_se(struct radeon_encoder *enc, int value)
608 {
609 unsigned int v = 0;
610
611 if (value != 0)
612 v = (value < 0 ? ((unsigned int)(0 - value) << 1) : (((unsigned int)(value) << 1) - 1));
613
614 radeon_enc_code_ue(enc, v);
615 }
616