1 /* $FreeBSD: releng/12.2/sys/dev/usb/controller/xhci.c 365239 2020-09-02 10:10:28Z hselasky $ */
2 /*-
3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 *
5 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
31 *
32 * The XHCI 1.0 spec can be found at
33 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
34 * and the USB 3.0 spec at
35 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
36 */
37
38 /*
39 * A few words about the design implementation: This driver emulates
40 * the concept about TDs which is found in EHCI specification. This
41 * way we achieve that the USB controller drivers look similar to
42 * eachother which makes it easier to understand the code.
43 */
44
45 #include "implementation/global_implementation.h"
46 #include "controller/xhci.h"
47 #include "controller/xhcireg.h"
48
49 #define XHCI_BUS2SC(bus) \
50 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
51 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
52
53 static int xhcistreams;
54
55 #ifdef USB_DEBUG
56 static int xhcidebug = 20;
57 static int xhciroute = 0;
58 static int xhcipolling = 0;
59 static int xhcidma32 = 0;
60 static int xhcictlstep = 0;
61 #else
62 #define xhciroute 0
63 #define xhcidma32 0
64 #define xhcictlstep 0
65 #endif
66
67 #undef USB_DEBUG_VAR
68 #define USB_DEBUG_VAR xhcidebug
69
70 #ifdef LOSCFG_USB_DEBUG
71 static int xhcidebug = 0;
72 #endif
73
74
75 #define XHCI_INTR_ENDPT 1
76
77 #define XHCI_DO_CMD_TIMEOUT 1000
78
79 struct xhci_std_temp {
80 struct xhci_softc *sc;
81 struct usb_page_cache *pc;
82 struct xhci_td *td;
83 struct xhci_td *td_next;
84 uint32_t len;
85 uint32_t offset;
86 uint32_t max_packet_size;
87 uint32_t average;
88 uint16_t isoc_delta;
89 uint16_t isoc_frame;
90 uint8_t shortpkt;
91 uint8_t multishort;
92 uint8_t last_frame;
93 uint8_t trb_type;
94 uint8_t direction;
95 uint8_t tbc;
96 uint8_t tlbpc;
97 uint8_t step_td;
98 uint8_t do_isoc_sync;
99 };
100
101 static void xhci_do_poll(struct usb_bus *);
102 static void xhci_device_done(struct usb_xfer *, usb_error_t);
103 static void xhci_root_intr(struct xhci_softc *);
104 static void xhci_free_device_ext(struct usb_device *);
105 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
106 struct usb_endpoint_descriptor *);
107 static usb_proc_callback_t xhci_configure_msg;
108 static usb_error_t xhci_configure_device(struct usb_device *);
109 static usb_error_t xhci_configure_endpoint(struct usb_device *,
110 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
111 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
112 uint8_t);
113 static usb_error_t xhci_configure_mask(struct usb_device *,
114 uint32_t, uint8_t);
115 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
116 uint64_t, uint8_t);
117 static void xhci_endpoint_doorbell(struct usb_xfer *);
118 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
119 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
120 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
121 #ifdef USB_DEBUG
122 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
123 #endif
124
125 extern struct usb_bus_methods xhci_bus_methods;
126
127 #ifdef USB_DEBUG
128 static void
xhci_dump_trb(struct xhci_trb * trb)129 xhci_dump_trb(struct xhci_trb *trb)
130 {
131 DPRINTFN(5, "trb = %p\n", trb);
132 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
133 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
134 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
135 }
136
137 static void
xhci_dump_endpoint(struct xhci_softc * sc,struct xhci_endp_ctx * pep)138 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
139 {
140 DPRINTFN(5, "pep = %p\n", pep);
141 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
142 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
143 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
144 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
145 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
146 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
147 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
148 }
149
150 static void
xhci_dump_device(struct xhci_softc * sc,struct xhci_slot_ctx * psl)151 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
152 {
153 DPRINTFN(5, "psl = %p\n", psl);
154 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
155 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
156 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
157 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
158 }
159 #endif
160
161 uint8_t
xhci_use_polling(void)162 xhci_use_polling(void)
163 {
164 #ifdef USB_DEBUG
165 return (xhcipolling != 0);
166 #else
167 return (0);
168 #endif
169 }
170
171 static void
xhci_iterate_hw_softc(struct usb_bus * bus,usb_bus_mem_sub_cb_t * cb)172 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
173 {
174 struct xhci_softc *sc = XHCI_BUS2SC(bus);
175 uint8_t i;
176
177 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
178 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
179
180 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
181 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
182
183 for (i = 0; i != sc->sc_noscratch; i++) {
184 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
185 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
186 }
187 }
188
189 static void
xhci_ctx_set_le32(struct xhci_softc * sc,volatile uint32_t * ptr,uint32_t val)190 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
191 {
192 uint32_t offset;
193 if (sc->sc_ctx_is_64_byte) {
194 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
195 /* all contexts are initially 32-bytes */
196 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
197 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
198 }
199 *ptr = htole32(val);
200 }
201
202 static uint32_t
xhci_ctx_get_le32(struct xhci_softc * sc,volatile uint32_t * ptr)203 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
204 {
205 uint32_t offset;
206 if (sc->sc_ctx_is_64_byte) {
207 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
208 /* all contexts are initially 32-bytes */
209 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
210 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
211 }
212 return (le32toh(*ptr));
213 }
214
215 static void
xhci_ctx_set_le64(struct xhci_softc * sc,volatile uint64_t * ptr,uint64_t val)216 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
217 {
218 uint32_t offset;
219 if (sc->sc_ctx_is_64_byte) {
220 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
221 /* all contexts are initially 32-bytes */
222 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
223 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
224 }
225 *ptr = htole64(val);
226 }
227
228 #ifdef USB_DEBUG
229 static uint64_t
xhci_ctx_get_le64(struct xhci_softc * sc,volatile uint64_t * ptr)230 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
231 {
232 uint32_t offset;
233 if (sc->sc_ctx_is_64_byte) {
234 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
235 /* all contexts are initially 32-bytes */
236 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
237 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
238 }
239 return (le64toh(*ptr));
240 }
241 #endif
242
243 static int
xhci_reset_command_queue_locked(struct xhci_softc * sc)244 xhci_reset_command_queue_locked(struct xhci_softc *sc)
245 {
246 struct usb_page_search buf_res;
247 struct xhci_hw_root *phwr;
248 uint64_t addr;
249 uint32_t temp;
250
251 DPRINTF("\n");
252
253 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
254 if (temp & XHCI_CRCR_LO_CRR) {
255 DPRINTF("Command ring running\n");
256 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
257
258 /*
259 * Try to abort the last command as per section
260 * 4.6.1.2 "Aborting a Command" of the XHCI
261 * specification:
262 */
263
264 /* stop and cancel */
265 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
266 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
267
268 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
269 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
270
271 /* wait 250ms */
272 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
273
274 /* check if command ring is still running */
275 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
276 if (temp & XHCI_CRCR_LO_CRR) {
277 DPRINTF("Comand ring still running\n");
278 return (USB_ERR_IOERROR);
279 }
280 }
281
282 /* reset command ring */
283 sc->sc_command_ccs = 1;
284 sc->sc_command_idx = 0;
285
286 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
287
288 /* set up command ring control base address */
289 addr = buf_res.physaddr;
290 phwr = buf_res.buffer;
291 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
292
293 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
294
295 (void)memset_s(phwr->hwr_commands, sizeof(phwr->hwr_commands), 0, sizeof(phwr->hwr_commands));
296 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
297
298 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
299
300 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
301 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
302
303 return (0);
304 }
305
306 usb_error_t
xhci_start_controller(struct xhci_softc * sc)307 xhci_start_controller(struct xhci_softc *sc)
308 {
309 struct usb_page_search buf_res;
310 struct xhci_hw_root *phwr;
311 struct xhci_dev_ctx_addr *pdctxa;
312 uint64_t addr;
313 uint32_t temp;
314 uint16_t i;
315 int ret;
316
317 DPRINTF("\n");
318
319 sc->sc_event_ccs = 1;
320 sc->sc_event_idx = 0;
321 sc->sc_command_ccs = 1;
322 sc->sc_command_idx = 0;
323
324 /* Reset controller */
325 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
326
327 for (i = 0; i != 100; i++) {
328 usb_pause_mtx(NULL, hz / 100);
329 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
330 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
331 if (!temp)
332 break;
333 }
334
335 if (temp) {
336 device_printf(sc->sc_bus.parent, "Controller "
337 "reset timeout.\n");
338 return (USB_ERR_IOERROR);
339 }
340
341 /* set up number of device slots */
342 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
343 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
344
345 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
346
347 temp = XREAD4(sc, oper, XHCI_USBSTS);
348
349 /* clear interrupts */
350 XWRITE4(sc, oper, XHCI_USBSTS, temp);
351 /* disable all device notifications */
352 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
353
354 /* set up device context base address */
355 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
356 pdctxa = buf_res.buffer;
357 ret = memset_s(pdctxa, USB_PAGE_SIZE, 0, sizeof(*pdctxa));
358 if (ret != EOK) {
359 usb_err("memset_s failed, ret:%d\n", ret);
360 return (USB_ERR_BAD_BUFSIZE);
361 }
362
363 addr = buf_res.physaddr;
364 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
365
366 /* slot 0 points to the table of scratchpad pointers */
367 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
368
369 for (i = 0; i != sc->sc_noscratch; i++) {
370 struct usb_page_search buf_scp;
371 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
372 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
373 }
374
375 addr = buf_res.physaddr;
376
377 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
378 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
379 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
380 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
381
382 /* set up event table size */
383 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
384 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
385
386 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
387
388 /* set up interrupt rate */
389 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
390
391 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
392
393 phwr = buf_res.buffer;
394 addr = buf_res.physaddr;
395 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
396
397 /* reset hardware root structure */
398 ret = memset_s(phwr, USB_PAGE_SIZE, 0, sizeof(*phwr));
399 if (ret != EOK) {
400 usb_err("memset_s failed, ret:%d\n", ret);
401 return (USB_ERR_BAD_BUFSIZE);
402 }
403
404 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
405 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
406
407 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
408
409 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
410 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
411
412 addr = buf_res.physaddr;
413
414 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
415
416 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
417 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
418
419 /* set up interrupter registers */
420 temp = XREAD4(sc, runt, XHCI_IMAN(0));
421 temp |= XHCI_IMAN_INTR_ENA;
422 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
423
424 /* set up command ring control base address */
425 addr = buf_res.physaddr;
426 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
427
428 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
429
430 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
431 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
432
433 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
434
435 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
436
437 /* Go! */
438 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
439 XHCI_CMD_INTE | XHCI_CMD_HSEE);
440
441 for (i = 0; i != 100; i++) {
442 usb_pause_mtx(NULL, hz / 100);
443 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
444 if (!temp)
445 break;
446 }
447 if (temp) {
448 XWRITE4(sc, oper, XHCI_USBCMD, 0);
449 device_printf(sc->sc_bus.parent, "Run timeout.\n");
450 return (USB_ERR_IOERROR);
451 }
452
453 /* catch any lost interrupts */
454 xhci_do_poll(&sc->sc_bus);
455
456 if (sc->sc_port_route != NULL) {
457 /* Route all ports to the XHCI by default */
458 (void)sc->sc_port_route(sc->sc_bus.parent,
459 ~xhciroute, xhciroute);
460 }
461 return (USB_ERR_NORMAL_COMPLETION);
462 }
463
464 usb_error_t
xhci_halt_controller(struct xhci_softc * sc)465 xhci_halt_controller(struct xhci_softc *sc)
466 {
467 uint32_t temp;
468 uint16_t i;
469
470 DPRINTF("\n");
471
472 sc->sc_capa_off = 0;
473 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
474 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
475 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
476
477 /* Halt controller */
478 XWRITE4(sc, oper, XHCI_USBCMD, 0);
479
480 for (i = 0; i != 100; i++) {
481 usb_pause_mtx(NULL, hz / 100);
482 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
483 if (temp)
484 break;
485 }
486
487 if (!temp) {
488 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
489 return (USB_ERR_IOERROR);
490 }
491 return (USB_ERR_NORMAL_COMPLETION);
492 }
493
494 usb_error_t
xhci_reset_controller(struct xhci_softc * sc)495 xhci_reset_controller(struct xhci_softc *sc)
496 {
497 uint32_t temp = 0;
498 uint16_t i;
499
500 DPRINTF("\n");
501
502 /* Reset controller */
503 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
504
505 for (i = 0; i != 100; i++) {
506 usb_pause_mtx(NULL, hz / 100);
507 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
508 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
509 if (!temp)
510 break;
511 }
512
513 if (temp) {
514 device_printf(sc->sc_bus.parent, "Controller "
515 "reset timeout.\n");
516 return (USB_ERR_IOERROR);
517 }
518 return (USB_ERR_NORMAL_COMPLETION);
519 }
520
521 usb_error_t
xhci_init(struct xhci_softc * sc,device_t self,uint8_t dma32)522 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
523 {
524 uint32_t temp;
525
526 DPRINTF("\n");
527
528 /* initialize some bus fields */
529 sc->sc_bus.parent = self;
530
531 /* set the bus revision */
532 sc->sc_bus.usbrev = USB_REV_3_0;
533
534 /* set up the bus struct */
535 sc->sc_bus.methods = &xhci_bus_methods;
536
537 /* set up devices array */
538 sc->sc_bus.devices = sc->sc_devices;
539 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
540
541 /* set default cycle state in case of early interrupts */
542 sc->sc_event_ccs = 1;
543 sc->sc_command_ccs = 1;
544
545 /* set up bus space offsets */
546 sc->sc_capa_off = 0;
547 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
548 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
549 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
550
551 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
552 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
553 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
554
555 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
556
557 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
558 device_printf(sc->sc_bus.parent, "Controller does "
559 "not support 4K page size.\n");
560 return (usb_error_t)(ENXIO);
561 }
562
563 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
564
565 DPRINTF("HCS0 = 0x%08x\n", temp);
566
567 /* set up context size */
568 if (XHCI_HCS0_CSZ(temp)) {
569 sc->sc_ctx_is_64_byte = 1;
570 } else {
571 sc->sc_ctx_is_64_byte = 0;
572 }
573
574 /* get DMA bits */
575 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
576 xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
577
578 device_printf(self, "%d bytes context size, %d-bit DMA\n",
579 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
580
581 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
582
583 /* get number of device slots */
584 sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
585
586 if (sc->sc_noport == 0) {
587 device_printf(sc->sc_bus.parent, "Invalid number "
588 "of ports: %u\n", sc->sc_noport);
589 return (usb_error_t)(ENXIO);
590 }
591
592 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
593
594 DPRINTF("Max slots: %u\n", sc->sc_noslot);
595
596 if (sc->sc_noslot > XHCI_MAX_DEVICES)
597 sc->sc_noslot = XHCI_MAX_DEVICES;
598
599 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
600
601 DPRINTF("HCS2=0x%08x\n", temp);
602
603 /* get number of scratchpads */
604 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
605
606 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
607 device_printf(sc->sc_bus.parent, "XHCI request "
608 "too many scratchpads\n");
609 return (usb_error_t)(ENOMEM);
610 }
611
612 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
613
614 /* get event table size */
615 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
616 if (sc->sc_erst_max > XHCI_MAX_RSEG)
617 sc->sc_erst_max = XHCI_MAX_RSEG;
618
619 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
620
621 /* get maximum exit latency */
622 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
623 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
624
625 /* Check if we should use the default IMOD value. */
626 if (sc->sc_imod_default == 0)
627 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
628
629 /* get all DMA memory */
630 if (usb_bus_mem_alloc_all(&sc->sc_bus,
631 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
632 return (usb_error_t)(ENOMEM);
633 }
634
635 /* set up command queue mutex and condition varible */
636 cv_init(&sc->sc_cmd_cv, "CMDQ");
637 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
638
639 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
640 sc->sc_config_msg[0].bus = &sc->sc_bus;
641 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
642 sc->sc_config_msg[1].bus = &sc->sc_bus;
643
644 return (USB_ERR_NORMAL_COMPLETION);
645 }
646
647 void
xhci_uninit(struct xhci_softc * sc)648 xhci_uninit(struct xhci_softc *sc)
649 {
650 /*
651 * NOTE: At this point the control transfer process is gone
652 * and "xhci_configure_msg" is no longer called. Consequently
653 * waiting for the configuration messages to complete is not
654 * needed.
655 */
656 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
657
658 cv_destroy(&sc->sc_cmd_cv);
659 sx_destroy(&sc->sc_cmd_sx);
660 }
661
662 static void
xhci_set_hw_power_sleep(struct usb_bus * bus,uint32_t state)663 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
664 {
665 struct xhci_softc *sc = XHCI_BUS2SC(bus);
666
667 switch (state) {
668 case USB_HW_POWER_SUSPEND:
669 DPRINTF("Stopping the XHCI\n");
670 (void)xhci_halt_controller(sc);
671 (void)xhci_reset_controller(sc);
672 break;
673 case USB_HW_POWER_SHUTDOWN:
674 DPRINTF("Stopping the XHCI\n");
675 (void)xhci_halt_controller(sc);
676 (void)xhci_reset_controller(sc);
677 break;
678 case USB_HW_POWER_RESUME:
679 DPRINTF("Starting the XHCI\n");
680 (void)xhci_start_controller(sc);
681 break;
682 default:
683 break;
684 }
685 }
686
687 static usb_error_t
xhci_generic_done_sub(struct usb_xfer * xfer)688 xhci_generic_done_sub(struct usb_xfer *xfer)
689 {
690 struct xhci_td *td;
691 struct xhci_td *td_alt_next;
692 uint32_t len;
693 uint8_t status;
694
695 td = xfer->td_transfer_cache;
696 td_alt_next = td->alt_next;
697
698 if (xfer->aframes != xfer->nframes)
699 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
700
701 while (1) {
702
703 usb_pc_cpu_invalidate(td->page_cache);
704
705 status = td->status;
706 len = td->remainder;
707
708 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
709 xfer, (unsigned int)xfer->aframes,
710 (unsigned int)xfer->nframes,
711 (unsigned int)len, (unsigned int)td->len,
712 (unsigned int)status);
713
714 /*
715 * Verify the status length and
716 * add the length to "frlengths[]":
717 */
718 if (len > td->len) {
719 /* should not happen */
720 DPRINTF("Invalid status length, "
721 "0x%04x/0x%04x bytes\n", len, td->len);
722 status = XHCI_TRB_ERROR_LENGTH;
723 } else if (xfer->aframes != xfer->nframes) {
724 xfer->frlengths[xfer->aframes] += td->len - len;
725 }
726 /* Check for last transfer */
727 if (((void *)td) == xfer->td_transfer_last) {
728 td = NULL;
729 break;
730 }
731 /* Check for transfer error */
732 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
733 status != XHCI_TRB_ERROR_SUCCESS) {
734 /* the transfer is finished */
735 td = NULL;
736 break;
737 }
738 /* Check for short transfer */
739 if (len > 0) {
740 if (xfer->flags_int.short_frames_ok ||
741 xfer->flags_int.isochronous_xfr ||
742 xfer->flags_int.control_xfr) {
743 /* follow alt next */
744 td = td->alt_next;
745 } else {
746 /* the transfer is finished */
747 td = NULL;
748 }
749 break;
750 }
751 td = td->obj_next;
752
753 if (td->alt_next != td_alt_next) {
754 /* this USB frame is complete */
755 break;
756 }
757 }
758
759 /* update transfer cache */
760
761 xfer->td_transfer_cache = td;
762
763 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
764 (status != XHCI_TRB_ERROR_SHORT_PKT &&
765 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
766 USB_ERR_NORMAL_COMPLETION);
767 }
768
769 static void
xhci_generic_done(struct usb_xfer * xfer)770 xhci_generic_done(struct usb_xfer *xfer)
771 {
772 usb_error_t err = USB_ERR_NORMAL_COMPLETION;
773
774 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
775 xfer, xfer->endpoint);
776
777 /* reset scanner */
778
779 xfer->td_transfer_cache = xfer->td_transfer_first;
780
781 if (xfer->flags_int.control_xfr) {
782
783 if (xfer->flags_int.control_hdr)
784 err = xhci_generic_done_sub(xfer);
785
786 xfer->aframes = 1;
787
788 if (xfer->td_transfer_cache == NULL)
789 goto done;
790 }
791
792 while (xfer->aframes != xfer->nframes) {
793
794 err = xhci_generic_done_sub(xfer);
795 xfer->aframes++;
796
797 if (xfer->td_transfer_cache == NULL)
798 goto done;
799 }
800
801 if (xfer->flags_int.control_xfr &&
802 !xfer->flags_int.control_act)
803 err = xhci_generic_done_sub(xfer);
804 done:
805 /* transfer is complete */
806 xhci_device_done(xfer, err);
807 }
808
809 static void
xhci_activate_transfer(struct usb_xfer * xfer)810 xhci_activate_transfer(struct usb_xfer *xfer)
811 {
812 struct xhci_td *td;
813
814 td = xfer->td_transfer_cache;
815
816 usb_pc_cpu_invalidate(td->page_cache);
817
818 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
819 /* activate the transfer */
820 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
821 usb_pc_cpu_flush(td->page_cache);
822
823 xhci_endpoint_doorbell(xfer);
824 }
825 }
826
827 static void
xhci_skip_transfer(struct usb_xfer * xfer)828 xhci_skip_transfer(struct usb_xfer *xfer)
829 {
830 struct xhci_td *td;
831 struct xhci_td *td_last;
832
833 td = xfer->td_transfer_cache;
834 td_last = xfer->td_transfer_last;
835
836 td = td->alt_next;
837
838 usb_pc_cpu_invalidate(td->page_cache);
839
840 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
841 usb_pc_cpu_invalidate(td_last->page_cache);
842
843 /* copy LINK TRB to current waiting location */
844
845 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
846 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
847 usb_pc_cpu_flush(td->page_cache);
848
849 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
850 usb_pc_cpu_flush(td->page_cache);
851
852 xhci_endpoint_doorbell(xfer);
853 }
854 }
855
856 /*------------------------------------------------------------------------*
857 * xhci_check_transfer
858 *------------------------------------------------------------------------*/
859 static void
xhci_check_transfer(struct xhci_softc * sc,struct xhci_trb * trb)860 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
861 {
862 struct xhci_endpoint_ext *pepext;
863 int64_t offset;
864 uint64_t td_event;
865 uint32_t temp;
866 uint32_t remainder;
867 uint16_t stream_id = 0;
868 uint16_t i;
869 uint8_t status;
870 uint8_t halted;
871 uint8_t epno;
872 uint8_t index;
873
874 /* decode TRB */
875 td_event = le64toh(trb->qwTrb0);
876 temp = le32toh(trb->dwTrb2);
877
878 remainder = XHCI_TRB_2_REM_GET(temp);
879 status = XHCI_TRB_2_ERROR_GET(temp);
880
881 temp = le32toh(trb->dwTrb3);
882 epno = XHCI_TRB_3_EP_GET(temp);
883 index = XHCI_TRB_3_SLOT_GET(temp);
884
885 /* check if error means halted */
886 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
887 status != XHCI_TRB_ERROR_SUCCESS);
888
889 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
890 index, epno, remainder, status);
891
892 if (index > sc->sc_noslot) {
893 DPRINTF("Invalid slot.\n");
894 return;
895 }
896
897 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
898 DPRINTF("Invalid endpoint.\n");
899 return;
900 }
901
902 pepext = &sc->sc_hw.devs[index].endp[epno];
903
904 /* try to find the USB transfer that generated the event */
905 for (i = 0;; i++) {
906 struct usb_xfer *xfer;
907 struct xhci_td *td;
908
909 if (i == (XHCI_MAX_TRANSFERS - 1)) {
910 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS ||
911 stream_id == (XHCI_MAX_STREAMS - 1))
912 break;
913 stream_id++;
914 i = 0;
915 DPRINTFN(5, "stream_id=%u\n", stream_id);
916 }
917
918 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
919 if (xfer == NULL)
920 continue;
921
922 td = xfer->td_transfer_cache;
923 if (td == NULL) {
924 continue;
925 }
926
927 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
928 (long long)td_event,
929 (long long)td->td_self,
930 (long long)td->td_self + sizeof(td->td_trb));
931
932 /*
933 * NOTE: Some XHCI implementations might not trigger
934 * an event on the last LINK TRB so we need to
935 * consider both the last and second last event
936 * address as conditions for a successful transfer.
937 *
938 * NOTE: We assume that the XHCI will only trigger one
939 * event per chain of TRBs.
940 */
941
942 offset = td_event - td->td_self;
943
944 if ((offset >= 0) &&
945 (offset < (int64_t)sizeof(td->td_trb))) {
946
947 usb_pc_cpu_invalidate(td->page_cache);
948
949 /* compute rest of remainder, if any */
950 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
951 temp = le32toh(td->td_trb[i].dwTrb2);
952 remainder += XHCI_TRB_2_BYTES_GET(temp);
953 }
954
955 DPRINTFN(5, "New remainder: %u\n", remainder);
956
957 /* clear isochronous transfer errors */
958 if (xfer->flags_int.isochronous_xfr) {
959 if (halted) {
960 halted = 0;
961 status = XHCI_TRB_ERROR_SUCCESS;
962 remainder = td->len;
963 }
964 }
965
966 /* "td->remainder" is verified later */
967 td->remainder = remainder;
968 td->status = status;
969
970 usb_pc_cpu_flush(td->page_cache);
971
972 /*
973 * 1) Last transfer descriptor makes the
974 * transfer done
975 */
976 if (((void *)td) == xfer->td_transfer_last) {
977 DPRINTF("TD is last\n");
978 xhci_generic_done(xfer);
979 break;
980 }
981
982 /*
983 * 2) Any kind of error makes the transfer
984 * done
985 */
986 if (halted) {
987 DPRINTF("TD has I/O error\n");
988 xhci_generic_done(xfer);
989 break;
990 }
991
992 /*
993 * 3) If there is no alternate next transfer,
994 * a short packet also makes the transfer done
995 */
996 if (td->remainder > 0) {
997 if (td->alt_next == NULL) {
998 DPRINTF(
999 "short TD has no alternate next\n");
1000 xhci_generic_done(xfer);
1001 break;
1002 }
1003 DPRINTF("TD has short pkt\n");
1004 if (xfer->flags_int.short_frames_ok ||
1005 xfer->flags_int.isochronous_xfr ||
1006 xfer->flags_int.control_xfr) {
1007 /* follow the alt next */
1008 xfer->td_transfer_cache = td->alt_next;
1009 xhci_activate_transfer(xfer);
1010 break;
1011 }
1012 xhci_skip_transfer(xfer);
1013 xhci_generic_done(xfer);
1014 break;
1015 }
1016
1017 /*
1018 * 4) Transfer complete - go to next TD
1019 */
1020 DPRINTF("Following next TD\n");
1021 xfer->td_transfer_cache = td->obj_next;
1022 xhci_activate_transfer(xfer);
1023 break; /* there should only be one match */
1024 }
1025 }
1026 }
1027
1028 static int
xhci_check_command(struct xhci_softc * sc,struct xhci_trb * trb)1029 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1030 {
1031 if (sc->sc_cmd_addr == trb->qwTrb0) {
1032 DPRINTF("Received command event\n");
1033 sc->sc_cmd_result[0] = trb->dwTrb2;
1034 sc->sc_cmd_result[1] = trb->dwTrb3;
1035 (void)cv_signal(&sc->sc_cmd_cv);
1036 return (1); /* command match */
1037 }
1038 return (0);
1039 }
1040
1041 static int
xhci_interrupt_poll(struct xhci_softc * sc)1042 xhci_interrupt_poll(struct xhci_softc *sc)
1043 {
1044 struct usb_page_search buf_res;
1045 struct xhci_hw_root *phwr;
1046 uint64_t addr;
1047 uint32_t temp;
1048 int retval = 0;
1049 uint16_t i;
1050 uint8_t event;
1051 uint8_t j;
1052 uint8_t k;
1053 uint8_t t;
1054
1055 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1056
1057 phwr = buf_res.buffer;
1058
1059 /* Receive any events */
1060
1061 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1062
1063 i = sc->sc_event_idx;
1064 j = sc->sc_event_ccs;
1065 t = 2;
1066
1067 while (1) {
1068
1069 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1070
1071 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1072
1073 if (j != k)
1074 break;
1075
1076 event = XHCI_TRB_3_TYPE_GET(temp);
1077
1078 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1079 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1080 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1081 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1082
1083 switch (event) {
1084 case XHCI_TRB_EVENT_TRANSFER:
1085 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1086 break;
1087 case XHCI_TRB_EVENT_CMD_COMPLETE:
1088 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1089 break;
1090 default:
1091 DPRINTF("Unhandled event = %u\n", event);
1092 break;
1093 }
1094
1095 i++;
1096
1097 if (i == XHCI_MAX_EVENTS) {
1098 i = 0;
1099 j ^= 1;
1100
1101 /* check for timeout */
1102 if (!--t)
1103 break;
1104 }
1105 }
1106
1107 sc->sc_event_idx = i;
1108 sc->sc_event_ccs = j;
1109
1110 /*
1111 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1112 * latched. That means to activate the register we need to
1113 * write both the low and high double word of the 64-bit
1114 * register.
1115 */
1116
1117 addr = buf_res.physaddr;
1118 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1119
1120 /* try to clear busy bit */
1121 addr |= XHCI_ERDP_LO_BUSY;
1122
1123 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1124 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1125
1126 return (retval);
1127 }
1128
1129 static usb_error_t
xhci_do_command(struct xhci_softc * sc,struct xhci_trb * trb,uint16_t timeout_ms)1130 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1131 uint16_t timeout_ms)
1132 {
1133 struct usb_page_search buf_res;
1134 struct xhci_hw_root *phwr;
1135 uint64_t addr;
1136 uint32_t temp;
1137 uint8_t i;
1138 uint8_t j;
1139 uint8_t timeout = 0;
1140 usb_error_t err;
1141
1142 XHCI_CMD_ASSERT_LOCKED(sc);
1143
1144 /* get hardware root structure */
1145
1146 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1147
1148 phwr = buf_res.buffer;
1149
1150 /* Queue command */
1151
1152 USB_BUS_LOCK(&sc->sc_bus);
1153 retry:
1154 i = sc->sc_command_idx;
1155 j = sc->sc_command_ccs;
1156
1157 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1158 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1159 (long long)le64toh(trb->qwTrb0),
1160 (long)le32toh(trb->dwTrb2),
1161 (long)le32toh(trb->dwTrb3));
1162
1163 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1164 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1165
1166 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1167
1168 temp = trb->dwTrb3;
1169
1170 if (j)
1171 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1172 else
1173 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1174
1175 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1176
1177 phwr->hwr_commands[i].dwTrb3 = temp;
1178
1179 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1180
1181 addr = buf_res.physaddr;
1182 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1183
1184 sc->sc_cmd_addr = htole64(addr);
1185
1186 i++;
1187
1188 if (i == (XHCI_MAX_COMMANDS - 1)) {
1189
1190 if (j) {
1191 temp = htole32(XHCI_TRB_3_TC_BIT |
1192 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1193 XHCI_TRB_3_CYCLE_BIT);
1194 } else {
1195 temp = htole32(XHCI_TRB_3_TC_BIT |
1196 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1197 }
1198
1199 phwr->hwr_commands[i].dwTrb3 = temp;
1200
1201 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1202
1203 i = 0;
1204 j ^= 1;
1205 }
1206
1207 sc->sc_command_idx = i;
1208 sc->sc_command_ccs = j;
1209
1210 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1211
1212 err = (usb_error_t)cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1213 USB_MS_TO_TICKS(timeout_ms));
1214
1215 /*
1216 * In some error cases event interrupts are not generated.
1217 * Poll one time to see if the command has completed.
1218 */
1219 if ((err != 0) && (xhci_interrupt_poll(sc) != 0)) {
1220 DPRINTF("Command was completed when polling\n");
1221 err = USB_ERR_NORMAL_COMPLETION;
1222 }
1223 if (err != 0) {
1224 DPRINTF("Command timeout!\n");
1225 /*
1226 * After some weeks of continuous operation, it has
1227 * been observed that the ASMedia Technology, ASM1042
1228 * SuperSpeed USB Host Controller can suddenly stop
1229 * accepting commands via the command queue. Try to
1230 * first reset the command queue. If that fails do a
1231 * host controller reset.
1232 */
1233 if ((timeout == 0) &&
1234 (xhci_reset_command_queue_locked(sc) == 0)) {
1235 temp = le32toh(trb->dwTrb3);
1236
1237 /*
1238 * Avoid infinite XHCI reset loops if the set
1239 * address command fails to respond due to a
1240 * non-enumerating device:
1241 */
1242 if ((XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE) &&
1243 ((temp & XHCI_TRB_3_BSR_BIT) == 0)) {
1244 DPRINTF("Set address timeout\n");
1245 } else {
1246 timeout = 1;
1247 goto retry;
1248 }
1249 } else {
1250 DPRINTF("Controller reset!\n");
1251 usb_bus_reset_async_locked(&sc->sc_bus);
1252 }
1253 err = USB_ERR_TIMEOUT;
1254 trb->dwTrb2 = 0;
1255 trb->dwTrb3 = 0;
1256 } else {
1257 temp = le32toh(sc->sc_cmd_result[0]);
1258 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) {
1259 if (!((XHCI_TRB_2_ERROR_GET(temp) == XHCI_TRB_ERROR_SLOT_NOT_ON) &&
1260 (XHCI_TRB_3_SLOT_GET(le32toh(sc->sc_cmd_result[1]))))) {
1261 err = USB_ERR_IOERROR;
1262 }
1263 }
1264
1265 trb->dwTrb2 = sc->sc_cmd_result[0];
1266 trb->dwTrb3 = sc->sc_cmd_result[1];
1267 }
1268
1269 USB_BUS_UNLOCK(&sc->sc_bus);
1270
1271 return (err);
1272 }
1273
1274 static usb_error_t
xhci_cmd_enable_slot(struct xhci_softc * sc,uint8_t * pslot)1275 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1276 {
1277 struct xhci_trb trb;
1278 uint32_t temp;
1279 usb_error_t err;
1280
1281 DPRINTF("\n");
1282
1283 trb.qwTrb0 = 0;
1284 trb.dwTrb2 = 0;
1285 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1286
1287 err = xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */);
1288 if (err)
1289 goto done;
1290
1291 temp = le32toh(trb.dwTrb3);
1292
1293 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1294
1295 done:
1296 return (err);
1297 }
1298
1299 static usb_error_t
xhci_cmd_disable_slot(struct xhci_softc * sc,uint8_t slot_id)1300 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1301 {
1302 struct xhci_trb trb;
1303 uint32_t temp;
1304
1305 DPRINTF("\n");
1306
1307 trb.qwTrb0 = 0;
1308 trb.dwTrb2 = 0;
1309 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1310 XHCI_TRB_3_SLOT_SET(slot_id);
1311
1312 trb.dwTrb3 = htole32(temp);
1313
1314 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1315 }
1316
1317 static usb_error_t
xhci_cmd_set_address(struct xhci_softc * sc,uint64_t input_ctx,uint8_t bsr,uint8_t slot_id)1318 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1319 uint8_t bsr, uint8_t slot_id)
1320 {
1321 struct xhci_trb trb;
1322 uint32_t temp;
1323
1324 DPRINTF("\n");
1325
1326 trb.qwTrb0 = htole64(input_ctx);
1327 trb.dwTrb2 = 0;
1328 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1329 XHCI_TRB_3_SLOT_SET(slot_id);
1330
1331 if (bsr)
1332 temp |= XHCI_TRB_3_BSR_BIT;
1333
1334 trb.dwTrb3 = htole32(temp);
1335
1336 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1337 }
1338
1339 static usb_error_t
xhci_set_address(struct usb_device * udev,struct mtx * mtx,uint16_t address)1340 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1341 {
1342 struct usb_page_search buf_inp;
1343 struct usb_page_search buf_dev;
1344 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1345 struct xhci_hw_dev *hdev;
1346 struct xhci_dev_ctx *pdev;
1347 struct xhci_endpoint_ext *pepext;
1348 uint32_t temp;
1349 uint16_t mps;
1350 usb_error_t err;
1351 uint8_t index;
1352
1353 /* the root HUB case is not handled here */
1354 if (udev->parent_hub == NULL)
1355 return (USB_ERR_INVAL);
1356
1357 index = udev->controller_slot_id;
1358
1359 hdev = &sc->sc_hw.devs[index];
1360
1361 if (mtx != NULL)
1362 mtx_unlock(mtx);
1363
1364 XHCI_CMD_LOCK(sc);
1365
1366 switch (hdev->state) {
1367 case XHCI_ST_DEFAULT:
1368 case XHCI_ST_ENABLED:
1369
1370 hdev->state = XHCI_ST_ENABLED;
1371
1372 /* set configure mask to slot and EP0 */
1373 (void)xhci_configure_mask(udev, 3, 0);
1374
1375 /* configure input slot context structure */
1376 err = xhci_configure_device(udev);
1377
1378 if (err != 0) {
1379 DPRINTF("Could not configure device\n");
1380 break;
1381 }
1382
1383 /* configure input endpoint context structure */
1384 switch (udev->speed) {
1385 case USB_SPEED_LOW:
1386 case USB_SPEED_FULL:
1387 mps = 8;
1388 break;
1389 case USB_SPEED_HIGH:
1390 mps = 64;
1391 break;
1392 default:
1393 mps = 512;
1394 break;
1395 }
1396
1397 pepext = xhci_get_endpoint_ext(udev,
1398 &udev->ctrl_ep_desc);
1399
1400 /* ensure the control endpoint is setup again */
1401 USB_BUS_LOCK(udev->bus);
1402 pepext->trb_halted = 1;
1403 pepext->trb_running = 0;
1404 USB_BUS_UNLOCK(udev->bus);
1405
1406 err = xhci_configure_endpoint(udev,
1407 &udev->ctrl_ep_desc, pepext,
1408 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1409
1410 if (err != 0) {
1411 DPRINTF("Could not configure default endpoint\n");
1412 break;
1413 }
1414
1415 /* execute set address command */
1416 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1417
1418 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1419 (address == 0), index);
1420
1421 if (err != 0) {
1422 temp = le32toh(sc->sc_cmd_result[0]);
1423 if ((address == 0) && (sc->sc_port_route != NULL) &&
1424 (XHCI_TRB_2_ERROR_GET(temp) ==
1425 XHCI_TRB_ERROR_PARAMETER)) {
1426 /* LynxPoint XHCI - ports are not switchable */
1427 /* Un-route all ports from the XHCI */
1428 (void)sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1429 }
1430 DPRINTF("Could not set address "
1431 "for slot %u.\n", index);
1432 if (address != 0)
1433 break;
1434 }
1435
1436 /* update device address to new value */
1437
1438 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1439 pdev = buf_dev.buffer;
1440 usb_pc_cpu_invalidate(&hdev->device_pc);
1441
1442 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1443 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1444
1445 /* update device state to new value */
1446
1447 if (address != 0)
1448 hdev->state = XHCI_ST_ADDRESSED;
1449 else
1450 hdev->state = XHCI_ST_DEFAULT;
1451 break;
1452
1453 default:
1454 DPRINTF("Wrong state for set address.\n");
1455 err = USB_ERR_IOERROR;
1456 break;
1457 }
1458 XHCI_CMD_UNLOCK(sc);
1459
1460 if (mtx != NULL)
1461 mtx_lock(mtx);
1462
1463 return (err);
1464 }
1465
1466 static usb_error_t
xhci_cmd_configure_ep(struct xhci_softc * sc,uint64_t input_ctx,uint8_t deconfigure,uint8_t slot_id)1467 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1468 uint8_t deconfigure, uint8_t slot_id)
1469 {
1470 struct xhci_trb trb;
1471 uint32_t temp;
1472
1473 DPRINTF("\n");
1474
1475 trb.qwTrb0 = htole64(input_ctx);
1476 trb.dwTrb2 = 0;
1477 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1478 XHCI_TRB_3_SLOT_SET(slot_id);
1479
1480 if (deconfigure)
1481 temp |= XHCI_TRB_3_DCEP_BIT;
1482
1483 trb.dwTrb3 = htole32(temp);
1484
1485 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1486 }
1487
1488 static usb_error_t
xhci_cmd_evaluate_ctx(struct xhci_softc * sc,uint64_t input_ctx,uint8_t slot_id)1489 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1490 uint8_t slot_id)
1491 {
1492 struct xhci_trb trb;
1493 uint32_t temp;
1494
1495 DPRINTF("\n");
1496
1497 trb.qwTrb0 = htole64(input_ctx);
1498 trb.dwTrb2 = 0;
1499 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1500 XHCI_TRB_3_SLOT_SET(slot_id);
1501 trb.dwTrb3 = htole32(temp);
1502
1503 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1504 }
1505
1506 static usb_error_t
xhci_cmd_reset_ep(struct xhci_softc * sc,uint8_t preserve,uint8_t ep_id,uint8_t slot_id)1507 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1508 uint8_t ep_id, uint8_t slot_id)
1509 {
1510 struct xhci_trb trb;
1511 uint32_t temp;
1512
1513 DPRINTF("\n");
1514
1515 trb.qwTrb0 = 0;
1516 trb.dwTrb2 = 0;
1517 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1518 XHCI_TRB_3_SLOT_SET(slot_id) |
1519 XHCI_TRB_3_EP_SET(ep_id);
1520
1521 if (preserve)
1522 temp |= XHCI_TRB_3_PRSV_BIT;
1523
1524 trb.dwTrb3 = htole32(temp);
1525
1526 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1527 }
1528
1529 static usb_error_t
xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc * sc,uint64_t dequeue_ptr,uint16_t stream_id,uint8_t ep_id,uint8_t slot_id)1530 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1531 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1532 {
1533 struct xhci_trb trb;
1534 uint32_t temp;
1535
1536 DPRINTF("\n");
1537
1538 trb.qwTrb0 = htole64(dequeue_ptr);
1539
1540 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1541 trb.dwTrb2 = htole32(temp);
1542
1543 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1544 XHCI_TRB_3_SLOT_SET(slot_id) |
1545 XHCI_TRB_3_EP_SET(ep_id);
1546 trb.dwTrb3 = htole32(temp);
1547
1548 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1549 }
1550
1551 static usb_error_t
xhci_cmd_stop_ep(struct xhci_softc * sc,uint8_t suspend,uint8_t ep_id,uint8_t slot_id)1552 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1553 uint8_t ep_id, uint8_t slot_id)
1554 {
1555 struct xhci_trb trb;
1556 uint32_t temp;
1557
1558 DPRINTF("\n");
1559
1560 trb.qwTrb0 = 0;
1561 trb.dwTrb2 = 0;
1562 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1563 XHCI_TRB_3_SLOT_SET(slot_id) |
1564 XHCI_TRB_3_EP_SET(ep_id);
1565
1566 if (suspend)
1567 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1568
1569 trb.dwTrb3 = htole32(temp);
1570
1571 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1572 }
1573
1574 static usb_error_t
xhci_cmd_reset_dev(struct xhci_softc * sc,uint8_t slot_id)1575 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1576 {
1577 struct xhci_trb trb;
1578 uint32_t temp;
1579
1580 DPRINTF("\n");
1581
1582 trb.qwTrb0 = 0;
1583 trb.dwTrb2 = 0;
1584 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1585 XHCI_TRB_3_SLOT_SET(slot_id);
1586
1587 trb.dwTrb3 = htole32(temp);
1588
1589 return (xhci_do_command(sc, &trb, XHCI_DO_CMD_TIMEOUT/* ms */));
1590 }
1591
1592 /*------------------------------------------------------------------------*
1593 * xhci_interrupt - XHCI interrupt handler
1594 *------------------------------------------------------------------------*/
1595 void
xhci_interrupt(unsigned int irq,struct xhci_softc * sc)1596 xhci_interrupt(unsigned int irq, struct xhci_softc *sc)
1597 {
1598 uint32_t status;
1599 uint32_t temp;
1600
1601 USB_BUS_LOCK(&sc->sc_bus);
1602
1603 status = XREAD4(sc, oper, XHCI_USBSTS);
1604
1605 /* acknowledge interrupts, if any */
1606 if (status != 0) {
1607 XWRITE4(sc, oper, XHCI_USBSTS, status);
1608 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1609 }
1610
1611 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1612
1613 /* force clearing of pending interrupts */
1614 if (temp & XHCI_IMAN_INTR_PEND)
1615 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1616
1617 /* check for event(s) */
1618 (void)xhci_interrupt_poll(sc);
1619
1620 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1621 XHCI_STS_HSE | XHCI_STS_HCE)) {
1622
1623 if (status & XHCI_STS_PCD) {
1624 xhci_root_intr(sc);
1625 }
1626
1627 if (status & XHCI_STS_HCH) {
1628 PRINTK("%s: host controller halted\n",
1629 __FUNCTION__);
1630 }
1631
1632 if (status & XHCI_STS_HSE) {
1633 PRINTK("%s: host system error\n",
1634 __FUNCTION__);
1635 }
1636
1637 if (status & XHCI_STS_HCE) {
1638 PRINTK("%s: host controller error\n",
1639 __FUNCTION__);
1640 }
1641 }
1642 USB_BUS_UNLOCK(&sc->sc_bus);
1643 }
1644
1645 /*------------------------------------------------------------------------*
1646 * xhci_timeout - XHCI timeout handler
1647 *------------------------------------------------------------------------*/
1648 static void
xhci_timeout(void * arg)1649 xhci_timeout(void *arg)
1650 {
1651 struct usb_xfer *xfer = arg;
1652
1653 DPRINTF("xfer=%p\n", xfer);
1654
1655 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1656
1657 /* transfer is transferred */
1658 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1659 }
1660
1661 static void
xhci_do_poll(struct usb_bus * bus)1662 xhci_do_poll(struct usb_bus *bus)
1663 {
1664 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1665
1666 USB_BUS_LOCK(&sc->sc_bus);
1667 (void)xhci_interrupt_poll(sc);
1668 USB_BUS_UNLOCK(&sc->sc_bus);
1669 }
1670
1671 static void
xhci_setup_generic_chain_sub(struct xhci_std_temp * temp)1672 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1673 {
1674 struct usb_page_search buf_res;
1675 struct xhci_td *td;
1676 struct xhci_td *td_next;
1677 struct xhci_td *td_alt_next;
1678 struct xhci_td *td_first;
1679 uint32_t buf_offset;
1680 uint32_t average;
1681 uint32_t len_old;
1682 uint32_t npkt_off;
1683 uint32_t dword;
1684 uint8_t shortpkt_old;
1685 uint8_t precompute;
1686 uint8_t x;
1687
1688 td_alt_next = NULL;
1689 buf_offset = 0;
1690 shortpkt_old = temp->shortpkt;
1691 len_old = temp->len;
1692 npkt_off = 0;
1693 precompute = 1;
1694
1695 restart:
1696
1697 td = temp->td;
1698 td_next = td_first = temp->td_next;
1699
1700 while (1) {
1701
1702 if (temp->len == 0) {
1703
1704 if (temp->shortpkt)
1705 break;
1706
1707 /* send a Zero Length Packet, ZLP, last */
1708
1709 temp->shortpkt = 1;
1710 average = 0;
1711
1712 } else {
1713
1714 average = temp->average;
1715
1716 if (temp->len < average) {
1717 if (temp->len % temp->max_packet_size) {
1718 temp->shortpkt = 1;
1719 }
1720 average = temp->len;
1721 }
1722 }
1723
1724 if (td_next == NULL)
1725 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1726
1727 /* get next TD */
1728
1729 td = td_next;
1730 td_next = td->obj_next;
1731
1732 /* check if we are pre-computing */
1733
1734 if (precompute) {
1735
1736 /* update remaining length */
1737
1738 temp->len -= average;
1739
1740 continue;
1741 }
1742 /* fill out current TD */
1743
1744 td->len = average;
1745 td->remainder = 0;
1746 td->status = 0;
1747
1748 /* update remaining length */
1749
1750 temp->len -= average;
1751
1752 /* reset TRB index */
1753
1754 x = 0;
1755
1756 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1757 /* immediate data */
1758
1759 if (average > 8)
1760 average = 8;
1761
1762 td->td_trb[0].qwTrb0 = 0;
1763
1764 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1765 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1766 average);
1767
1768 dword = XHCI_TRB_2_BYTES_SET(8) |
1769 XHCI_TRB_2_TDSZ_SET(0) |
1770 XHCI_TRB_2_IRQ_SET(0);
1771
1772 td->td_trb[0].dwTrb2 = htole32(dword);
1773
1774 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1775 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1776
1777 /* check wLength */
1778 if (td->td_trb[0].qwTrb0 &
1779 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1780 if (td->td_trb[0].qwTrb0 &
1781 htole64(XHCI_TRB_0_DIR_IN_MASK))
1782 dword |= XHCI_TRB_3_TRT_IN;
1783 else
1784 dword |= XHCI_TRB_3_TRT_OUT;
1785 }
1786
1787 td->td_trb[0].dwTrb3 = htole32(dword);
1788 #ifdef USB_DEBUG
1789 xhci_dump_trb(&td->td_trb[x]);
1790 #endif
1791 x++;
1792
1793 } else do {
1794
1795 uint32_t npkt;
1796
1797 /* fill out buffer pointers */
1798
1799 if (average == 0) {
1800 (void)memset_s(&buf_res, sizeof(buf_res), 0, sizeof(buf_res));
1801 } else {
1802 usbd_get_page(temp->pc, temp->offset +
1803 buf_offset, &buf_res);
1804
1805 /* get length to end of page */
1806 if (buf_res.length > average)
1807 buf_res.length = average;
1808
1809 /* check for maximum length */
1810 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1811 buf_res.length = XHCI_TD_PAGE_SIZE;
1812
1813 npkt_off += buf_res.length;
1814 }
1815
1816 /* set up npkt */
1817 npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1818 temp->max_packet_size;
1819
1820 if (npkt == 0)
1821 npkt = 1;
1822 else if (npkt > 31)
1823 npkt = 31;
1824
1825 /* fill out TRB's */
1826 td->td_trb[x].qwTrb0 =
1827 htole64((uint64_t)buf_res.physaddr);
1828
1829 dword =
1830 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1831 XHCI_TRB_2_TDSZ_SET(npkt) |
1832 XHCI_TRB_2_IRQ_SET(0);
1833
1834 td->td_trb[x].dwTrb2 = htole32(dword);
1835
1836 switch (temp->trb_type) {
1837 case XHCI_TRB_TYPE_ISOCH:
1838 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1839 XHCI_TRB_3_TBC_SET(temp->tbc) |
1840 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1841 if (td != td_first) {
1842 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1843 } else if (temp->do_isoc_sync != 0) {
1844 temp->do_isoc_sync = 0;
1845 /* wait until "isoc_frame" */
1846 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1847 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1848 } else {
1849 /* start data transfer at next interval */
1850 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1851 XHCI_TRB_3_ISO_SIA_BIT;
1852 }
1853 if (temp->direction == UE_DIR_IN)
1854 dword |= XHCI_TRB_3_ISP_BIT;
1855 break;
1856 case XHCI_TRB_TYPE_DATA_STAGE:
1857 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1858 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1859 if (temp->direction == UE_DIR_IN)
1860 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1861 /*
1862 * Section 3.2.9 in the XHCI
1863 * specification about control
1864 * transfers says that we should use a
1865 * normal-TRB if there are more TRBs
1866 * extending the data-stage
1867 * TRB. Update the "trb_type".
1868 */
1869 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1870 break;
1871 case XHCI_TRB_TYPE_STATUS_STAGE:
1872 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1873 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1874 if (temp->direction == UE_DIR_IN)
1875 dword |= XHCI_TRB_3_DIR_IN;
1876 break;
1877 default: /* XHCI_TRB_TYPE_NORMAL */
1878 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1879 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1880 if (temp->direction == UE_DIR_IN)
1881 dword |= XHCI_TRB_3_ISP_BIT;
1882 break;
1883 }
1884 td->td_trb[x].dwTrb3 = htole32(dword);
1885
1886 average -= buf_res.length;
1887 buf_offset += buf_res.length;
1888 #ifdef USB_DEBUG
1889 xhci_dump_trb(&td->td_trb[x]);
1890 #endif
1891 x++;
1892
1893 } while (average != 0);
1894
1895 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1896
1897 /* store number of data TRB's */
1898
1899 td->ntrb = x;
1900
1901 DPRINTF("NTRB=%u\n", x);
1902
1903 /* fill out link TRB */
1904
1905 if (td_next != NULL) {
1906 /* link the current TD with the next one */
1907 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1908 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1909 } else {
1910 /* this field will get updated later */
1911 DPRINTF("NOLINK\n");
1912 }
1913
1914 dword = XHCI_TRB_2_IRQ_SET(0);
1915
1916 td->td_trb[x].dwTrb2 = htole32(dword);
1917
1918 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1919 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1920 /*
1921 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1922 * frame only receives a single short packet event
1923 * by setting the CHAIN bit in the LINK field. In
1924 * addition some XHCI controllers have problems
1925 * sending a ZLP unless the CHAIN-BIT is set in
1926 * the LINK TRB.
1927 */
1928 XHCI_TRB_3_CHAIN_BIT;
1929
1930 td->td_trb[x].dwTrb3 = htole32(dword);
1931
1932 td->alt_next = td_alt_next;
1933 #ifdef USB_DEBUG
1934 xhci_dump_trb(&td->td_trb[x]);
1935 #endif
1936 usb_pc_cpu_flush(td->page_cache);
1937 }
1938
1939 if (precompute) {
1940 precompute = 0;
1941
1942 /* set up alt next pointer, if any */
1943 if (temp->last_frame) {
1944 td_alt_next = NULL;
1945 } else {
1946 /* we use this field internally */
1947 td_alt_next = td_next;
1948 }
1949
1950 /* restore */
1951 temp->shortpkt = shortpkt_old;
1952 temp->len = len_old;
1953 goto restart;
1954 }
1955
1956 /*
1957 * Remove cycle bit from the first TRB if we are
1958 * stepping them:
1959 */
1960 if (temp->step_td != 0) {
1961 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1962 usb_pc_cpu_flush(td_first->page_cache);
1963 }
1964
1965 /* clear TD SIZE to zero, hence this is the last TRB */
1966 /* remove chain bit because this is the last data TRB in the chain */
1967 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1968 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1969 /* remove CHAIN-BIT from last LINK TRB */
1970 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1971
1972 usb_pc_cpu_flush(td->page_cache);
1973
1974 temp->td = td;
1975 temp->td_next = td_next;
1976 }
1977
1978 static void
xhci_setup_generic_chain(struct usb_xfer * xfer)1979 xhci_setup_generic_chain(struct usb_xfer *xfer)
1980 {
1981 struct xhci_std_temp temp;
1982 struct xhci_td *td;
1983 uint32_t x;
1984 uint32_t y;
1985 uint8_t mult;
1986
1987 temp.do_isoc_sync = 0;
1988 temp.step_td = 0;
1989 temp.tbc = 0;
1990 temp.tlbpc = 0;
1991 temp.average = xfer->max_hc_frame_size;
1992 temp.max_packet_size = xfer->max_packet_size;
1993 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1994 temp.pc = NULL;
1995 temp.last_frame = 0;
1996 temp.offset = 0;
1997 temp.multishort = xfer->flags_int.isochronous_xfr ||
1998 xfer->flags_int.control_xfr ||
1999 xfer->flags_int.short_frames_ok;
2000
2001 /* toggle the DMA set we are using */
2002 xfer->flags_int.curr_dma_set ^= 1;
2003
2004 /* get next DMA set */
2005 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2006
2007 temp.td = NULL;
2008 temp.td_next = td;
2009
2010 xfer->td_transfer_first = td;
2011 xfer->td_transfer_cache = td;
2012
2013 if (xfer->flags_int.isochronous_xfr) {
2014 uint8_t shift;
2015
2016 /* compute multiplier for ISOCHRONOUS transfers */
2017 mult = xfer->endpoint->ecomp ?
2018 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2019 : 0;
2020 /* check for USB 2.0 multiplier */
2021 if (mult == 0) {
2022 mult = (xfer->endpoint->edesc->
2023 wMaxPacketSize[1] >> 3) & 3;
2024 }
2025 /* range check */
2026 if (mult > 2)
2027 mult = 3;
2028 else
2029 mult++;
2030
2031 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2032
2033 DPRINTF("MFINDEX=0x%08x\n", x);
2034
2035 switch (usbd_get_speed(xfer->xroot->udev)) {
2036 case USB_SPEED_FULL:
2037 shift = 3;
2038 temp.isoc_delta = 8; /* 1ms */
2039 x += temp.isoc_delta - 1;
2040 x &= ~(temp.isoc_delta - 1);
2041 break;
2042 default:
2043 shift = usbd_xfer_get_fps_shift(xfer);
2044 temp.isoc_delta = 1U << shift;
2045 x += temp.isoc_delta - 1;
2046 x &= ~(temp.isoc_delta - 1);
2047 /* simple frame load balancing */
2048 x += xfer->endpoint->usb_uframe;
2049 break;
2050 }
2051
2052 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2053
2054 if ((xfer->endpoint->is_synced == 0) ||
2055 (y < (xfer->nframes << shift)) ||
2056 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2057 /*
2058 * If there is data underflow or the pipe
2059 * queue is empty we schedule the transfer a
2060 * few frames ahead of the current frame
2061 * position. Else two isochronous transfers
2062 * might overlap.
2063 */
2064 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2065 xfer->endpoint->is_synced = 1;
2066 temp.do_isoc_sync = 1;
2067
2068 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2069 }
2070
2071 /* compute isochronous completion time */
2072
2073 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2074
2075 xfer->isoc_time_complete =
2076 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2077 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2078
2079 x = 0;
2080 temp.isoc_frame = xfer->endpoint->isoc_next;
2081 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2082
2083 xfer->endpoint->isoc_next += xfer->nframes << shift;
2084
2085 } else if (xfer->flags_int.control_xfr) {
2086
2087 /* check if we should prepend a setup message */
2088
2089 if (xfer->flags_int.control_hdr) {
2090
2091 temp.len = xfer->frlengths[0];
2092 temp.pc = xfer->frbuffers + 0;
2093 temp.shortpkt = temp.len ? 1 : 0;
2094 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2095 temp.direction = 0;
2096
2097 /* check for last frame */
2098 if (xfer->nframes == 1) {
2099 /* no STATUS stage yet, SETUP is last */
2100 if (xfer->flags_int.control_act)
2101 temp.last_frame = 1;
2102 }
2103
2104 xhci_setup_generic_chain_sub(&temp);
2105 }
2106 x = 1;
2107 mult = 1;
2108 temp.isoc_delta = 0;
2109 temp.isoc_frame = 0;
2110 temp.trb_type = xfer->flags_int.control_did_data ?
2111 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2112 } else {
2113 x = 0;
2114 mult = 1;
2115 temp.isoc_delta = 0;
2116 temp.isoc_frame = 0;
2117 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2118 }
2119
2120 if (x != xfer->nframes) {
2121 /* set up page_cache pointer */
2122 temp.pc = xfer->frbuffers + x;
2123 /* set endpoint direction */
2124 temp.direction = UE_GET_DIR(xfer->endpointno);
2125 }
2126
2127 while (x != xfer->nframes) {
2128
2129 /* DATA0 / DATA1 message */
2130
2131 temp.len = xfer->frlengths[x];
2132 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2133 x != 0 && temp.multishort == 0);
2134
2135 x++;
2136
2137 if (x == xfer->nframes) {
2138 if (xfer->flags_int.control_xfr) {
2139 /* no STATUS stage yet, DATA is last */
2140 if (xfer->flags_int.control_act)
2141 temp.last_frame = 1;
2142 } else {
2143 temp.last_frame = 1;
2144 }
2145 }
2146 if (temp.len == 0) {
2147
2148 /* make sure that we send an USB packet */
2149
2150 temp.shortpkt = 0;
2151
2152 temp.tbc = 0;
2153 temp.tlbpc = mult - 1;
2154
2155 } else if (xfer->flags_int.isochronous_xfr) {
2156
2157 uint8_t tdpc;
2158
2159 /*
2160 * Isochronous transfers don't have short
2161 * packet termination:
2162 */
2163
2164 temp.shortpkt = 1;
2165
2166 /* isochronous transfers have a transfer limit */
2167
2168 if (temp.len > xfer->max_frame_size)
2169 temp.len = xfer->max_frame_size;
2170
2171 /* compute TD packet count */
2172 tdpc = (temp.len + xfer->max_packet_size - 1) /
2173 xfer->max_packet_size;
2174
2175 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2176 temp.tlbpc = (tdpc % mult);
2177
2178 if (temp.tlbpc == 0)
2179 temp.tlbpc = mult - 1;
2180 else
2181 temp.tlbpc--;
2182 } else {
2183
2184 /* regular data transfer */
2185
2186 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2187 }
2188
2189 xhci_setup_generic_chain_sub(&temp);
2190
2191 if (xfer->flags_int.isochronous_xfr) {
2192 temp.offset += xfer->frlengths[x - 1];
2193 temp.isoc_frame += temp.isoc_delta;
2194 } else {
2195 /* get next Page Cache pointer */
2196 temp.pc = xfer->frbuffers + x;
2197 }
2198 }
2199
2200 /* check if we should append a status stage */
2201
2202 if (xfer->flags_int.control_xfr &&
2203 !xfer->flags_int.control_act) {
2204
2205 /*
2206 * Send a DATA1 message and invert the current
2207 * endpoint direction.
2208 */
2209 if (xhcictlstep || temp.sc->sc_ctlstep) {
2210 /*
2211 * Some XHCI controllers will not delay the
2212 * status stage until the next SOF. Force this
2213 * behaviour to avoid failed control
2214 * transfers.
2215 */
2216 temp.step_td = (xfer->nframes != 0);
2217 } else {
2218 temp.step_td = 0;
2219 }
2220 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2221 temp.len = 0;
2222 temp.pc = NULL;
2223 temp.shortpkt = 0;
2224 temp.last_frame = 1;
2225 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2226
2227 xhci_setup_generic_chain_sub(&temp);
2228 }
2229
2230 td = temp.td;
2231
2232 /* must have at least one frame! */
2233
2234 xfer->td_transfer_last = td;
2235
2236 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2237 }
2238
2239 static void
xhci_set_slot_pointer(struct xhci_softc * sc,uint8_t index,uint64_t dev_addr)2240 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2241 {
2242 struct usb_page_search buf_res;
2243 struct xhci_dev_ctx_addr *pdctxa;
2244
2245 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2246
2247 pdctxa = buf_res.buffer;
2248
2249 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2250
2251 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2252
2253 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2254 }
2255
2256 static usb_error_t
xhci_configure_mask(struct usb_device * udev,uint32_t mask,uint8_t drop)2257 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2258 {
2259 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2260 struct usb_page_search buf_inp;
2261 struct xhci_input_dev_ctx *pinp;
2262 uint32_t temp;
2263 uint8_t index;
2264 uint8_t x;
2265
2266 index = udev->controller_slot_id;
2267
2268 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2269
2270 pinp = buf_inp.buffer;
2271
2272 if (drop) {
2273 mask &= XHCI_INCTX_NON_CTRL_MASK;
2274 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2275 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2276 } else {
2277 /*
2278 * Some hardware requires that we drop the endpoint
2279 * context before adding it again:
2280 */
2281 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2282 mask & XHCI_INCTX_NON_CTRL_MASK);
2283
2284 /* Add new endpoint context */
2285 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2286
2287 /* find most significant set bit */
2288 for (x = 31; x != 1; x--) {
2289 if (mask & (1 << x))
2290 break;
2291 }
2292
2293 /* adjust */
2294 x--;
2295
2296 /* figure out the maximum number of contexts */
2297 if (x > sc->sc_hw.devs[index].context_num)
2298 sc->sc_hw.devs[index].context_num = x;
2299 else
2300 x = sc->sc_hw.devs[index].context_num;
2301
2302 /* update number of contexts */
2303 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2304 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2305 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2306 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2307 }
2308 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2309 return (USB_ERR_NORMAL_COMPLETION);
2310 }
2311
2312 static usb_error_t
xhci_configure_endpoint(struct usb_device * udev,struct usb_endpoint_descriptor * edesc,struct xhci_endpoint_ext * pepext,uint16_t interval,uint8_t max_packet_count,uint8_t mult,uint8_t fps_shift,uint16_t max_packet_size,uint16_t max_frame_size,uint8_t ep_mode)2313 xhci_configure_endpoint(struct usb_device *udev,
2314 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2315 uint16_t interval, uint8_t max_packet_count,
2316 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2317 uint16_t max_frame_size, uint8_t ep_mode)
2318 {
2319 struct usb_page_search buf_inp;
2320 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2321 struct xhci_input_dev_ctx *pinp;
2322 uint64_t ring_addr = pepext->physaddr;
2323 uint32_t temp;
2324 uint8_t index;
2325 uint8_t epno;
2326 uint8_t type;
2327
2328 index = udev->controller_slot_id;
2329
2330 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2331
2332 pinp = buf_inp.buffer;
2333
2334 epno = edesc->bEndpointAddress;
2335 type = edesc->bmAttributes & UE_XFERTYPE;
2336
2337 if (type == UE_CONTROL)
2338 epno |= UE_DIR_IN;
2339
2340 epno = XHCI_EPNO2EPID(epno);
2341
2342 if (epno == 0)
2343 return (USB_ERR_NO_PIPE); /* invalid */
2344
2345 if (max_packet_count == 0)
2346 return (USB_ERR_BAD_BUFSIZE);
2347
2348 max_packet_count--;
2349
2350 if (mult == 0)
2351 return (USB_ERR_BAD_BUFSIZE);
2352
2353 /* store endpoint mode */
2354 pepext->trb_ep_mode = ep_mode;
2355 /* store bMaxPacketSize for control endpoints */
2356 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2357 usb_pc_cpu_flush(pepext->page_cache);
2358
2359 if (ep_mode == USB_EP_MODE_STREAMS) {
2360 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2361 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2362 XHCI_EPCTX_0_LSA_SET(1);
2363
2364 ring_addr += sizeof(struct xhci_trb) *
2365 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2366 } else {
2367 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2368 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2369 XHCI_EPCTX_0_LSA_SET(0);
2370
2371 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2372 }
2373
2374 switch (udev->speed) {
2375 case USB_SPEED_FULL:
2376 case USB_SPEED_LOW:
2377 /* 1ms -> 125us */
2378 fps_shift += 3;
2379 break;
2380 default:
2381 break;
2382 }
2383
2384 switch (type) {
2385 case UE_INTERRUPT:
2386 if (fps_shift > 3)
2387 fps_shift--;
2388 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2389 break;
2390 case UE_ISOCHRONOUS:
2391 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2392
2393 switch (udev->speed) {
2394 case USB_SPEED_SUPER:
2395 if (mult > 3)
2396 mult = 3;
2397 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2398 max_packet_count /= mult;
2399 break;
2400 default:
2401 break;
2402 }
2403 break;
2404 default:
2405 break;
2406 }
2407
2408 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2409
2410 temp =
2411 XHCI_EPCTX_1_HID_SET(0) |
2412 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2413 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2414
2415 /*
2416 * Always enable the "three strikes and you are gone" feature
2417 * except for ISOCHRONOUS endpoints. This is suggested by
2418 * section 4.3.3 in the XHCI specification about device slot
2419 * initialisation.
2420 */
2421 if (type != UE_ISOCHRONOUS)
2422 temp |= XHCI_EPCTX_1_CERR_SET(3);
2423
2424 switch (type) {
2425 case UE_CONTROL:
2426 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2427 break;
2428 case UE_ISOCHRONOUS:
2429 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2430 break;
2431 case UE_BULK:
2432 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2433 break;
2434 default:
2435 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2436 break;
2437 }
2438
2439 /* check for IN direction */
2440 if (epno & 1)
2441 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2442
2443 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2444 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2445
2446 switch (edesc->bmAttributes & UE_XFERTYPE) {
2447 case UE_INTERRUPT:
2448 case UE_ISOCHRONOUS:
2449 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2450 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2451 max_frame_size));
2452 break;
2453 case UE_CONTROL:
2454 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2455 break;
2456 default:
2457 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2458 break;
2459 }
2460
2461 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2462
2463 #ifdef USB_DEBUG
2464 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2465 #endif
2466 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2467
2468 return (USB_ERR_NORMAL_COMPLETION); /* success */
2469 }
2470
2471 static usb_error_t
xhci_configure_endpoint_by_xfer(struct usb_xfer * xfer)2472 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2473 {
2474 struct xhci_endpoint_ext *pepext;
2475 struct usb_endpoint_ss_comp_descriptor *ecomp;
2476 usb_stream_t x;
2477
2478 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2479 xfer->endpoint->edesc);
2480
2481 ecomp = xfer->endpoint->ecomp;
2482
2483 for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2484 uint64_t temp;
2485
2486 /* halt any transfers */
2487 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2488
2489 /* compute start of TRB ring for stream "x" */
2490 temp = pepext->physaddr +
2491 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2492 XHCI_SCTX_0_SCT_SEC_TR_RING;
2493
2494 /* make tree structure */
2495 pepext->trb[(XHCI_MAX_TRANSFERS *
2496 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2497
2498 /* reserved fields */
2499 pepext->trb[(XHCI_MAX_TRANSFERS *
2500 XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2501 pepext->trb[(XHCI_MAX_TRANSFERS *
2502 XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2503 }
2504 usb_pc_cpu_flush(pepext->page_cache);
2505
2506 return (xhci_configure_endpoint(xfer->xroot->udev,
2507 xfer->endpoint->edesc, pepext,
2508 xfer->interval, xfer->max_packet_count,
2509 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2510 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2511 xfer->max_frame_size, xfer->endpoint->ep_mode));
2512 }
2513
2514 static usb_error_t
xhci_configure_device(struct usb_device * udev)2515 xhci_configure_device(struct usb_device *udev)
2516 {
2517 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2518 struct usb_page_search buf_inp;
2519 struct usb_page_cache *pcinp;
2520 struct xhci_input_dev_ctx *pinp;
2521 struct usb_device *hubdev;
2522 uint32_t temp;
2523 uint32_t route;
2524 uint32_t rh_port;
2525 uint8_t is_hub;
2526 uint8_t index;
2527 uint8_t depth;
2528
2529 index = udev->controller_slot_id;
2530
2531 DPRINTF("index=%u\n", index);
2532
2533 pcinp = &sc->sc_hw.devs[index].input_pc;
2534
2535 usbd_get_page(pcinp, 0, &buf_inp);
2536
2537 pinp = buf_inp.buffer;
2538
2539 rh_port = 0;
2540 route = 0;
2541
2542 /* figure out route string and root HUB port number */
2543
2544 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2545
2546 if (hubdev->parent_hub == NULL)
2547 break;
2548
2549 depth = hubdev->parent_hub->depth;
2550
2551 /*
2552 * NOTE: HS/FS/LS devices and the SS root HUB can have
2553 * more than 15 ports
2554 */
2555
2556 rh_port = hubdev->port_no;
2557
2558 if (depth == 0)
2559 break;
2560
2561 if (rh_port > 15)
2562 rh_port = 15;
2563
2564 if (depth < 6)
2565 route |= rh_port << (4 * (depth - 1));
2566 }
2567
2568 DPRINTF("Route=0x%08x\n", route);
2569
2570 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2571 XHCI_SCTX_0_CTX_NUM_SET(
2572 sc->sc_hw.devs[index].context_num + 1);
2573
2574 switch (udev->speed) {
2575 case USB_SPEED_LOW:
2576 temp |= XHCI_SCTX_0_SPEED_SET(2);
2577 if ((udev->parent_hs_hub != NULL) &&
2578 (udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2579 UDPROTO_HSHUBMTT)) {
2580 DPRINTF("Device inherits MTT\n");
2581 temp |= XHCI_SCTX_0_MTT_SET(1);
2582 }
2583 break;
2584 case USB_SPEED_HIGH:
2585 temp |= XHCI_SCTX_0_SPEED_SET(3);
2586 if ((sc->sc_hw.devs[index].nports != 0) &&
2587 (udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT)) {
2588 DPRINTF("HUB supports MTT\n");
2589 temp |= XHCI_SCTX_0_MTT_SET(1);
2590 }
2591 break;
2592 case USB_SPEED_FULL:
2593 temp |= XHCI_SCTX_0_SPEED_SET(1);
2594 if ((udev->parent_hs_hub != NULL) &&
2595 (udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2596 UDPROTO_HSHUBMTT)) {
2597 DPRINTF("Device inherits MTT\n");
2598 temp |= XHCI_SCTX_0_MTT_SET(1);
2599 }
2600 break;
2601 default:
2602 temp |= XHCI_SCTX_0_SPEED_SET(4);
2603 break;
2604 }
2605
2606 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2607 (udev->speed == USB_SPEED_SUPER ||
2608 udev->speed == USB_SPEED_HIGH);
2609
2610 if (is_hub)
2611 temp |= XHCI_SCTX_0_HUB_SET(1);
2612
2613 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2614
2615 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2616
2617 if (is_hub) {
2618 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2619 sc->sc_hw.devs[index].nports);
2620 }
2621
2622 switch (udev->speed) {
2623 case USB_SPEED_SUPER:
2624 switch (sc->sc_hw.devs[index].state) {
2625 case XHCI_ST_ADDRESSED:
2626 case XHCI_ST_CONFIGURED:
2627 /* enable power save */
2628 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2629 break;
2630 default:
2631 /* disable power save */
2632 break;
2633 }
2634 break;
2635 default:
2636 break;
2637 }
2638
2639 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2640
2641 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2642
2643 if (is_hub) {
2644 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2645 sc->sc_hw.devs[index].tt);
2646 }
2647
2648 hubdev = udev->parent_hs_hub;
2649
2650 /* check if we should activate the transaction translator */
2651 switch (udev->speed) {
2652 case USB_SPEED_FULL:
2653 case USB_SPEED_LOW:
2654 if (hubdev != NULL) {
2655 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2656 hubdev->controller_slot_id);
2657 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2658 udev->hs_port_no);
2659 }
2660 break;
2661 default:
2662 break;
2663 }
2664
2665 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2666
2667 /*
2668 * These fields should be initialized to zero, according to
2669 * XHCI section 6.2.2 - slot context:
2670 */
2671 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2672 XHCI_SCTX_3_SLOT_STATE_SET(0);
2673
2674 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2675
2676 #ifdef USB_DEBUG
2677 xhci_dump_device(sc, &pinp->ctx_slot);
2678 #endif
2679 usb_pc_cpu_flush(pcinp);
2680
2681 return (USB_ERR_NORMAL_COMPLETION); /* success */
2682 }
2683
2684 static usb_error_t
xhci_alloc_device_ext(struct usb_device * udev)2685 xhci_alloc_device_ext(struct usb_device *udev)
2686 {
2687 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2688 struct usb_page_search buf_dev;
2689 struct usb_page_search buf_ep;
2690 struct xhci_trb *trb;
2691 struct usb_page_cache *pc;
2692 struct usb_page *pg;
2693 uint64_t addr;
2694 uint8_t index;
2695 uint8_t i;
2696
2697 index = udev->controller_slot_id;
2698
2699 pc = &sc->sc_hw.devs[index].device_pc;
2700 pg = &sc->sc_hw.devs[index].device_pg;
2701
2702 /* need to initialize the page cache */
2703 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2704
2705 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2706 (2 * sizeof(struct xhci_dev_ctx)) :
2707 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2708 goto error;
2709
2710 usbd_get_page(pc, 0, &buf_dev);
2711
2712 pc = &sc->sc_hw.devs[index].input_pc;
2713 pg = &sc->sc_hw.devs[index].input_pg;
2714
2715 /* need to initialize the page cache */
2716 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2717
2718 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2719 (2 * sizeof(struct xhci_input_dev_ctx)) :
2720 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2721 goto error;
2722 }
2723
2724 /* initialize all endpoint LINK TRBs */
2725
2726 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2727
2728 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2729 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2730
2731 /* need to initialize the page cache */
2732 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2733
2734 if (usb_pc_alloc_mem(pc, pg,
2735 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2736 goto error;
2737 }
2738
2739 /* lookup endpoint TRB ring */
2740 usbd_get_page(pc, 0, &buf_ep);
2741
2742 /* get TRB pointer */
2743 trb = buf_ep.buffer;
2744 trb += XHCI_MAX_TRANSFERS - 1;
2745
2746 /* get TRB start address */
2747 addr = buf_ep.physaddr;
2748
2749 /* create LINK TRB */
2750 trb->qwTrb0 = htole64(addr);
2751 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2752 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2753 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2754
2755 usb_pc_cpu_flush(pc);
2756 }
2757
2758 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2759
2760 return (USB_ERR_NORMAL_COMPLETION);
2761
2762 error:
2763 xhci_free_device_ext(udev);
2764
2765 return (USB_ERR_NOMEM);
2766 }
2767
2768 static void
xhci_free_device_ext(struct usb_device * udev)2769 xhci_free_device_ext(struct usb_device *udev)
2770 {
2771 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2772 uint8_t index;
2773 uint8_t i;
2774
2775 index = udev->controller_slot_id;
2776 xhci_set_slot_pointer(sc, index, 0);
2777
2778 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2779 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2780 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2781 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2782 }
2783
2784 static struct xhci_endpoint_ext *
xhci_get_endpoint_ext(struct usb_device * udev,struct usb_endpoint_descriptor * edesc)2785 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2786 {
2787 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2788 struct xhci_endpoint_ext *pepext;
2789 struct usb_page_cache *pc;
2790 struct usb_page_search buf_ep;
2791 uint8_t epno;
2792 uint8_t index;
2793
2794 epno = edesc->bEndpointAddress;
2795 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2796 epno |= UE_DIR_IN;
2797
2798 epno = XHCI_EPNO2EPID(epno);
2799
2800 index = udev->controller_slot_id;
2801
2802 pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2803
2804 usbd_get_page(pc, 0, &buf_ep);
2805
2806 pepext = &sc->sc_hw.devs[index].endp[epno];
2807 pepext->page_cache = pc;
2808 pepext->trb = buf_ep.buffer;
2809 pepext->physaddr = buf_ep.physaddr;
2810
2811 return (pepext);
2812 }
2813
2814 static void
xhci_endpoint_doorbell(struct usb_xfer * xfer)2815 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2816 {
2817 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2818 uint8_t epno;
2819 uint8_t index;
2820
2821 epno = xfer->endpointno;
2822 if (xfer->flags_int.control_xfr)
2823 epno |= UE_DIR_IN;
2824
2825 epno = XHCI_EPNO2EPID(epno);
2826 index = xfer->xroot->udev->controller_slot_id;
2827
2828 if (xfer->xroot->udev->flags.self_suspended == 0) {
2829 XWRITE4(sc, door, XHCI_DOORBELL(index),
2830 epno | XHCI_DB_SID_SET(xfer->stream_id));
2831 }
2832 }
2833
2834 static void
xhci_transfer_remove(struct usb_xfer * xfer,usb_error_t error)2835 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2836 {
2837 struct xhci_endpoint_ext *pepext;
2838
2839 if (xfer->flags_int.bandwidth_reclaimed) {
2840 xfer->flags_int.bandwidth_reclaimed = 0;
2841
2842 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2843 xfer->endpoint->edesc);
2844
2845 pepext->trb_used[xfer->stream_id]--;
2846
2847 pepext->xfer[xfer->qh_pos] = NULL;
2848
2849 if (error && (pepext->trb_running != 0)) {
2850 pepext->trb_halted = 1;
2851 pepext->trb_running = 0;
2852 }
2853 }
2854 }
2855
2856 static usb_error_t
xhci_transfer_insert(struct usb_xfer * xfer)2857 xhci_transfer_insert(struct usb_xfer *xfer)
2858 {
2859 struct xhci_td *td_first;
2860 struct xhci_td *td_last;
2861 struct xhci_trb *trb_link;
2862 struct xhci_endpoint_ext *pepext;
2863 uint64_t addr;
2864 usb_stream_t id;
2865 uint8_t i;
2866 uint8_t inext;
2867 uint8_t trb_limit;
2868
2869 DPRINTFN(8, "\n");
2870
2871 id = xfer->stream_id;
2872
2873 /* check if already inserted */
2874 if (xfer->flags_int.bandwidth_reclaimed) {
2875 DPRINTFN(8, "Already in schedule\n");
2876 return (USB_ERR_NORMAL_COMPLETION);
2877 }
2878
2879 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2880 xfer->endpoint->edesc);
2881
2882 td_first = xfer->td_transfer_first;
2883 td_last = xfer->td_transfer_last;
2884 addr = pepext->physaddr;
2885
2886 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2887 case UE_CONTROL:
2888 case UE_INTERRUPT:
2889 /* single buffered */
2890 trb_limit = 1;
2891 break;
2892 default:
2893 /* multi buffered */
2894 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2895 break;
2896 }
2897
2898 if (pepext->trb_used[id] >= trb_limit) {
2899 DPRINTFN(8, "Too many TDs queued.\n");
2900 return (USB_ERR_NOMEM);
2901 }
2902
2903 /* check if bMaxPacketSize changed */
2904 if (xfer->flags_int.control_xfr != 0 &&
2905 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2906
2907 DPRINTFN(8, "Reconfigure control endpoint\n");
2908
2909 /* force driver to reconfigure endpoint */
2910 pepext->trb_halted = 1;
2911 pepext->trb_running = 0;
2912 }
2913
2914 /* check for stopped condition, after putting transfer on interrupt queue */
2915 if (pepext->trb_running == 0) {
2916 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2917
2918 DPRINTFN(8, "Not running\n");
2919
2920 /* start configuration */
2921 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2922 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2923 return (USB_ERR_NORMAL_COMPLETION);
2924 }
2925
2926 pepext->trb_used[id]++;
2927
2928 /* get current TRB index */
2929 i = pepext->trb_index[id];
2930
2931 /* get next TRB index */
2932 inext = (i + 1);
2933
2934 /* the last entry of the ring is a hardcoded link TRB */
2935 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2936 inext = 0;
2937
2938 /* store next TRB index, before stream ID offset is added */
2939 pepext->trb_index[id] = inext;
2940
2941 /* offset for stream */
2942 i += id * XHCI_MAX_TRANSFERS;
2943 inext += id * XHCI_MAX_TRANSFERS;
2944
2945 /* compute terminating return address */
2946 addr += (inext * sizeof(struct xhci_trb));
2947
2948 /* compute link TRB pointer */
2949 trb_link = td_last->td_trb + td_last->ntrb;
2950
2951 /* update next pointer of last link TRB */
2952 trb_link->qwTrb0 = htole64(addr);
2953 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2954 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2955 XHCI_TRB_3_CYCLE_BIT |
2956 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2957
2958 #ifdef USB_DEBUG
2959 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2960 #endif
2961 usb_pc_cpu_flush(td_last->page_cache);
2962
2963 /* write ahead chain end marker */
2964
2965 pepext->trb[inext].qwTrb0 = 0;
2966 pepext->trb[inext].dwTrb2 = 0;
2967 pepext->trb[inext].dwTrb3 = 0;
2968
2969 /* update next pointer of link TRB */
2970
2971 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2972 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2973
2974 #ifdef USB_DEBUG
2975 xhci_dump_trb(&pepext->trb[i]);
2976 #endif
2977 usb_pc_cpu_flush(pepext->page_cache);
2978
2979 /* toggle cycle bit which activates the transfer chain */
2980
2981 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2982 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2983
2984 usb_pc_cpu_flush(pepext->page_cache);
2985
2986 DPRINTF("qh_pos = %u\n", i);
2987
2988 pepext->xfer[i] = xfer;
2989
2990 xfer->qh_pos = i;
2991
2992 xfer->flags_int.bandwidth_reclaimed = 1;
2993
2994 xhci_endpoint_doorbell(xfer);
2995
2996 return (USB_ERR_NORMAL_COMPLETION);
2997 }
2998
2999 static void
xhci_root_intr(struct xhci_softc * sc)3000 xhci_root_intr(struct xhci_softc *sc)
3001 {
3002 uint16_t i;
3003
3004 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3005
3006 /* clear any old interrupt data */
3007 (void)memset_s(sc->sc_hub_idata, sizeof(sc->sc_hub_idata), 0, sizeof(sc->sc_hub_idata));
3008
3009 for (i = 1; i <= sc->sc_noport; i++) {
3010 /* pick out CHANGE bits from the status register */
3011 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3012 XHCI_PS_CSC | XHCI_PS_PEC |
3013 XHCI_PS_OCC | XHCI_PS_WRC |
3014 XHCI_PS_PRC | XHCI_PS_PLC |
3015 XHCI_PS_CEC)) {
3016 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3017 DPRINTF("port %d changed\n", i);
3018 }
3019 }
3020 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3021 sizeof(sc->sc_hub_idata));
3022 }
3023
3024 /*------------------------------------------------------------------------*
3025 * xhci_device_done - XHCI done handler
3026 *
3027 * NOTE: This function can be called two times in a row on
3028 * the same USB transfer. From close and from interrupt.
3029 *------------------------------------------------------------------------*/
3030 static void
xhci_device_done(struct usb_xfer * xfer,usb_error_t error)3031 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3032 {
3033 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3034 xfer, xfer->endpoint, error);
3035
3036 /* remove transfer from HW queue */
3037 xhci_transfer_remove(xfer, error);
3038
3039 /* dequeue transfer and start next transfer */
3040 usbd_transfer_done(xfer, error);
3041 }
3042
3043 /*------------------------------------------------------------------------*
3044 * XHCI data transfer support (generic type)
3045 *------------------------------------------------------------------------*/
3046 static void
xhci_device_generic_open(struct usb_xfer * xfer)3047 xhci_device_generic_open(struct usb_xfer *xfer)
3048 {
3049 if (xfer->flags_int.isochronous_xfr) {
3050 switch (xfer->xroot->udev->speed) {
3051 case USB_SPEED_FULL:
3052 break;
3053 default:
3054 usb_hs_bandwidth_alloc(xfer);
3055 break;
3056 }
3057 }
3058 }
3059
3060 static void
xhci_device_generic_close(struct usb_xfer * xfer)3061 xhci_device_generic_close(struct usb_xfer *xfer)
3062 {
3063 DPRINTF("\n");
3064
3065 xhci_device_done(xfer, USB_ERR_CANCELLED);
3066
3067 if (xfer->flags_int.isochronous_xfr) {
3068 switch (xfer->xroot->udev->speed) {
3069 case USB_SPEED_FULL:
3070 break;
3071 default:
3072 usb_hs_bandwidth_free(xfer);
3073 break;
3074 }
3075 }
3076 }
3077
3078 static void
xhci_device_generic_multi_enter(struct usb_endpoint * ep,usb_stream_t stream_id,struct usb_xfer * enter_xfer)3079 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3080 usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3081 {
3082 struct usb_xfer *xfer;
3083
3084 /* check if there is a current transfer */
3085 xfer = ep->endpoint_q[stream_id].curr;
3086 if (xfer == NULL)
3087 return;
3088
3089 /*
3090 * Check if the current transfer is started and then pickup
3091 * the next one, if any. Else wait for next start event due to
3092 * block on failure feature.
3093 */
3094 if (!xfer->flags_int.bandwidth_reclaimed)
3095 return;
3096
3097 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3098 if (xfer == NULL) {
3099 /*
3100 * In case of enter we have to consider that the
3101 * transfer is queued by the USB core after the enter
3102 * method is called.
3103 */
3104 xfer = enter_xfer;
3105
3106 if (xfer == NULL)
3107 return;
3108 }
3109
3110 /* try to multi buffer */
3111 (void)xhci_transfer_insert(xfer);
3112 }
3113
3114 static void
xhci_device_generic_enter(struct usb_xfer * xfer)3115 xhci_device_generic_enter(struct usb_xfer *xfer)
3116 {
3117 DPRINTF("\n");
3118
3119 /* set up TD's and QH */
3120 xhci_setup_generic_chain(xfer);
3121
3122 xhci_device_generic_multi_enter(xfer->endpoint,
3123 xfer->stream_id, xfer);
3124 }
3125
3126 static void
xhci_device_generic_start(struct usb_xfer * xfer)3127 xhci_device_generic_start(struct usb_xfer *xfer)
3128 {
3129 DPRINTF("\n");
3130
3131 /* try to insert xfer on HW queue */
3132 (void)xhci_transfer_insert(xfer);
3133
3134 /* try to multi buffer */
3135 xhci_device_generic_multi_enter(xfer->endpoint,
3136 xfer->stream_id, NULL);
3137
3138 /* add transfer last on interrupt queue */
3139 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3140
3141 /* start timeout, if any */
3142 if (xfer->timeout != 0)
3143 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3144 }
3145
3146 struct usb_pipe_methods xhci_device_generic_methods = {
3147 .open = xhci_device_generic_open,
3148 .close = xhci_device_generic_close,
3149 .enter = xhci_device_generic_enter,
3150 .start = xhci_device_generic_start,
3151 };
3152
3153 /*------------------------------------------------------------------------*
3154 * xhci root HUB support
3155 *------------------------------------------------------------------------*
3156 * Simulate a hardware HUB by handling all the necessary requests.
3157 *------------------------------------------------------------------------*/
3158
3159 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3160
3161 static const
3162 struct usb_device_descriptor xhci_devd = {
3163 .bLength = sizeof(xhci_devd),
3164 .bDescriptorType = UDESC_DEVICE, /* type */
3165 HSETW(.bcdUSB, 0x0300), /* USB version */
3166 .bDeviceClass = UDCLASS_HUB, /* class */
3167 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3168 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3169 .bMaxPacketSize = 9, /* max packet size */
3170 HSETW(.idVendor, 0x0000), /* vendor */
3171 HSETW(.idProduct, 0x0000), /* product */
3172 HSETW(.bcdDevice, 0x0100), /* device version */
3173 .iManufacturer = 1,
3174 .iProduct = 2,
3175 .iSerialNumber = 0,
3176 .bNumConfigurations = 1, /* # of configurations */
3177 };
3178
3179 static const
3180 struct xhci_bos_desc xhci_bosd = {
3181 .bosd = {
3182 .bLength = sizeof(xhci_bosd.bosd),
3183 .bDescriptorType = UDESC_BOS,
3184 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3185 .bNumDeviceCaps = 3,
3186 },
3187 .usb2extd = {
3188 .bLength = sizeof(xhci_bosd.usb2extd),
3189 .bDescriptorType = 1,
3190 .bDevCapabilityType = 2,
3191 .bmAttributes[0] = 2,
3192 },
3193 .usbdcd = {
3194 .bLength = sizeof(xhci_bosd.usbdcd),
3195 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3196 .bDevCapabilityType = 3,
3197 .bmAttributes = 0,
3198 HSETW(.wSpeedsSupported, 0x000C),
3199 .bFunctionalitySupport = 8,
3200 .bU1DevExitLat = 255, /* dummy - not used */
3201 .wU2DevExitLat = { 0x00, 0x08 },
3202 },
3203 .cidd = {
3204 .bLength = sizeof(xhci_bosd.cidd),
3205 .bDescriptorType = 1,
3206 .bDevCapabilityType = 4,
3207 .bReserved = 0,
3208 .bContainerID = 0,
3209 },
3210 };
3211
3212 static const
3213 struct xhci_config_desc xhci_confd = {
3214 .confd = {
3215 .bLength = sizeof(xhci_confd.confd),
3216 .bDescriptorType = UDESC_CONFIG,
3217 .wTotalLength[0] = sizeof(xhci_confd),
3218 .bNumInterface = 1,
3219 .bConfigurationValue = 1,
3220 .iConfiguration = 0,
3221 .bmAttributes = UC_SELF_POWERED,
3222 .bMaxPower = 0 /* max power */
3223 },
3224 .ifcd = {
3225 .bLength = sizeof(xhci_confd.ifcd),
3226 .bDescriptorType = UDESC_INTERFACE,
3227 .bNumEndpoints = 1,
3228 .bInterfaceClass = UICLASS_HUB,
3229 .bInterfaceSubClass = UISUBCLASS_HUB,
3230 .bInterfaceProtocol = 0,
3231 },
3232 .endpd = {
3233 .bLength = sizeof(xhci_confd.endpd),
3234 .bDescriptorType = UDESC_ENDPOINT,
3235 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3236 .bmAttributes = UE_INTERRUPT,
3237 .wMaxPacketSize[0] = 2, /* max 15 ports */
3238 .bInterval = 255,
3239 },
3240 .endpcd = {
3241 .bLength = sizeof(xhci_confd.endpcd),
3242 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3243 .bMaxBurst = 0,
3244 .bmAttributes = 0,
3245 },
3246 };
3247
3248 static const
3249 struct usb_hub_ss_descriptor xhci_hubd = {
3250 .bLength = sizeof(xhci_hubd),
3251 .bDescriptorType = UDESC_SS_HUB,
3252 };
3253
3254 static usb_error_t
xhci_roothub_exec(struct usb_device * udev,struct usb_device_request * req,const void ** pptr,uint16_t * plength)3255 xhci_roothub_exec(struct usb_device *udev,
3256 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3257 {
3258 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3259 const char *str_ptr;
3260 const void *ptr;
3261 uint32_t port;
3262 uint32_t v;
3263 uint16_t len;
3264 uint16_t i;
3265 uint16_t value;
3266 uint16_t index;
3267 uint8_t j;
3268 usb_error_t err;
3269
3270 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3271
3272 /* buffer reset */
3273 ptr = (const void *)&sc->sc_hub_desc;
3274 len = 0;
3275 err = USB_ERR_NORMAL_COMPLETION;
3276
3277 value = UGETW(req->wValue);
3278 index = UGETW(req->wIndex);
3279
3280 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3281 "wValue=0x%04x wIndex=0x%04x\n",
3282 req->bmRequestType, req->bRequest,
3283 UGETW(req->wLength), value, index);
3284
3285 #define C(x,y) ((x) | ((y) << 8))
3286 switch (C(req->bRequest, req->bmRequestType)) {
3287 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3288 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3289 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3290 /*
3291 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3292 * for the integrated root hub.
3293 */
3294 break;
3295 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3296 len = 1;
3297 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3298 break;
3299 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3300 switch (value >> 8) {
3301 case UDESC_DEVICE:
3302 if ((value & 0xff) != 0) {
3303 err = USB_ERR_IOERROR;
3304 goto done;
3305 }
3306 len = sizeof(xhci_devd);
3307 ptr = (const void *)&xhci_devd;
3308 break;
3309
3310 case UDESC_BOS:
3311 if ((value & 0xff) != 0) {
3312 err = USB_ERR_IOERROR;
3313 goto done;
3314 }
3315 len = sizeof(xhci_bosd);
3316 ptr = (const void *)&xhci_bosd;
3317 break;
3318
3319 case UDESC_CONFIG:
3320 if ((value & 0xff) != 0) {
3321 err = USB_ERR_IOERROR;
3322 goto done;
3323 }
3324 len = sizeof(xhci_confd);
3325 ptr = (const void *)&xhci_confd;
3326 break;
3327
3328 case UDESC_STRING:
3329 switch (value & 0xff) {
3330 case 0: /* Language table */
3331 str_ptr = "\001";
3332 break;
3333
3334 case 1: /* Vendor */
3335 str_ptr = sc->sc_vendor;
3336 break;
3337
3338 case 2: /* Product */
3339 str_ptr = "XHCI root HUB";
3340 break;
3341
3342 default:
3343 str_ptr = "";
3344 break;
3345 }
3346
3347 len = usb_make_str_desc(
3348 sc->sc_hub_desc.temp,
3349 sizeof(sc->sc_hub_desc.temp),
3350 str_ptr);
3351 break;
3352
3353 default:
3354 err = USB_ERR_IOERROR;
3355 goto done;
3356 }
3357 break;
3358 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3359 len = 1;
3360 sc->sc_hub_desc.temp[0] = 0;
3361 break;
3362 case C(UR_GET_STATUS, UT_READ_DEVICE):
3363 len = 2;
3364 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3365 break;
3366 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3367 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3368 len = 2;
3369 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3370 break;
3371 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3372 if (value >= XHCI_MAX_DEVICES) {
3373 err = USB_ERR_IOERROR;
3374 goto done;
3375 }
3376 break;
3377 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3378 if ((value != 0) && (value != 1)) {
3379 err = USB_ERR_IOERROR;
3380 goto done;
3381 }
3382 sc->sc_conf = value;
3383 break;
3384 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3385 break;
3386 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3387 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3388 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3389 err = USB_ERR_IOERROR;
3390 goto done;
3391 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3392 break;
3393 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3394 break;
3395 /* Hub requests */
3396 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3397 break;
3398 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3399 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3400
3401 if ((index < 1) ||
3402 (index > sc->sc_noport)) {
3403 err = USB_ERR_IOERROR;
3404 goto done;
3405 }
3406 port = XHCI_PORTSC(index);
3407
3408 v = XREAD4(sc, oper, port);
3409 i = XHCI_PS_PLS_GET(v);
3410 v &= ~XHCI_PS_CLEAR;
3411
3412 switch (value) {
3413 case UHF_C_BH_PORT_RESET:
3414 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3415 break;
3416 case UHF_C_PORT_CONFIG_ERROR:
3417 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3418 break;
3419 case UHF_C_PORT_SUSPEND:
3420 case UHF_C_PORT_LINK_STATE:
3421 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3422 break;
3423 case UHF_C_PORT_CONNECTION:
3424 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3425 break;
3426 case UHF_C_PORT_ENABLE:
3427 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3428 break;
3429 case UHF_C_PORT_OVER_CURRENT:
3430 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3431 break;
3432 case UHF_C_PORT_RESET:
3433 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3434 break;
3435 case UHF_PORT_ENABLE:
3436 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3437 break;
3438 case UHF_PORT_POWER:
3439 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3440 break;
3441 case UHF_PORT_INDICATOR:
3442 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3443 break;
3444 case UHF_PORT_SUSPEND:
3445
3446 /* U3 -> U15 */
3447 if (i == 3) {
3448 XWRITE4(sc, oper, port, v |
3449 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3450 }
3451
3452 /* wait 20ms for resume sequence to complete */
3453 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3454
3455 /* U0 */
3456 XWRITE4(sc, oper, port, v |
3457 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3458 break;
3459 default:
3460 err = USB_ERR_IOERROR;
3461 goto done;
3462 }
3463 break;
3464
3465 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3466 if ((value & 0xff) != 0) {
3467 err = USB_ERR_IOERROR;
3468 goto done;
3469 }
3470
3471 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3472
3473 sc->sc_hub_desc.hubd = xhci_hubd;
3474
3475 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3476
3477 if (XHCI_HCS0_PPC(v))
3478 i = UHD_PWR_INDIVIDUAL;
3479 else
3480 i = UHD_PWR_GANGED;
3481
3482 if (XHCI_HCS0_PIND(v))
3483 i |= UHD_PORT_IND;
3484
3485 i |= UHD_OC_INDIVIDUAL;
3486
3487 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3488
3489 /* see XHCI section 5.4.9: */
3490 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3491
3492 for (j = 1; j <= sc->sc_noport; j++) {
3493
3494 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3495 if (v & XHCI_PS_DR) {
3496 sc->sc_hub_desc.hubd.
3497 DeviceRemovable[j / 8] |= 1U << (j % 8);
3498 }
3499 }
3500 len = sc->sc_hub_desc.hubd.bLength;
3501 break;
3502
3503 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3504 len = 16;
3505 (void)memset_s(sc->sc_hub_desc.temp, sizeof(sc->sc_hub_desc.temp), 0, len);
3506 break;
3507
3508 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3509 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3510
3511 if ((index < 1) ||
3512 (index > sc->sc_noport)) {
3513 err = USB_ERR_IOERROR;
3514 goto done;
3515 }
3516
3517 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3518
3519 DPRINTFN(9, "port status=0x%08x\n", v);
3520
3521 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3522
3523 switch (XHCI_PS_SPEED_GET(v)) {
3524 case 3:
3525 i |= UPS_HIGH_SPEED;
3526 break;
3527 case 2:
3528 i |= UPS_LOW_SPEED;
3529 break;
3530 case 1:
3531 /* FULL speed */
3532 break;
3533 default:
3534 i |= UPS_OTHER_SPEED;
3535 break;
3536 }
3537
3538 if (v & XHCI_PS_CCS)
3539 i |= UPS_CURRENT_CONNECT_STATUS;
3540 if (v & XHCI_PS_PED)
3541 i |= UPS_PORT_ENABLED;
3542 if (v & XHCI_PS_OCA)
3543 i |= UPS_OVERCURRENT_INDICATOR;
3544 if (v & XHCI_PS_PR)
3545 i |= UPS_RESET;
3546 if (v & XHCI_PS_PP) {
3547 /*
3548 * The USB 3.0 RH is using the
3549 * USB 2.0's power bit
3550 */
3551 i |= UPS_PORT_POWER;
3552 }
3553 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3554
3555 i = 0;
3556 if (v & XHCI_PS_CSC)
3557 i |= UPS_C_CONNECT_STATUS;
3558 if (v & XHCI_PS_PEC)
3559 i |= UPS_C_PORT_ENABLED;
3560 if (v & XHCI_PS_OCC)
3561 i |= UPS_C_OVERCURRENT_INDICATOR;
3562 if (v & XHCI_PS_WRC)
3563 i |= UPS_C_BH_PORT_RESET;
3564 if (v & XHCI_PS_PRC)
3565 i |= UPS_C_PORT_RESET;
3566 if (v & XHCI_PS_PLC)
3567 i |= UPS_C_PORT_LINK_STATE;
3568 if (v & XHCI_PS_CEC)
3569 i |= UPS_C_PORT_CONFIG_ERROR;
3570
3571 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3572 len = sizeof(sc->sc_hub_desc.ps);
3573 break;
3574
3575 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3576 err = USB_ERR_IOERROR;
3577 goto done;
3578
3579 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3580 break;
3581
3582 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3583
3584 i = index >> 8;
3585 index &= 0x00FF;
3586
3587 if ((index < 1) ||
3588 (index > sc->sc_noport)) {
3589 err = USB_ERR_IOERROR;
3590 goto done;
3591 }
3592
3593 port = XHCI_PORTSC(index);
3594 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3595
3596 switch (value) {
3597 case UHF_PORT_U1_TIMEOUT:
3598 if (XHCI_PS_SPEED_GET(v) != 4) {
3599 err = USB_ERR_IOERROR;
3600 goto done;
3601 }
3602 port = XHCI_PORTPMSC(index);
3603 v = XREAD4(sc, oper, port);
3604 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3605 v |= XHCI_PM3_U1TO_SET(i);
3606 XWRITE4(sc, oper, port, v);
3607 break;
3608 case UHF_PORT_U2_TIMEOUT:
3609 if (XHCI_PS_SPEED_GET(v) != 4) {
3610 err = USB_ERR_IOERROR;
3611 goto done;
3612 }
3613 port = XHCI_PORTPMSC(index);
3614 v = XREAD4(sc, oper, port);
3615 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3616 v |= XHCI_PM3_U2TO_SET(i);
3617 XWRITE4(sc, oper, port, v);
3618 break;
3619 case UHF_BH_PORT_RESET:
3620 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3621 break;
3622 case UHF_PORT_LINK_STATE:
3623 XWRITE4(sc, oper, port, v |
3624 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3625 /* 4ms settle time */
3626 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3627 break;
3628 case UHF_PORT_ENABLE:
3629 DPRINTFN(3, "set port enable %d\n", index);
3630 break;
3631 case UHF_PORT_SUSPEND:
3632 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3633 j = XHCI_PS_SPEED_GET(v);
3634 if ((j < 1) || (j > 3)) {
3635 /* non-supported speed */
3636 err = USB_ERR_IOERROR;
3637 goto done;
3638 }
3639 XWRITE4(sc, oper, port, v |
3640 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3641 break;
3642 case UHF_PORT_RESET:
3643 DPRINTFN(6, "reset port %d\n", index);
3644 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3645 break;
3646 case UHF_PORT_POWER:
3647 DPRINTFN(3, "set port power %d\n", index);
3648 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3649 break;
3650 case UHF_PORT_TEST:
3651 DPRINTFN(3, "set port test %d\n", index);
3652 break;
3653 case UHF_PORT_INDICATOR:
3654 DPRINTFN(3, "set port indicator %d\n", index);
3655
3656 v &= ~XHCI_PS_PIC_SET(3);
3657 v |= XHCI_PS_PIC_SET(1);
3658
3659 XWRITE4(sc, oper, port, v);
3660 break;
3661 default:
3662 err = USB_ERR_IOERROR;
3663 goto done;
3664 }
3665 break;
3666
3667 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3668 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3669 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3670 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3671 break;
3672 default:
3673 err = USB_ERR_IOERROR;
3674 goto done;
3675 }
3676 done:
3677 *plength = len;
3678 *pptr = ptr;
3679 return (err);
3680 }
3681
3682 static void
xhci_xfer_setup(struct usb_setup_params * parm)3683 xhci_xfer_setup(struct usb_setup_params *parm)
3684 {
3685 struct usb_page_search page_info;
3686 struct usb_page_cache *pc;
3687 struct usb_xfer *xfer;
3688 void *last_obj;
3689 uint32_t ntd;
3690 uint32_t n;
3691
3692 xfer = parm->curr_xfer;
3693
3694 /*
3695 * The proof for the "ntd" formula is illustrated like this:
3696 *
3697 * +------------------------------------+
3698 * | |
3699 * | |remainder -> |
3700 * | +-----+---+ |
3701 * | | xxx | x | frm 0 |
3702 * | +-----+---++ |
3703 * | | xxx | xx | frm 1 |
3704 * | +-----+----+ |
3705 * | ... |
3706 * +------------------------------------+
3707 *
3708 * "xxx" means a completely full USB transfer descriptor
3709 *
3710 * "x" and "xx" means a short USB packet
3711 *
3712 * For the remainder of an USB transfer modulo
3713 * "max_data_length" we need two USB transfer descriptors.
3714 * One to transfer the remaining data and one to finalise with
3715 * a zero length packet in case the "force_short_xfer" flag is
3716 * set. We only need two USB transfer descriptors in the case
3717 * where the transfer length of the first one is a factor of
3718 * "max_frame_size". The rest of the needed USB transfer
3719 * descriptors is given by the buffer size divided by the
3720 * maximum data payload.
3721 */
3722 parm->hc_max_packet_size = 0x400;
3723 parm->hc_max_packet_count = 16 * 3;
3724 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3725
3726 xfer->flags_int.bdma_enable = 1;
3727
3728 usbd_transfer_setup_sub(parm);
3729
3730 if (xfer->flags_int.isochronous_xfr) {
3731 ntd = ((1 * xfer->nframes)
3732 + (xfer->max_data_length / xfer->max_hc_frame_size));
3733 } else if (xfer->flags_int.control_xfr) {
3734 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3735 + (xfer->max_data_length / xfer->max_hc_frame_size));
3736 } else {
3737 ntd = ((2 * xfer->nframes)
3738 + (xfer->max_data_length / xfer->max_hc_frame_size));
3739 }
3740
3741 alloc_dma_set:
3742
3743 if (parm->err)
3744 return;
3745
3746 /*
3747 * Allocate queue heads and transfer descriptors
3748 */
3749 last_obj = NULL;
3750
3751 if (usbd_transfer_setup_sub_malloc(
3752 parm, &pc, sizeof(struct xhci_td),
3753 XHCI_TD_ALIGN, ntd)) {
3754 parm->err = USB_ERR_NOMEM;
3755 return;
3756 }
3757 if (parm->buf) {
3758 for (n = 0; n != ntd; n++) {
3759 struct xhci_td *td;
3760
3761 usbd_get_page(pc + n, 0, &page_info);
3762
3763 td = page_info.buffer;
3764
3765 /* init TD */
3766 td->td_self = page_info.physaddr;
3767 td->obj_next = last_obj;
3768 td->page_cache = pc + n;
3769
3770 last_obj = td;
3771
3772 usb_pc_cpu_flush(pc + n);
3773 }
3774 }
3775 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3776
3777 if (!xfer->flags_int.curr_dma_set) {
3778 xfer->flags_int.curr_dma_set = 1;
3779 goto alloc_dma_set;
3780 }
3781 }
3782
3783 static usb_error_t
xhci_configure_reset_endpoint(struct usb_xfer * xfer)3784 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3785 {
3786 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3787 struct usb_page_search buf_inp;
3788 struct usb_device *udev;
3789 struct xhci_endpoint_ext *pepext;
3790 struct usb_endpoint_descriptor *edesc;
3791 struct usb_page_cache *pcinp;
3792 usb_error_t err;
3793 usb_stream_t stream_id;
3794 uint8_t index;
3795 uint8_t epno;
3796
3797 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3798 xfer->endpoint->edesc);
3799
3800 udev = xfer->xroot->udev;
3801 index = udev->controller_slot_id;
3802
3803 pcinp = &sc->sc_hw.devs[index].input_pc;
3804
3805 usbd_get_page(pcinp, 0, &buf_inp);
3806
3807 edesc = xfer->endpoint->edesc;
3808
3809 epno = edesc->bEndpointAddress;
3810 stream_id = xfer->stream_id;
3811
3812 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3813 epno |= UE_DIR_IN;
3814
3815 epno = XHCI_EPNO2EPID(epno);
3816
3817 if (epno == 0)
3818 return (USB_ERR_NO_PIPE); /* invalid */
3819
3820 XHCI_CMD_LOCK(sc);
3821
3822 /* configure endpoint */
3823
3824 err = xhci_configure_endpoint_by_xfer(xfer);
3825
3826 if (err != 0) {
3827 XHCI_CMD_UNLOCK(sc);
3828 return (err);
3829 }
3830
3831 /*
3832 * Get the endpoint into the stopped state according to the
3833 * endpoint context state diagram in the XHCI specification:
3834 */
3835
3836 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3837
3838 if (err != 0)
3839 DPRINTF("Could not stop endpoint %u\n", epno);
3840
3841 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3842
3843 if (err != 0)
3844 DPRINTF("Could not reset endpoint %u\n", epno);
3845
3846 err = xhci_cmd_set_tr_dequeue_ptr(sc,
3847 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3848 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3849 stream_id, epno, index);
3850
3851 if (err != 0)
3852 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3853
3854 /*
3855 * Get the endpoint into the running state according to the
3856 * endpoint context state diagram in the XHCI specification:
3857 */
3858
3859 (void)xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3860
3861 if (epno > 1)
3862 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3863 else
3864 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3865
3866 if (err != 0)
3867 DPRINTF("Could not configure endpoint %u\n", epno);
3868
3869 XHCI_CMD_UNLOCK(sc);
3870
3871 return (USB_ERR_NORMAL_COMPLETION);
3872 }
3873
3874 static void
xhci_xfer_unsetup(struct usb_xfer * xfer)3875 xhci_xfer_unsetup(struct usb_xfer *xfer)
3876 {
3877 return;
3878 }
3879
3880 static void
xhci_start_dma_delay(struct usb_xfer * xfer)3881 xhci_start_dma_delay(struct usb_xfer *xfer)
3882 {
3883 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3884
3885 /* put transfer on interrupt queue (again) */
3886 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3887
3888 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3889 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3890 }
3891
3892 static void
xhci_configure_msg(struct usb_proc_msg * pm)3893 xhci_configure_msg(struct usb_proc_msg *pm)
3894 {
3895 struct xhci_softc *sc;
3896 struct xhci_endpoint_ext *pepext;
3897 struct usb_xfer *xfer;
3898
3899 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3900
3901 restart:
3902 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3903
3904 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3905 xfer->endpoint->edesc);
3906
3907 if ((pepext->trb_halted != 0) ||
3908 (pepext->trb_running == 0)) {
3909
3910 uint16_t i;
3911
3912 /* clear halted and running */
3913 pepext->trb_halted = 0;
3914 pepext->trb_running = 0;
3915
3916 /* nuke remaining buffered transfers */
3917
3918 for (i = 0; i != (XHCI_MAX_TRANSFERS *
3919 XHCI_MAX_STREAMS); i++) {
3920 /*
3921 * NOTE: We need to use the timeout
3922 * error code here else existing
3923 * isochronous clients can get
3924 * confused:
3925 */
3926 if (pepext->xfer[i] != NULL) {
3927 xhci_device_done(pepext->xfer[i],
3928 USB_ERR_TIMEOUT);
3929 }
3930 }
3931
3932 /*
3933 * NOTE: The USB transfer cannot vanish in
3934 * this state!
3935 */
3936
3937 USB_BUS_UNLOCK(&sc->sc_bus);
3938
3939 (void)xhci_configure_reset_endpoint(xfer);
3940
3941 USB_BUS_LOCK(&sc->sc_bus);
3942
3943 /* check if halted is still cleared */
3944 if (pepext->trb_halted == 0) {
3945 pepext->trb_running = 1;
3946 (void)memset_s(pepext->trb_index, sizeof(pepext->trb_index),
3947 0, sizeof(pepext->trb_index));
3948 }
3949 goto restart;
3950 }
3951
3952 if (xfer->flags_int.did_dma_delay) {
3953
3954 /* remove transfer from interrupt queue (again) */
3955 usbd_transfer_dequeue(xfer);
3956
3957 /* we are finally done */
3958 usb_dma_delay_done_cb(xfer);
3959
3960 /* queue changed - restart */
3961 goto restart;
3962 }
3963 }
3964
3965 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3966
3967 /* try to insert xfer on HW queue */
3968 (void)xhci_transfer_insert(xfer);
3969
3970 /* try to multi buffer */
3971 xhci_device_generic_multi_enter(xfer->endpoint,
3972 xfer->stream_id, NULL);
3973 }
3974 }
3975
3976 static void
xhci_ep_init(struct usb_device * udev,struct usb_endpoint_descriptor * edesc,struct usb_endpoint * ep)3977 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3978 struct usb_endpoint *ep)
3979 {
3980 struct xhci_endpoint_ext *pepext;
3981
3982 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3983 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3984
3985 if (udev->parent_hub == NULL) {
3986 /* root HUB has special endpoint handling */
3987 return;
3988 }
3989
3990 ep->methods = &xhci_device_generic_methods;
3991
3992 pepext = xhci_get_endpoint_ext(udev, edesc);
3993
3994 USB_BUS_LOCK(udev->bus);
3995 pepext->trb_halted = 1;
3996 pepext->trb_running = 0;
3997 USB_BUS_UNLOCK(udev->bus);
3998 }
3999
4000 static void
xhci_ep_uninit(struct usb_device * udev,struct usb_endpoint * ep)4001 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4002 {
4003
4004 }
4005
4006 static void
xhci_ep_clear_stall(struct usb_device * udev,struct usb_endpoint * ep)4007 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4008 {
4009 struct xhci_endpoint_ext *pepext;
4010
4011 DPRINTF("\n");
4012
4013 if (udev->flags.usb_mode != USB_MODE_HOST) {
4014 /* not supported */
4015 return;
4016 }
4017 if (udev->parent_hub == NULL) {
4018 /* root HUB has special endpoint handling */
4019 return;
4020 }
4021
4022 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4023
4024 USB_BUS_LOCK(udev->bus);
4025 pepext->trb_halted = 1;
4026 pepext->trb_running = 0;
4027 USB_BUS_UNLOCK(udev->bus);
4028 }
4029
4030 static usb_error_t
xhci_device_init(struct usb_device * udev)4031 xhci_device_init(struct usb_device *udev)
4032 {
4033 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4034 usb_error_t err;
4035 uint8_t temp;
4036
4037 /* no init for root HUB */
4038 if (udev->parent_hub == NULL)
4039 return (USB_ERR_NORMAL_COMPLETION);
4040
4041 XHCI_CMD_LOCK(sc);
4042
4043 /* set invalid default */
4044
4045 udev->controller_slot_id = sc->sc_noslot + 1;
4046
4047 /* try to get a new slot ID from the XHCI */
4048
4049 err = xhci_cmd_enable_slot(sc, &temp);
4050
4051 if (err) {
4052 XHCI_CMD_UNLOCK(sc);
4053 return (err);
4054 }
4055
4056 if (temp > sc->sc_noslot) {
4057 XHCI_CMD_UNLOCK(sc);
4058 return (USB_ERR_BAD_ADDRESS);
4059 }
4060
4061 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4062 DPRINTF("slot %u already allocated.\n", temp);
4063 XHCI_CMD_UNLOCK(sc);
4064 return (USB_ERR_BAD_ADDRESS);
4065 }
4066
4067 /* store slot ID for later reference */
4068
4069 udev->controller_slot_id = temp;
4070
4071 /* reset data structure */
4072
4073 (void)memset_s(&sc->sc_hw.devs[temp], sizeof(sc->sc_hw.devs[0]), 0, sizeof(sc->sc_hw.devs[0]));
4074
4075 /* set mark slot allocated */
4076
4077 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4078
4079 err = xhci_alloc_device_ext(udev);
4080
4081 XHCI_CMD_UNLOCK(sc);
4082
4083 /* get device into default state */
4084
4085 if (err == 0)
4086 err = xhci_set_address(udev, NULL, 0);
4087
4088 return (err);
4089 }
4090
4091 static void
xhci_device_uninit(struct usb_device * udev)4092 xhci_device_uninit(struct usb_device *udev)
4093 {
4094 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4095 uint8_t index;
4096
4097 /* no init for root HUB */
4098 if (udev->parent_hub == NULL)
4099 return;
4100
4101 XHCI_CMD_LOCK(sc);
4102
4103 index = udev->controller_slot_id;
4104
4105 if (index <= sc->sc_noslot) {
4106 (void)xhci_cmd_disable_slot(sc, index);
4107 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4108
4109 /* free device extension */
4110 xhci_free_device_ext(udev);
4111 }
4112
4113 XHCI_CMD_UNLOCK(sc);
4114 }
4115
4116 static void
xhci_get_dma_delay(struct usb_device * udev,uint32_t * pus)4117 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4118 {
4119 /*
4120 * Wait until the hardware has finished any possible use of
4121 * the transfer descriptor(s)
4122 */
4123 *pus = 2048; /* microseconds */
4124 }
4125
4126 static void
xhci_device_resume(struct usb_device * udev)4127 xhci_device_resume(struct usb_device *udev)
4128 {
4129 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4130 uint8_t index;
4131 uint8_t n;
4132 uint8_t p;
4133
4134 DPRINTF("\n");
4135
4136 /* check for root HUB */
4137 if (udev->parent_hub == NULL)
4138 return;
4139
4140 index = udev->controller_slot_id;
4141
4142 XHCI_CMD_LOCK(sc);
4143
4144 /* blindly resume all endpoints */
4145
4146 USB_BUS_LOCK(udev->bus);
4147
4148 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4149 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4150 XWRITE4(sc, door, XHCI_DOORBELL(index),
4151 n | XHCI_DB_SID_SET(p));
4152 }
4153 }
4154
4155 USB_BUS_UNLOCK(udev->bus);
4156
4157 XHCI_CMD_UNLOCK(sc);
4158 }
4159
4160 static void
xhci_device_suspend(struct usb_device * udev)4161 xhci_device_suspend(struct usb_device *udev)
4162 {
4163 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4164 uint8_t index;
4165 uint8_t n;
4166 usb_error_t err;
4167
4168 DPRINTF("\n");
4169
4170 /* check for root HUB */
4171 if (udev->parent_hub == NULL)
4172 return;
4173
4174 index = udev->controller_slot_id;
4175
4176 XHCI_CMD_LOCK(sc);
4177
4178 /* blindly suspend all endpoints */
4179
4180 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4181 err = xhci_cmd_stop_ep(sc, 1, n, index);
4182 if (err != 0) {
4183 DPRINTF("Failed to suspend endpoint "
4184 "%u on slot %u (ignored).\n", n, index);
4185 }
4186 }
4187
4188 XHCI_CMD_UNLOCK(sc);
4189 }
4190
4191 static void
xhci_set_hw_power(struct usb_bus * bus)4192 xhci_set_hw_power(struct usb_bus *bus)
4193 {
4194 DPRINTF("\n");
4195 }
4196
4197 static void
xhci_device_state_change(struct usb_device * udev)4198 xhci_device_state_change(struct usb_device *udev)
4199 {
4200 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4201 struct usb_page_search buf_inp;
4202 usb_error_t err;
4203 uint8_t index;
4204
4205 /* check for root HUB */
4206 if (udev->parent_hub == NULL)
4207 return;
4208
4209 index = udev->controller_slot_id;
4210
4211 DPRINTF("\n");
4212
4213 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4214 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4215 &sc->sc_hw.devs[index].tt);
4216 if (err != 0)
4217 sc->sc_hw.devs[index].nports = 0;
4218 }
4219
4220 XHCI_CMD_LOCK(sc);
4221
4222 switch (usb_get_device_state(udev)) {
4223 case USB_STATE_POWERED:
4224 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4225 break;
4226
4227 /* set default state */
4228 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4229
4230 /* reset number of contexts */
4231 sc->sc_hw.devs[index].context_num = 0;
4232
4233 err = xhci_cmd_reset_dev(sc, index);
4234
4235 if (err != 0) {
4236 DPRINTF("Device reset failed "
4237 "for slot %u.\n", index);
4238 }
4239 break;
4240
4241 case USB_STATE_ADDRESSED:
4242 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4243 break;
4244
4245 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4246
4247 /* set configure mask to slot only */
4248 (void)xhci_configure_mask(udev, 1, 0);
4249
4250 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4251
4252 if (err) {
4253 DPRINTF("Failed to deconfigure "
4254 "slot %u.\n", index);
4255 }
4256 break;
4257
4258 case USB_STATE_CONFIGURED:
4259 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4260 break;
4261
4262 /* set configured state */
4263 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4264
4265 /* reset number of contexts */
4266 sc->sc_hw.devs[index].context_num = 0;
4267
4268 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4269
4270 (void)xhci_configure_mask(udev, 3, 0);
4271
4272 err = xhci_configure_device(udev);
4273 if (err != 0) {
4274 DPRINTF("Could not configure device "
4275 "at slot %u.\n", index);
4276 }
4277
4278 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4279 if (err != 0) {
4280 DPRINTF("Could not evaluate device "
4281 "context at slot %u.\n", index);
4282 }
4283 break;
4284
4285 default:
4286 break;
4287 }
4288 XHCI_CMD_UNLOCK(sc);
4289 }
4290
4291 static usb_error_t
xhci_set_endpoint_mode(struct usb_device * udev,struct usb_endpoint * ep,uint8_t ep_mode)4292 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4293 uint8_t ep_mode)
4294 {
4295 switch (ep_mode) {
4296 case USB_EP_MODE_DEFAULT:
4297 return (USB_ERR_NORMAL_COMPLETION);
4298 case USB_EP_MODE_STREAMS:
4299 if ((xhcistreams == 0) ||
4300 ((ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK) ||
4301 (udev->speed != USB_SPEED_SUPER))
4302 return (USB_ERR_INVAL);
4303 return (USB_ERR_NORMAL_COMPLETION);
4304 default:
4305 return (USB_ERR_INVAL);
4306 }
4307 }
4308
4309 struct usb_bus_methods xhci_bus_methods = {
4310 .endpoint_init = xhci_ep_init,
4311 .endpoint_uninit = xhci_ep_uninit,
4312 .xfer_setup = xhci_xfer_setup,
4313 .xfer_unsetup = xhci_xfer_unsetup,
4314 .get_dma_delay = xhci_get_dma_delay,
4315 .device_init = xhci_device_init,
4316 .device_uninit = xhci_device_uninit,
4317 .device_resume = xhci_device_resume,
4318 .device_suspend = xhci_device_suspend,
4319 .set_hw_power = xhci_set_hw_power,
4320 .roothub_exec = xhci_roothub_exec,
4321 .xfer_poll = xhci_do_poll,
4322 .start_dma_delay = xhci_start_dma_delay,
4323 .set_address = xhci_set_address,
4324 .clear_stall = xhci_ep_clear_stall,
4325 .device_state_change = xhci_device_state_change,
4326 .set_hw_power_sleep = xhci_set_hw_power_sleep,
4327 .set_endpoint_mode = xhci_set_endpoint_mode,
4328 };
4329