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/kernel/linux/linux-5.10/drivers/mtd/maps/
Dscx200_docflash.c27 static int probe = 0; /* Don't autoprobe */
28 static unsigned size = 0x1000000; /* 16 MiB the whole ISA address space */
32 module_param(probe, int, 0);
34 module_param(size, int, 0);
36 module_param(width, int, 0);
38 module_param(flashtype, charp, 0);
51 .offset = 0,
52 .size = 0xc0000
56 .offset = 0xc0000,
57 .size = 0x40000
[all …]
/kernel/linux/linux-5.10/arch/sh/boards/mach-microdev/
Dsetup.c21 [0] = {
22 .start = 0x300,
23 .end = 0x300 + SZ_4K - 1,
41 { S1DREG_MISC, 0x00 },
42 { S1DREG_COM_DISP_MODE, 0x00 },
43 { S1DREG_GPIO_CNF0, 0x00 },
44 { S1DREG_GPIO_CNF1, 0x00 },
45 { S1DREG_GPIO_CTL0, 0x00 },
46 { S1DREG_GPIO_CTL1, 0x00 },
47 { S1DREG_CLK_CNF, 0x02 },
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dste-db8500.dtsi9 operating-points = <998400 0
10 800000 0
11 400000 0
12 200000 0>;
23 reg = <0x06000000 0x00f00000>;
29 reg = <0x06f00000 0x00100000>;
35 reg = <0x07000000 0x01000000>;
49 reg = <0x17f00000 0x00100000>;
Dste-db8520.dtsi9 operating-points = <1152000 0
10 800000 0
11 400000 0
12 200000 0>;
23 reg = <0x06000000 0x00f00000>;
29 reg = <0x06f00000 0x00100000>;
35 reg = <0x07000000 0x01000000>;
49 reg = <0x17f00000 0x00100000>;
Dbcm953012hr.dts50 reg = <0x80000000 0x10000000>;
55 partition@0 {
57 reg = <0x00000000 0x00200000>;
62 reg = <0x00200000 0x00400000>;
66 reg = <0x00600000 0x00a00000>;
70 reg = <0x01000000 0x07000000>;
82 partition@0 {
84 reg = <0x00000000 0x000d0000>;
88 reg = <0x000d0000 0x00030000>;
92 reg = <0x00100000 0x00600000>;
[all …]
Dbcm953012k.dts48 reg = <0x80000000 0x10000000>;
53 nandcs@0 {
55 reg = <0>;
64 partition@0 {
66 reg = <0x00000000 0x00200000>;
71 reg = <0x00200000 0x00400000>;
75 reg = <0x00600000 0x00a00000>;
79 reg = <0x01000000 0x07000000>;
92 partition@0 {
94 reg = <0x00000000 0x000d0000>;
[all …]
/kernel/linux/linux-5.10/drivers/edac/
Dfsl_ddr_edac.h27 #define FSL_MC_DDR_SDRAM_CFG 0x0110
28 #define FSL_MC_CS_BNDS_0 0x0000
29 #define FSL_MC_CS_BNDS_OFS 0x0008
31 #define FSL_MC_DATA_ERR_INJECT_HI 0x0e00
32 #define FSL_MC_DATA_ERR_INJECT_LO 0x0e04
33 #define FSL_MC_ECC_ERR_INJECT 0x0e08
34 #define FSL_MC_CAPTURE_DATA_HI 0x0e20
35 #define FSL_MC_CAPTURE_DATA_LO 0x0e24
36 #define FSL_MC_CAPTURE_ECC 0x0e28
37 #define FSL_MC_ERR_DETECT 0x0e40
[all …]
Dfsl_ddr_edac.c65 return sprintf(data, "0x%08x", in fsl_mc_inject_data_hi_show()
75 return sprintf(data, "0x%08x", in fsl_mc_inject_data_lo_show()
85 return sprintf(data, "0x%08x", in fsl_mc_inject_ctrl_show()
99 rc = kstrtoul(data, 0, &val); in fsl_mc_inject_data_hi_store()
106 return 0; in fsl_mc_inject_data_hi_store()
119 rc = kstrtoul(data, 0, &val); in fsl_mc_inject_data_lo_store()
126 return 0; in fsl_mc_inject_data_lo_store()
139 rc = kstrtoul(data, 0, &val); in fsl_mc_inject_ctrl_store()
146 return 0; in fsl_mc_inject_ctrl_store()
178 /* [0:31] [32:63] */
[all …]
/kernel/linux/linux-5.10/drivers/staging/wfx/
Dhwio.h30 #define CFG_ERR_SPI_FRAME 0x00000001 // only with SPI
31 #define CFG_ERR_SDIO_BUF_MISMATCH 0x00000001 // only with SDIO
32 #define CFG_ERR_BUF_UNDERRUN 0x00000002
33 #define CFG_ERR_DATA_IN_TOO_LARGE 0x00000004
34 #define CFG_ERR_HOST_NO_OUT_QUEUE 0x00000008
35 #define CFG_ERR_BUF_OVERRUN 0x00000010
36 #define CFG_ERR_DATA_OUT_TOO_LARGE 0x00000020
37 #define CFG_ERR_HOST_NO_IN_QUEUE 0x00000040
38 #define CFG_ERR_HOST_CRC_MISS 0x00000080 // only with SDIO
39 #define CFG_SPI_IGNORE_CS 0x00000080 // only with SPI
[all …]
/kernel/linux/linux-5.10/arch/powerpc/include/asm/
Dreg_8xx.h29 #define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
30 #define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */
38 #define LCTRL1_CTE_GT 0xc0000000
39 #define LCTRL1_CTF_LT 0x14000000
40 #define LCTRL1_CRWE_RW 0x00000000
41 #define LCTRL1_CRWE_RO 0x00040000
42 #define LCTRL1_CRWE_WO 0x000c0000
43 #define LCTRL1_CRWF_RW 0x00000000
44 #define LCTRL1_CRWF_RO 0x00010000
45 #define LCTRL1_CRWF_WO 0x00030000
[all …]
Dcpm2.h20 #define CPM_CR_RST ((uint)0x80000000)
21 #define CPM_CR_PAGE ((uint)0x7c000000)
22 #define CPM_CR_SBLOCK ((uint)0x03e00000)
23 #define CPM_CR_FLG ((uint)0x00010000)
24 #define CPM_CR_MCN ((uint)0x00003fc0)
25 #define CPM_CR_OPCODE ((uint)0x0000000f)
29 #define CPM_CR_SCC1_SBLOCK (0x04)
30 #define CPM_CR_SCC2_SBLOCK (0x05)
31 #define CPM_CR_SCC3_SBLOCK (0x06)
32 #define CPM_CR_SCC4_SBLOCK (0x07)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dexynos-srom.yaml33 <bank-number> 0 <parent address of bank> <size>
37 "^.*@[0-3],[a-f0-9]+$":
50 typically 0 as this is the start of the bank.
74 Tacp: Page mode access cycle at Page mode (0 - 15)
75 Tcah: Address holding time after CSn (0 - 15)
76 Tcoh: Chip selection hold on OEn (0 - 15)
77 Tacc: Access cycle (0 - 31, the actual time is N + 1)
78 Tcos: Chip selection set-up before OEn (0 - 15)
79 Tacs: Address set-up before CSn (0 - 15)
96 reg = <0x12560000 0x14>;
[all …]
/kernel/linux/linux-5.10/include/linux/bcma/
Dbcma_regs.h7 #define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
8 #define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
9 #define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
10 #define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
11 #define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
12 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
13 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
14 #define BCMA_CLKCTLST_HQCLKREQ 0x00000040 /* HQ Clock */
15 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
17 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/etnaviv/
Dstate_hi.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001
49 #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002
50 #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003
51 #define MMU_EXCEPTION_OUT_OF_BOUND 0x00000004
52 #define MMU_EXCEPTION_READ_SECURITY_VIOLATION 0x00000005
53 #define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION 0x00000006
54 #define VIVS_HI 0x00000000
56 #define VIVS_HI_CLOCK_CONTROL 0x00000000
[all …]
/kernel/linux/linux-5.10/sound/pci/cs46xx/
Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
Dauxgm200.c36 nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00710000, 0x00000000); in gm200_i2c_aux_fini()
44 const u32 ureq = unksel ? 0x00100000 : 0x00200000; in gm200_i2c_aux_init()
45 const u32 urep = unksel ? 0x01000000 : 0x02000000; in gm200_i2c_aux_init()
51 ctrl = nvkm_rd32(device, 0x00d954 + (aux->ch * 0x50)); in gm200_i2c_aux_init()
57 } while (ctrl & 0x07010000); in gm200_i2c_aux_init()
60 nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00700000, ureq); in gm200_i2c_aux_init()
63 ctrl = nvkm_rd32(device, 0x00d954 + (aux->ch * 0x50)); in gm200_i2c_aux_init()
70 } while ((ctrl & 0x07000000) != urep); in gm200_i2c_aux_init()
72 return 0; in gm200_i2c_aux_init()
81 const u32 base = aux->ch * 0x50; in gm200_i2c_aux_xfer()
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Daiutils.h29 #define SI_CORE_SIZE 0x1000
38 #define SI_PCI_DMA_SZ 0x40000000
41 #define SI_PCIE_DMA_H32 0x80000000
44 #define SI_CC_IDX 0
52 #define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
55 #define CCS_FORCEALP 0x00000001 /* force ALP request */
56 #define CCS_FORCEHT 0x00000002 /* force HT request */
57 #define CCS_FORCEILP 0x00000004 /* force ILP request */
58 #define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
59 #define CCS_HTAREQ 0x00000010 /* HT Avail Request */
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/
Di740_reg.h37 #define XRX 0x3D6
38 #define MRX 0x3D2
41 #define DACMASK 0x3C6
42 #define DACSTATE 0x3C7
43 #define DACRX 0x3C7
44 #define DACWX 0x3C8
45 #define DACDATA 0x3C9
48 #define START_ADDR_HI 0x0C
49 #define START_ADDR_LO 0x0D
50 #define VERT_SYNC_END 0x11
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dp1023rdb.dts56 size = <0 0x1000000>;
57 alignment = <0 0x1000000>;
60 size = <0 0x400000>;
61 alignment = <0 0x400000>;
64 size = <0 0x2000000>;
65 alignment = <0 0x2000000>;
70 ranges = <0x0 0xf 0xff000000 0x200000>;
74 ranges = <0x0 0xf 0xff200000 0x200000>;
78 ranges = <0x0 0x0 0xff600000 0x200000>;
83 reg = <0x53>;
[all …]
/kernel/linux/linux-5.10/arch/m68k/include/asm/
Dm54xxpci.h21 #define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */
22 #define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */
23 #define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */
24 #define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */
25 #define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */
26 #define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */
27 #define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */
28 #define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */
29 #define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */
30 #define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */
[all …]
/kernel/linux/linux-5.10/arch/microblaze/include/asm/
Dpvr.h13 #define PVR_MSR_BIT 0x400
22 #define PVR0_PVR_FULL_MASK 0x80000000
23 #define PVR0_USE_BARREL_MASK 0x40000000
24 #define PVR0_USE_DIV_MASK 0x20000000
25 #define PVR0_USE_HW_MUL_MASK 0x10000000
26 #define PVR0_USE_FPU_MASK 0x08000000
27 #define PVR0_USE_EXC_MASK 0x04000000
28 #define PVR0_USE_ICACHE_MASK 0x02000000
29 #define PVR0_USE_DCACHE_MASK 0x01000000
30 #define PVR0_USE_MMU 0x00800000
[all …]
/kernel/linux/linux-5.10/drivers/mtd/devices/
Dms02-nv.c26 "ms02-nv.c: v.1.0.0 13 Aug 2001 Maciej W. Rozycki.\n";
35 * at any 8MiB boundary within a 0MiB up to 112MiB range or at any 32MiB
36 * boundary within a 0MiB up to 448MiB range. We don't support a module
37 * at 0MiB, though.
40 0x07000000, 0x06800000, 0x06000000, 0x05800000, 0x05000000,
41 0x04800000, 0x04000000, 0x03800000, 0x03000000, 0x02800000,
42 0x02000000, 0x01800000, 0x01000000, 0x00800000
60 return 0; in ms02nv_read()
70 return 0; in ms02nv_write()
92 return 0; in ms02nv_probe_one()
[all …]
/kernel/linux/linux-5.10/drivers/crypto/chelsio/
Dchcr_crypto.h63 #define CHCR_ENCRYPT_OP 0
72 #define CHCR_SCMD_AUTH_CTRL_AUTH_CIPHER 0
75 #define CHCR_SCMD_CIPHER_MODE_NOP 0
83 #define CHCR_SCMD_AUTH_MODE_NOP 0
95 #define CHCR_SCMD_HMAC_CTRL_NOP 0
103 #define VERIFY_HW 0
106 #define CHCR_SCMD_IVGEN_CTRL_HW 0
111 #define CHCR_KEYCTX_MAC_KEY_SIZE_128 0
116 #define CHCR_KEYCTX_CIPHER_KEY_SIZE_128 0
128 #define IV_NOP 0
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/
Dar9003_mci.h20 #define MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */
25 #define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0
29 #define MCI_GPM_COEX_MINOR_VERSION_WLAN 0
32 MCI_GPM_COEX_QUERY_BT_ALL_INFO = BIT(0),
50 #define MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002
51 #define MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004
52 #define MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008
53 #define MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010
54 #define MCI_BT_MCI_FLAGS_DEBUG 0x00000020
55 #define MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040
[all …]
/kernel/linux/linux-5.10/sound/pci/oxygen/
Doxygen_regs.h6 #define OXYGEN_DMA_A_ADDRESS 0x00 /* 32-bit base address */
7 #define OXYGEN_DMA_A_COUNT 0x04 /* buffer counter (dwords) */
8 #define OXYGEN_DMA_A_TCOUNT 0x06 /* interrupt counter (dwords) */
11 #define OXYGEN_DMA_B_ADDRESS 0x08
12 #define OXYGEN_DMA_B_COUNT 0x0c
13 #define OXYGEN_DMA_B_TCOUNT 0x0e
16 #define OXYGEN_DMA_C_ADDRESS 0x10
17 #define OXYGEN_DMA_C_COUNT 0x14
18 #define OXYGEN_DMA_C_TCOUNT 0x16
21 #define OXYGEN_DMA_SPDIF_ADDRESS 0x18
[all …]

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