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/kernel/linux/linux-5.10/arch/c6x/boot/dts/
Dtms320c6472.dtsi14 model = "ti,c64x+";
19 model = "ti,c64x+";
24 model = "ti,c64x+";
29 model = "ti,c64x+";
34 model = "ti,c64x+";
39 model = "ti,c64x+";
51 compatible = "ti,c64x+core-pic";
57 compatible = "ti,c64x+megamod-pic";
65 compatible = "ti,c64x+cache";
70 compatible = "ti,c64x+timer64";
[all …]
Dtms320c6474.dtsi14 model = "ti,c64x+";
19 model = "ti,c64x+";
24 model = "ti,c64x+";
38 compatible = "ti,c64x+core-pic";
42 compatible = "ti,c64x+megamod-pic";
50 compatible = "ti,c64x+cache";
55 compatible = "ti,c64x+timer64";
61 compatible = "ti,c64x+timer64";
67 compatible = "ti,c64x+timer64";
73 compatible = "ti,c64x+dscr";
[all …]
Dtms320c6678.dtsi61 compatible = "ti,c64x+core-pic";
67 compatible = "ti,c64x+megamod-pic";
75 compatible = "ti,c64x+cache";
80 compatible = "ti,c64x+timer64";
86 compatible = "ti,c64x+timer64";
92 compatible = "ti,c64x+timer64";
98 compatible = "ti,c64x+timer64";
104 compatible = "ti,c64x+timer64";
110 compatible = "ti,c64x+timer64";
116 compatible = "ti,c64x+timer64";
[all …]
Dtms320c6457.dtsi13 model = "ti,c64x+";
28 compatible = "ti,c64x+core-pic";
32 compatible = "ti,c64x+megamod-pic";
40 compatible = "ti,c64x+cache";
45 compatible = "ti,c64x+dscr";
57 compatible = "ti,c64x+timer64";
62 compatible = "ti,c6457-pll", "ti,c64x+pll";
64 ti,c64x+pll-bypass-delay = <300>;
65 ti,c64x+pll-reset-delay = <24000>;
66 ti,c64x+pll-lock-delay = <50000>;
Dtms320c6455.dtsi13 model = "ti,c64x+";
28 compatible = "ti,c64x+core-pic";
35 compatible = "ti,c64x+megamod-pic";
43 compatible = "ti,c64x+cache";
48 compatible = "ti,c64x+emifa", "simple-bus";
66 compatible = "ti,c64x+timer64";
72 compatible = "ti,c6455-pll", "ti,c64x+pll";
74 ti,c64x+pll-bypass-delay = <1440>;
75 ti,c64x+pll-reset-delay = <15360>;
76 ti,c64x+pll-lock-delay = <24000>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/c6x/
Dclocks.txt10 - compatible: "ti,c64x+pll"
24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
33 compatible = "ti,c6472-pll", "ti,c64x+pll";
37 ti,c64x+pll-bypass-delay = <200>;
38 ti,c64x+pll-reset-delay = <12000>;
39 ti,c64x+pll-lock-delay = <80000>;
Demifa.txt9 - compatible: must be "ti,c64x+emifa", "simple-bus"
32 compatible = "ti,c64x+emifa", "simple-bus";
Ddscr.txt24 - compatible: must be "ti,c64x+dscr"
104 compatible = "ti,c64x+dscr";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dti,c64x+megamod-pic.txt4 * C64X+ Core Interrupt Controller
7 C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
13 - compatible: Should be "ti,c64x+core-pic";
26 compatible = "ti,c64x+core-pic";
31 * C64x+ Megamodule Interrupt Controller
45 - compatible: "ti,c64x+megamod-pic"
55 - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
68 interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
75 compatible = "ti,c64x+megamod-pic";
89 compatible = "ti,c64x+megamod-pic";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Dti,c64x+timer64.txt8 - compatible: must be "ti,c64x+timer64"
20 compatible = "ti,c64x+timer64";
/kernel/linux/linux-5.10/arch/c6x/include/asm/
Dirq.h22 * The C64X+ core has 16 IRQ vectors. One each is used by Reset and NMI. Two
27 * The C64x+ megamodule provides a PIC which combines SoC IRQ sources into a
Dunaligned.h16 * The C64x+ can do unaligned word and dword accesses in hardware
Dclock.h3 * TI C64X clock definitions
/kernel/linux/linux-5.10/arch/c6x/platforms/
Dmegamod-pic.c3 * Support for C64x+ Megamodule Interrupt Controller
183 map = of_get_property(np, "ti,c64x+megamod-pic-mux", &maplen); in parse_priority_map()
204 pr_info("Initializing C64x+ Megamodule PIC\n"); in init_megamod_pic()
333 np = of_find_compatible_node(NULL, NULL, "ti,c64x+megamod-pic"); in megamod_pic_init()
Dplldata.c414 { .compatible = "ti,c64x+pll" },
443 err = of_property_read_u32(node, "ti,c64x+pll-bypass-delay", &val); in c64x_setup_clocks()
448 err = of_property_read_u32(node, "ti,c64x+pll-reset-delay", &val); in c64x_setup_clocks()
453 err = of_property_read_u32(node, "ti,c64x+pll-lock-delay", &val); in c64x_setup_clocks()
Dtimer64.c175 for_each_compatible_node(np, NULL, "ti,c64x+timer64") { in timer64_init()
190 pr_debug("Cannot find ti,c64x+timer64 timer.\n"); in timer64_init()
Demif.c33 { .compatible = "ti,c64x+emifa" },
Dcache.c428 node = of_find_compatible_node(NULL, NULL, "ti,c64x+cache"); in c6x_cache_init()
Dpll.c3 * Clock and PLL control for C64x+ devices
/kernel/linux/linux-5.10/arch/c6x/kernel/
Dsetup.c130 p->cpu_name = "C64x"; in get_cpuinfo()
133 p->cpu_name = "C64x"; in get_cpuinfo()
136 p->cpu_name = "C64x+"; in get_cpuinfo()
176 p->cpu_rev = "C64x"; in get_cpuinfo()
Dirq.c98 np = of_find_compatible_node(NULL, NULL, "ti,c64x+core-pic"); in init_IRQ()
/kernel/linux/linux-5.10/Documentation/locking/
Dhwspinlock.rst12 For example, OMAP4 has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP,
24 remote M3 and/or C64x+ slave processors (by an IPC subsystem called Syslink).
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/remoteproc/
Dti,omap-remoteproc.yaml22 sub-system. The DSP processor sub-system can contain any of the TI's C64x,
/kernel/linux/linux-5.10/Documentation/staging/
Dremoteproc.rst12 OMAP4, for example, has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP.
Drpmsg.rst19 OMAP4, for example, has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP.

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