Searched +full:bt1 +full:- +full:ccu +full:- +full:axi (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Baikal-T1 Clock Control Unit Dividers11 - Serge Semin <fancer.lancer@gmail.com>14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller15 responsible for the chip subsystems clocking and resetting. The CCU is18 IP-blocks or to groups of blocks (clock domains). The transformation is done19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Baikal-T1 Clock Control Unit PLL11 - Serge Semin <fancer.lancer@gmail.com>14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller15 responsible for the chip subsystems clocking and resetting. The CCU is18 IP-blocks or to groups of blocks (clock domains). The transformation is done19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.[all …]
1 // SPDX-License-Identifier: GPL-2.0-only9 * Baikal-T1 CCU Dividers clock driver12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt17 #include <linux/clk-provider.h>18 #include <linux/reset-controller.h>26 #include <dt-bindings/clock/bt1-ccu.h>27 #include <dt-bindings/reset/bt1-ccu.h>29 #include "ccu-div.h"128 * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks131 * the later is clocking the AXI-bus between DDR controller and the Main[all …]
1 // SPDX-License-Identifier: GPL-2.0-only9 * Baikal-T1 CCU PLL clocks driver12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt17 #include <linux/clk-provider.h>24 #include <dt-bindings/clock/bt1-ccu.h>26 #include "ccu-pll.h"56 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and57 * DDR controller AXI-bus clocks. If they are gated the system will be59 * of the corresponding subsystems. So until we aren't ready to re-initialize88 pll = data->plls[idx]; in ccu_pll_find_desc()[all …]