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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dmarvell,mmp2-audio-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/marvell,mmp2-audio-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MMP2 Audio Clock Controller
10 - Lubomir Rintel <lkundrak@v3.sk>
13 The audio clock controller generates and supplies the clocks to the audio
16 Each clock is assigned an identifier and client nodes use this identifier
17 to specify the clock which they consume.
20 <dt-bindings/clock/marvell,mmp2-audio.h>.
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Dmarvell,mmp2-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/marvell,mmp2-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MMP2 and MMP3 Clock Controller
10 - Lubomir Rintel <lkundrak@v3.sk>
13 The clock subsystem on MMP2 or MMP3 generates and supplies clock to various
16 Each clock is assigned an identifier and client nodes use this identifier
17 to specify the clock which they consume.
19 All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>.
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmmp2.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <1>;
26 compatible = "simple-bus";
27 interrupt-parent = <&intc>;
30 L2: l2-cache {
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Dmmp3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/marvell,mmp2.h>
7 #include <dt-bindings/power/marvell,mmp2.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 enable-method = "marvell,mmp3-smp";
22 next-level-cache = <&l2>;
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Dmmp2-olpc-xo-1-75.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
8 /dts-v1/;
9 #include "mmp2.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/linux-event-codes.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
15 model = "OLPC XO-1.75";
16 compatible = "olpc,xo-1.75", "mrvl,mmp2";
19 #address-cells = <1>;
20 #size-cells = <1>;
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/
Dmarvell,mmp2-ccic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/marvell,mmp2-ccic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Marvell MMP2 camera host interface bindings
11 - Lubomir Rintel <lkundrak@v3.sk>
15 pattern: '^camera@[a-f0-9]+$'
18 const: marvell,mmp2-ccic
36 # Documentation/devicetree/bindings/media/video-interfaces.txt
38 remote-endpoint: true
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dmarvell,mmp2-ssp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/spi/marvell,mmp2-ssp.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Lubomir Rintel <lkundrak@v3.sk>
14 - $ref: spi-controller.yaml#
18 const: marvell,mmp2-ssp
29 ready-gpios:
36 - compatible
37 - reg
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/kernel/linux/linux-5.10/arch/arm/mach-mmp/
Dmmp2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-mmp/mmp2.c
5 * code name MMP2
18 #include <asm/hardware/cache-tauros2.h>
21 #include "addr-map.h"
22 #include "regs-apbc.h"
27 #include "mmp2.h"
28 #include "pm-mmp2.h"
128 * enable bus/functional clock, enable 6.5MHz (divider 4), in mmp2_timer_init()
137 /* on-chip devices */
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Dpm-mmp2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MMP2 Power Management Routines
18 #include <asm/mach-types.h>
21 #include "addr-map.h"
22 #include "pm-mmp2.h"
23 #include "regs-icu.h"
29 int irq = d->irq; in mmp2_set_wake()
63 /* close AXI fabric clock gate */ in pm_scu_clk_disable()
67 /* close MCB master clock gate */ in pm_scu_clk_disable()
79 /* open AXI fabric clock gate */ in pm_scu_clk_enable()
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/kernel/linux/linux-5.10/drivers/clk/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
20 Select this option when the clock API in <linux/clk.h> is implemented
26 bool "Common Clock Framework"
33 The common clock framework is a single definition of struct
35 implementation of the clock API in include/linux/clk.h.
42 tristate "Clock driver for WM831x/2x PMICs"
59 tristate "Clock driver for Maxim 77620/77686/77802 MFD"
63 clock.
66 tristate "Maxim 9485 Programmable Clock Generator"
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/
Dmrvl-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpio/mrvl-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
12 - Rob Herring <robh+dt@kernel.org>
15 - if:
20 - intel,pxa25x-gpio
21 - intel,pxa26x-gpio
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/kernel/linux/linux-5.10/drivers/clk/mmp/
Dclk-audio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MMP Audio Clock Controller driver
8 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/marvell,mmp2-audio.h>
123 aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0); in audio_pll_recalc_rate()
131 aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1); in audio_pll_recalc_rate()
214 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL0); in audio_pll_set_rate()
218 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL1); in audio_pll_set_rate()
224 return -ERANGE; in audio_pll_set_rate()
236 { .hw = &priv->audio_pll_hw }, in register_clocks()
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Dclk-mmp2.c2 * mmp2 clock framework source file
195 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); in mmp2_clk_init()
199 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); in mmp2_clk_init()
203 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2"); in mmp2_clk_init()
207 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3"); in mmp2_clk_init()
211 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4"); in mmp2_clk_init()
215 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5"); in mmp2_clk_init()
219 clk_register_clkdev(clk, NULL, "mmp2-gpio"); in mmp2_clk_init()
223 clk_register_clkdev(clk, NULL, "pxa27x-keypad"); in mmp2_clk_init()
227 clk_register_clkdev(clk, NULL, "mmp-rtc"); in mmp2_clk_init()
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Dclk-of-mmp2.c2 * mmp2 clock framework source file
22 #include <dt-bindings/clock/marvell,mmp2.h>
23 #include <dt-bindings/power/marvell,mmp2.h>
183 struct mmp_clk_unit *unit = &pxa_unit->unit; in mmp2_main_clk_init()
188 if (pxa_unit->model == CLK_MODEL_MMP3) { in mmp2_main_clk_init()
190 pxa_unit->mpmu_base, in mmp2_main_clk_init()
194 pxa_unit->mpmu_base, in mmp2_main_clk_init()
203 pxa_unit->mpmu_base + MPMU_UART_PLL, in mmp2_main_clk_init()
210 pxa_unit->mpmu_base + MPMU_I2S0_PLL, in mmp2_main_clk_init()
215 pxa_unit->mpmu_base + MPMU_I2S1_PLL, in mmp2_main_clk_init()
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Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MMP PLL clock rate calculation
8 #include <linux/clk-provider.h>
34 val = readl_relaxed(pll->enable_reg); in mmp_clk_pll_is_enabled()
35 if ((val & pll->enable) == pll->enable) in mmp_clk_pll_is_enabled()
38 /* Some PLLs, if not software controlled, output default clock. */ in mmp_clk_pll_is_enabled()
39 if (pll->default_rate > 0) in mmp_clk_pll_is_enabled()
53 val = readl_relaxed(pll->enable_reg); in mmp_clk_pll_recalc_rate()
54 if ((val & pll->enable) != pll->enable) in mmp_clk_pll_recalc_rate()
55 return pll->default_rate; in mmp_clk_pll_recalc_rate()
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Dclk-of-pxa1928.c2 * pxa1928 clock framework source file
7 * Based on drivers/clk/mmp/clk-of-mmp2.c:
21 #include <dt-bindings/clock/marvell,pxa1928.h>
71 struct mmp_clk_unit *unit = &pxa_unit->unit; in pxa1928_pll_init()
81 pxa_unit->mpmu_base + MPMU_UART_PLL, in pxa1928_pll_init()
132 struct mmp_clk_unit *unit = &pxa_unit->unit; in pxa1928_apb_periph_clk_init()
134 mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base, in pxa1928_apb_periph_clk_init()
137 mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base, in pxa1928_apb_periph_clk_init()
171 struct mmp_clk_unit *unit = &pxa_unit->unit; in pxa1928_axi_periph_clk_init()
173 mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base, in pxa1928_axi_periph_clk_init()
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dmarvell,pxau2o-ehci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/marvell,pxau2o-ehci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Lubomir Rintel <lkundrak@v3.sk>
14 - $ref: usb-hcd.yaml#
18 const: marvell,pxau2o-ehci
29 clock-names:
35 phy-names:
39 - compatible
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dmarvell,mmp-sspa.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/marvell,mmp-sspa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lubomir Rintel <lkundrak@v3.sk>
14 pattern: "^audio-controller(@.*)?$"
17 const: marvell,mmp-sspa
21 - description: RX block
22 - description: TX block
29 - description: Clock for the Audio block
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/
Di2c-pxa.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh+dt@kernel.org>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
17 - mrvl,i2c-polling
20 - interrupts
25 - mrvl,mmp-twsi
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/kernel/linux/linux-5.10/include/linux/platform_data/
Dpxa_sdhci.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * PXA Platform - SDHCI platform data definitions
15 /* Require clock free running */
17 /* card always wired to host, like on-chip emmc */
19 /* Board design supports 8-bit data on SD/SDIO BUS */
23 * struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI
26 * mmp2: each step is roughly 100ps, 5bits width
/kernel/linux/linux-5.10/drivers/media/platform/marvell-ccic/
Dmmp-driver.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <media/v4l2-device.h>
18 #include <linux/platform_data/media/mmp-camera.h>
29 #include "mcam-core.h"
31 MODULE_ALIAS("platform:mmp-camera");
53 * dphy[0] - CSI2_DPHY3
54 * dphy[1] - CSI2_DPHY5
55 * dphy[2] - CSI2_DPHY6
62 struct mmp_camera_platform_data *pdata = cam->pdev->dev.platform_data; in mmpcam_calc_dphy()
63 struct device *dev = &cam->pdev->dev; in mmpcam_calc_dphy()
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/kernel/linux/linux-5.10/drivers/video/fbdev/mmp/hw/
Dmmp_ctrl.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 /* ------------< LCD register >------------ */
18 /* TV patch register for MMP2 */
150 #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
151 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
321 #define LCD_PN_SEPXLCNT 0x013c /* MMP2 */
339 #define LCD_READ_IOPAD (0x0148) /* MMP2*/
361 #define LCD_SLV_DBG (0x0164) /* MMP2 */
371 #define LCD_TV_PALETTE_RDDAT (0x0178) /* MMP2 */
380 #define LCD_FRAME_CNT (0x017C) /* MMP2 */
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/kernel/linux/linux-5.10/drivers/gpio/
Dgpio-pxa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/plat-pxa/gpio.c
15 #include <linux/gpio-pxa.h>
34 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
35 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
36 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
38 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
39 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
40 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
42 * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248
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/kernel/linux/linux-5.10/drivers/spi/
Dspi-pxa2xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
31 #include "spi-pxa2xx.h"
36 MODULE_ALIAS("platform:pxa2xx-spi");
78 /* LPSS offset from drv_data->ioaddr */
80 /* Register offsets from drv_data->lpss_base or -1 */
104 .reg_capabilities = -1,
114 .reg_capabilities = -1,
124 .reg_capabilities = -1,
134 .reg_general = -1,
137 .reg_capabilities = -1,
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/kernel/linux/config/linux-5.10/arch/arm/configs/
Dqemu-arm-linux_standard_defconfig5 CONFIG_CC_VERSION_TEXT="OHOS (release) clang version 10.0.1.73276 (llvm-project 434bcd0f84635e92ea…
382 # Cortex-A platforms
397 # Cortex-A/Cortex-M asymmetric multiprocessing platforms
422 # Marvell PXA168/910/MMP2 Implementations
429 # end of Marvell PXA168/910/MMP2 Implementations
892 # General architecture-dependent options
955 # GCOV-based kernel profiling
959 # end of GCOV-based kernel profiling
962 # end of General architecture-dependent options
1590 # Self-contained MTD device drivers
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