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/third_party/lz4/contrib/snap/
Dsnapcraft.yaml6 speed > 500 MB/s per core, scalable with multi-cores CPU. It features an
8 reaching RAM speed limits on multi-core systems.
20 LZ4 library is provided as open-source software using BSD 2-Clause license.
/third_party/grpc/src/python/grpcio_tests/tests/qps/
Dworker_server.py7 # http://www.apache.org/licenses/LICENSE-2.0
43 config = next(request_iterator).setup #pylint: disable=stop-iteration-return
45 cores = multiprocessing.cpu_count()
48 yield self._get_server_status(start_time, start_time, port, cores)
52 status = self._get_server_status(start_time, end_time, port, cores)
58 def _get_server_status(self, start_time, end_time, port, cores): argument
60 elapsed_time = end_time - start_time
64 return control_pb2.ServerStatus(stats=stats, port=port, cores=cores)
111 config = next(request_iterator).setup #pylint: disable=stop-iteration-return
143 elapsed_time = end_time - start_time
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/third_party/ltp/testcases/kernel/power_management/lib/
Dpm_sched_mc.py32 os.system('dmesg -c >/dev/null')
69 '''Return 1 if the system is multi socket else return 0
77 print("Failed to check if system is multi socket system")
88 if line.startswith('cpu cores'):
97 print("Failed to check if system is hyper-threaded")
101 ''' Return true if system has sockets has multiple cores
109 if line.startswith('cpu cores'):
127 print("Failed to check if system is multi core system")
140 if line.startswith('cpu cores'):
145 print("Failed to check if system is hyper-threaded")
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/third_party/libuv/docs/src/guide/
Dprocesses.rst10 (similar to using pipes in shells). A multi-process model with messages
14 A common refrain against event-based programs is that they cannot take
15 advantage of multiple cores in modern computers. In a multi-threaded program
17 cores, improving performance. But an event loop has only one thread. The
23 ------------------------
32 :lines: 6-8,15-
33 :emphasize-lines: 11,13-17
60 :lines: 9-12
61 :emphasize-lines: 3
66 ---------------------------
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DThreading.h1 //===-- llvm/Support/Threading.h - Control multithreading mode --*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file declares helper functions for running LLVM in a multi-threaded
12 //===----------------------------------------------------------------------===//
19 #include "llvm/Config/llvm-config.h" // for LLVM_ON_UNIX
52 /// Returns true if LLVM is compiled with support for multi-threading, and
63 /// \param UserFn - The callback to execute.
64 /// \param UserData - An argument to pass to the callback function.
65 /// \param StackSizeInBytes - A requested size (in bytes) for the thread stack
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/third_party/skia/third_party/externals/abseil-cpp/absl/random/internal/
Dnanobenchmark_test.cc7 // https://www.apache.org/licenses/LICENSE-2.0
53 // Avoid migrating between cores - important on multi-socket systems. in RunAll()
54 int cpu = -1; in RunAll()
/third_party/abseil-cpp/absl/random/internal/
Dnanobenchmark_test.cc7 // https://www.apache.org/licenses/LICENSE-2.0
53 // Avoid migrating between cores - important on multi-socket systems. in RunAll()
54 int cpu = -1; in RunAll()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/include/llvm/Support/
DThreading.h1 //===-- llvm/Support/Threading.h - Control multithreading mode --*- C++ -*-===//
8 //===----------------------------------------------------------------------===//
10 // This file declares helper functions for running LLVM in a multi-threaded
13 //===----------------------------------------------------------------------===//
18 #include "llvm/Config/llvm-config.h" // for LLVM_ON_UNIX
40 /// Returns true if LLVM is compiled with support for multi-threading, and
44 /// llvm_execute_on_thread - Execute the given \p UserFn on a separate
52 /// \param UserFn - The callback to execute.
53 /// \param UserData - An argument to pass to the callback function.
54 /// \param RequestedStackSize - If non-zero, a requested size (in bytes) for
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/third_party/boost/libs/fiber/doc/
Dtuning.qbk23 the heap. The default user-level memory allocator (UMA) of glibc is ptmalloc2
24 but it can be replaced by another UMA that fit better for the concret work-load
26 [@http://goog-perftools.sourceforge.net/doc/tcmalloc.html TCmalloc] enables a
35 Depending on the work-load several strategies of scheduling the fibers are
36 possible [footnote 1024cores.net:
37 [@http://www.1024cores.net/home/scalable-architecture/task-scheduling-strategies Task Scheduling St…
40 * work-stealing: ready fibers are hold in a local queue, when the
41 fiber-scheduler's local queue runs out of ready fibers, it randomly
42 selects another fiber-scheduler and tries to steal a ready fiber from the
45 * work-requesting: ready fibers are hold in a local queue, when the
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Dasio.qbk34 The example section contains a complete publish-subscribe application
79 The C10K-website [footnote [@http://www.kegel.com/c10k.html 'The C10K problem',
88 overhead of the kernel scheduler starts to swamp the available cores.)
95 Therefore developers are able to use patterns familiar from multi-threaded
/third_party/flutter/skia/third_party/externals/sdl/include/
DSDL_cpuinfo.h3 Copyright (C) 1997-2016 Sam Lantinga <slouken@libsdl.org>
5 This software is provided 'as-is', without any express or implied
74 * The 64-bit PowerPC processors have a 128 byte cache line.
80 * This function returns the number of CPU cores available.
87 * This is useful for determining multi-threaded structure padding
DSDL_atomic.h3 Copyright (C) 1997-2016 Sam Lantinga <slouken@libsdl.org>
5 This software is provided 'as-is', without any express or implied
44 * http://msdn.microsoft.com/en-us/library/ee418650%28v=vs.85%29.aspx
47 * http://www.1024cores.net/home/lock-free-algorithms
92 * \brief Try to lock a spin lock by setting it to a non-zero value.
101 * \brief Lock a spin lock by setting it to a non-zero value.
135 * reordered by the compiler and being seen out of order on multi-core CPUs.
150 * http://preshing.com/20120913/acquire-and-release-semantics
235 #define SDL_AtomicDecRef(a) (SDL_AtomicAdd(a, -1) == 1)
/third_party/lz4/
DREADME.md1 LZ4 - Extremely fast compression
6 scalable with multi-cores CPU.
9 typically reaching RAM speed limits on multi-core systems.
17 …with [dictionary compression](https://github.com/facebook/zstd#the-case-for-small-data-compression…
18 …81) and [CLI](https://github.com/lz4/lz4/blob/v1.8.3/programs/lz4.1.md#operation-modifiers) levels.
20 …onary Builder](https://github.com/facebook/zstd/blob/v1.3.5/programs/zstd.1.md#dictionary-builder),
24 LZ4 library is provided as open-source software using BSD 2-Clause license.
28 |------------|---------|
31 [travisDevBadge]: https://travis-ci.org/lz4/lz4.svg?branch=dev "Continuous Integration test suite"
32 [travisLink]: https://travis-ci.org/lz4/lz4
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/third_party/mesa3d/src/gallium/drivers/swr/rasterizer/core/
Dthreads.cpp2 * Copyright (C) 2014-2018 Intel Corporation. All Rights Reserved.
65 std::vector<Core> cores; member
94 uint32_t count = bufSize / pBufferMem->Size; in CalculateProcessorTopology()
99 SWR_ASSERT(pBuffer->Relationship == RelationProcessorCore); in CalculateProcessorTopology()
100 for (uint32_t g = 0; g < pBuffer->Processor.GroupCount; ++g) in CalculateProcessorTopology()
102 auto& gmask = pBuffer->Processor.GroupMask[g]; in CalculateProcessorTopology()
121 // Already seen this mask. This means that we are in 32-bit mode and in CalculateProcessorTopology()
125 SWR_INVALID("Shouldn't get here in 64-bit mode"); in CalculateProcessorTopology()
151 numaNode.cores.push_back(Core()); in CalculateProcessorTopology()
152 pCore = &numaNode.cores.back(); in CalculateProcessorTopology()
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/third_party/boost/boost/interprocess/detail/
Dos_thread_functions.hpp3 // (C) Copyright Ion Gaztanaga 2005-2013. Distributed under the Boost
15 // Copyright (c) 2002 Peter Dimov and Multi Media Ltd.
123 return (curres - 1ul)*100ul; in get_system_tick_ns()
132 return (curres - 1ul)/10ul + 1ul; in get_system_tick_us()
145 return (curres-1ul)/10000ul + 1ul; in get_system_tick_in_highres_counts()
149 __int64 count_fs = (1000000000000000LL - 1LL)/freq + 1LL; in get_system_tick_in_highres_counts()
150 __int64 tick_counts = (static_cast<__int64>(curres)*100000000LL - 1LL)/count_fs + 1LL; in get_system_tick_in_highres_counts()
178 { return l - r; } in system_highres_count_subtract()
343 return (get_system_tick_ns()-1)/1000ul + 1ul;
377 res.tv_nsec = 1000000000 + l.tv_nsec - r.tv_nsec;
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/third_party/openh264/codec/encoder/core/inc/
Dwels_const.h69 #define MAX_THREADS_NUM 4 // assume to support up to 4 logical cores(threads)
71 #define INTPEL_NEEDED_MARGIN (3) // for safe sub-pel MC
113 #define MAX_GOP_SIZE (1<<(MAX_TEMPORAL_LEVEL-1))
120 #define MAX_MULTI_REF_PIC_COUNT 1 //maximum multi-reference number
133 #define INVALID_ID (-1)
/third_party/cmsis/CMSIS/DSP/Include/dsp/
Dsvm_functions_f16.h6 * Target Processor: Cortex-M and Cortex-A cores
9 * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
11 * SPDX-License-Identifier: Apache-2.0
17 * www.apache.org/licenses/LICENSE-2.0
49 * The training must be done from scikit-learn. The parameters can be easily
50 * generated from the scikit-learn object. Some examples are given in
54 * will have to be used, as building blocks, to do multi-class classification.
56 * No multi-class classification is provided in this SVM folder.
70 nb --; in arm_exponent_f16()
74 nb--; in arm_exponent_f16()
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Dsvm_functions.h6 * Target Processor: Cortex-M and Cortex-A cores
9 * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
11 * SPDX-License-Identifier: Apache-2.0
17 * www.apache.org/licenses/LICENSE-2.0
47 * The training must be done from scikit-learn. The parameters can be easily
48 * generated from the scikit-learn object. Some examples are given in
52 * will have to be used, as building blocks, to do multi-class classification.
54 * No multi-class classification is provided in this SVM folder.
68 nb --; in arm_exponent_f32()
72 nb--; in arm_exponent_f32()
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/third_party/grpc/test/cpp/microbenchmarks/
Dbm_cq_multiple_threads.cc9 * http://www.apache.org/licenses/LICENSE-2.0
53 gpr_mu_init(&ps->mu); in pollset_init()
54 *mu = &ps->mu; in pollset_init()
57 static void pollset_destroy(grpc_pollset* ps) { gpr_mu_destroy(&ps->mu); } in pollset_destroy()
75 gpr_log(GPR_DEBUG, "no-op"); in pollset_work()
79 gpr_mu_unlock(&ps->mu); in pollset_work()
86 grpc_core::ExecCtx::Get()->Flush(); in pollset_work()
87 gpr_mu_lock(&ps->mu); in pollset_work()
111 // Override the polling engine for the non-polling engine in setup()
139 /* A few notes about Multi-threaded benchmarks:
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/third_party/cmsis/
DREADME.md3 ….0. The [documentation](http://arm-software.github.io/CMSIS_5/General/html/index.html) is availab…
5 Use [Issues](https://github.com/ARM-software/CMSIS_5#issues-and-labels) to provide feedback and rep…
9 …-built documentation](http://www.keil.com/pack/doc/CMSIS_Dev/index.html) is updated from time to t…
15 | CMSIS-... | Target Processors | Description |
16 |:----------|:--------------------|:-------------|
17 …-software.github.io/CMSIS_5/Core/html/index.html) | All Cortex-M, SecurCore | Standardized API fo…
18 …ore(A)](http://arm-software.github.io/CMSIS_5/Core_A/html/index.html)| Cortex-A5/A7/A9 | API and b…
19 |[Driver](http://arm-software.github.io/CMSIS_5/Driver/html/index.html) | All Cortex-M, SecurCore |…
20 …-software.github.io/CMSIS_5/DSP/html/index.html) | All Cortex-M | DSP library collection wit…
21 …-software.github.io/CMSIS_5/NN/html/index.html) | All Cortex-M | Collection of efficient ne…
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/third_party/ffmpeg/libavcodec/
Dframe_thread_encoder.c18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
69 ThreadContext *c = avctx->internal->frame_thread_encoder; in worker()
71 while (!atomic_load(&c->exit)) { in worker()
78 pthread_mutex_lock(&c->task_fifo_mutex); in worker()
79 while (c->next_task_index == c->task_index || atomic_load(&c->exit)) { in worker()
80 if (atomic_load(&c->exit)) { in worker()
81 pthread_mutex_unlock(&c->task_fifo_mutex); in worker()
84 pthread_cond_wait(&c->task_fifo_cond, &c->task_fifo_mutex); in worker()
86 task_index = c->next_task_index; in worker()
87 c->next_task_index = (c->next_task_index + 1) % c->max_tasks; in worker()
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/third_party/grpc/doc/core/
Dgrpc-polling-engines.md3 _Author: Sree Kuchibhotla (@sreecha) - Sep 2018_
10 - gRPC code deals with a bunch of file descriptors on which events like descriptor being readable/w…
11 - gRPC code knows the actions to perform when such events happen
12 - For example:
13 …- `grpc_endpoint` code calls `recvmsg` call when the fd is readable and `sendmsg` call when the fd…
14 …- ` tcp_client` connect code issues async `connect` and finishes creating the client once the fd i…
15 - gRPC needed some component that can "efficiently" do the above operations __using the threads pro…
21 - Linux:
23 - **`epollex`** (default but requires kernel version >= 4.5),
24 - `epoll1` (If `epollex` is not available and glibc version >= 2.9)
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/third_party/boost/libs/fiber/doc/html/fiber/
Dtuning.html3 <meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
22 <div class="spirit-nav">
48 fiber stacks are allocated on the heap. The default user-level memory allocator
50 …better for the concret work-load For instance Google’s <a href="http://goog-perftools.sourceforge.…
61 cooperatively, rather than preemptively. Depending on the work-load several
64 <div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; ">
66 work-stealing: ready fibers are hold in a local queue, when the fiber-scheduler's
67 local queue runs out of ready fibers, it randomly selects another fiber-scheduler
72 work-requesting: ready fibers are hold in a local queue, when the fiber-scheduler's
73 local queue runs out of ready fibers, it randomly selects another fiber-scheduler
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/third_party/elfio/elfio/
Delf_types.hpp2 Copyright (C) 2001-present by Serge Lamikhov-Center
93 #define EM_MIPS 8 // MIPS R3000 (officially, big-endian only)
95 #define EM_MIPS_RS3_LE 10 // MIPS R3000 little-endian (Deprecated)
106 #define EM_PPC64 21 // 64-bit PowerPC
129 #define EM_SPARCV9 43 // SPARC v9 64-bit
131 #define EM_ARC 45 // ARC Cores
136 #define EM_IA_64 50 // Intel IA-64 Processor
137 #define EM_MIPS_X 51 // Stanford MIPS-X
148 #define EM_X86_64 62 // Advanced Micro Devices X86-64 processor
150 #define EM_PDP10 64 // Digital Equipment Corp. PDP-10
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/third_party/openssl/crypto/sha/asm/
Dsha1-sparcv9.pl2 # Copyright 2007-2020 The OpenSSL Project Authors. All Rights Reserved.
19 # Performance improvement is not really impressive on pre-T1 CPU: +8%
21 # turned to be 40% faster than 64-bit code generated by Sun C 5.8 and
22 # >2x than 64-bit code generated by gcc 3.4. And there is a gimmick.
23 # X[16] vector is packed to 8 64-bit registers and as result nothing
26 # subject to [inter-thread] cache-thrashing hazard. The goal is to
28 # amount of active threads exceeds the number of physical cores.
31 # faster than software. Multi-process benchmark saturates at 11x
32 # single-process result on 8-core processor, or ~9GBps per 2.85GHz
285 save %sp,-STACK_FRAME,%sp
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