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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenEVEX2VEXTables.inc3 |* X86 EVEX2VEX tables *|
9 // X86 EVEX encoded instructions that have a VEX 128 encoding
13 { X86::VADDPDZ128rm, X86::VADDPDrm },
14 { X86::VADDPDZ128rr, X86::VADDPDrr },
15 { X86::VADDPSZ128rm, X86::VADDPSrm },
16 { X86::VADDPSZ128rr, X86::VADDPSrr },
17 { X86::VADDSDZrm, X86::VADDSDrm },
18 { X86::VADDSDZrm_Int, X86::VADDSDrm_Int },
19 { X86::VADDSDZrr, X86::VADDSDrr },
20 { X86::VADDSDZrr_Int, X86::VADDSDrr_Int },
[all …]
DX86GenRegisterInfo.inc18 namespace X86 {
305 } // end namespace X86
309 namespace X86 {
431 } // end namespace X86
436 namespace X86 {
451 } // end namespace X86
1147 { X86::AH },
1148 { X86::AL },
1149 { X86::BH },
1150 { X86::BL },
[all …]
DX86GenRegisterBank.inc12 namespace X86 {
18 } // end namespace X86
35 namespace X86 {
38 (1u << (X86::GR8RegClassID - 0)) |
39 (1u << (X86::GR16RegClassID - 0)) |
40 (1u << (X86::LOW32_ADDR_ACCESS_RBPRegClassID - 0)) |
41 (1u << (X86::LOW32_ADDR_ACCESSRegClassID - 0)) |
42 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID - 0)) |
43 (1u << (X86::GR8_NOREXRegClassID - 0)) |
44 (1u << (X86::GR8_ABCD_HRegClassID - 0)) |
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DX86GenAsmMatcher.inc4971 Inst.addOperand(MCOperand::createReg(X86::AX));
4974 Inst.addOperand(MCOperand::createReg(X86::EAX));
4977 Inst.addOperand(MCOperand::createReg(X86::RAX));
5043 Inst.addOperand(MCOperand::createReg(X86::ST1));
5046 Inst.addOperand(MCOperand::createReg(X86::ST0));
7090 case X86::AL: OpKind = MCK_AL; break;
7091 case X86::DL: OpKind = MCK_GR8_ABCD_L; break;
7092 case X86::CL: OpKind = MCK_CL; break;
7093 case X86::BL: OpKind = MCK_GR8_ABCD_L; break;
7094 case X86::AH: OpKind = MCK_GR8_ABCD_H; break;
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DX86GenCallingConv.inc174 X86::ECX, X86::EDX, X86::R8D, X86::R9D
186 X86::RCX, X86::RDX, X86::R8, X86::R9
198 X86::EDI, X86::ESI, X86::EDX, X86::ECX
210 X86::RDI, X86::RSI, X86::RDX, X86::RCX
232 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
245 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
258 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
268 if (unsigned Reg = State.AllocateReg(X86::K1)) {
396 if (unsigned Reg = State.AllocateReg(X86::ECX)) {
406 X86::EAX, X86::EDX, X86::ECX
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DX86GenFastISel.inc3 |* "Fast" Instruction Selector for the X86 target *|
46 return fastEmitInst_r(X86::VPABSBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill);
49 return fastEmitInst_r(X86::PABSBrr, &X86::VR128RegClass, Op0, Op0IsKill);
52 return fastEmitInst_r(X86::VPABSBrr, &X86::VR128RegClass, Op0, Op0IsKill);
61 return fastEmitInst_r(X86::VPABSBZ256rr, &X86::VR256XRegClass, Op0, Op0IsKill);
64 return fastEmitInst_r(X86::VPABSBYrr, &X86::VR256RegClass, Op0, Op0IsKill);
73 return fastEmitInst_r(X86::VPABSBZrr, &X86::VR512RegClass, Op0, Op0IsKill);
82 return fastEmitInst_r(X86::VPABSWZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill);
85 return fastEmitInst_r(X86::PABSWrr, &X86::VR128RegClass, Op0, Op0IsKill);
88 return fastEmitInst_r(X86::VPABSWrr, &X86::VR128RegClass, Op0, Op0IsKill);
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrFoldTables.cpp1 //===-- X86InstrFoldTables.cpp - X86 Instruction Folding Tables -----------===//
9 // This file contains the X86 memory folding tables.
31 // because as new instruction are added into holes in the X86 opcode map they
36 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
37 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
38 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
39 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
40 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
41 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
42 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
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DX86InstrInfo.cpp1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
9 // This file contains the X86 implementation of the TargetInstrInfo class.
14 #include "X86.h"
45 #define DEBUG_TYPE "x86-instr-info"
57 " fuse, but the X86 backend currently can't"),
80 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
81 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
82 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
83 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
84 X86::CATCHRET, in X86InstrInfo()
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DX86MCInstLower.cpp1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
9 // This file contains code to lower X86 MachineInstrs to their corresponding
303 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
321 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw in SimplifyMOVSX()
322 if (Op0 == X86::AX && Op1 == X86::AL) in SimplifyMOVSX()
323 NewOpcode = X86::CBW; in SimplifyMOVSX()
325 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl in SimplifyMOVSX()
326 if (Op0 == X86::EAX && Op1 == X86::AX) in SimplifyMOVSX()
327 NewOpcode = X86::CWDE; in SimplifyMOVSX()
329 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq in SimplifyMOVSX()
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DX86FloatingPoint.cpp25 #include "X86.h"
52 #define DEBUG_TYPE "x86-codegen"
84 StringRef getPassName() const override { return "X86 FP Stackifier"; } in getPassName()
131 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums"); in calcLiveInMask()
132 if (Reg >= X86::FP0 && Reg <= X86::FP6) { in calcLiveInMask()
133 Mask |= 1 << (Reg - X86::FP0); in calcLiveInMask()
195 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
202 /// getSTReg - Return the X86::ST(i) register which contains the specified
205 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
241 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
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DX86AvoidStoreForwardingBlocks.cpp54 #define DEBUG_TYPE "x86-avoid-SFB"
57 "x86-disable-avoid-SFB", cl::Hidden,
58 cl::desc("X86: Disable Store Forwarding Blocks fixup."), cl::init(false));
61 "x86-sfb-inspection-limit",
62 cl::desc("X86: Number of instructions backward to "
76 return "X86 Avoid Store Forwarding Blocks"; in getPassName()
133 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || in isXMMLoadOpcode()
134 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || in isXMMLoadOpcode()
135 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || in isXMMLoadOpcode()
136 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm || in isXMMLoadOpcode()
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DX86SpeculativeLoadHardening.cpp22 #include "X86.h"
63 #define PASS_KEY "x86-slh"
78 "x86-speculative-load-hardening",
128 return "X86 speculative load hardening"; in getPassName()
254 BuildMI(&MBB, DebugLoc(), TII.get(X86::JMP_1)).addMBB(&OldLayoutSucc); in splitEdge()
377 if (MI.getOpcode() == X86::LFENCE) in hasVulnerableLoad()
385 if (MI.getOpcode() == X86::MFENCE) in hasVulnerableLoad()
414 PS.emplace(MF, &X86::GR64_NOSPRegClass); in runOnMachineFunction()
447 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::MOV64ri32), PS->PoisonReg) in runOnMachineFunction()
460 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::LFENCE)); in runOnMachineFunction()
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DX86DomainReassignment.cpp15 #include "X86.h"
33 #define DEBUG_TYPE "x86-domain-reassignment"
38 "disable-x86-domain-reassignment", cl::Hidden,
39 cl::desc("X86: Disable Virtual Register Reassignment."), cl::init(false));
45 return X86::GR64RegClass.hasSubClassEq(RC) || in isGPR()
46 X86::GR32RegClass.hasSubClassEq(RC) || in isGPR()
47 X86::GR16RegClass.hasSubClassEq(RC) || in isGPR()
48 X86::GR8RegClass.hasSubClassEq(RC); in isGPR()
53 return X86::VK16RegClass.hasSubClassEq(RC); in isMask()
69 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
[all …]
DX86ExpandPseudo.cpp15 #include "X86.h"
28 #define DEBUG_TYPE "x86-pseudo"
29 #define X86_EXPAND_PSEUDO_NAME "X86 pseudo instruction expansion pass"
58 return "X86 pseudo instruction expansion pass"; in getPassName()
92 BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11) in INITIALIZE_PASS()
93 .addReg(X86::RIP) in INITIALIZE_PASS()
99 BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr)) in INITIALIZE_PASS()
101 .addReg(X86::R11); in INITIALIZE_PASS()
107 if (!MBB->isLiveIn(X86::EFLAGS)) in INITIALIZE_PASS()
108 MBB->addLiveIn(X86::EFLAGS); in INITIALIZE_PASS()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicsX86.h16 x86_3dnow_pavgusb = 6322, // llvm.x86.3dnow.pavgusb
17 x86_3dnow_pf2id, // llvm.x86.3dnow.pf2id
18 x86_3dnow_pfacc, // llvm.x86.3dnow.pfacc
19 x86_3dnow_pfadd, // llvm.x86.3dnow.pfadd
20 x86_3dnow_pfcmpeq, // llvm.x86.3dnow.pfcmpeq
21 x86_3dnow_pfcmpge, // llvm.x86.3dnow.pfcmpge
22 x86_3dnow_pfcmpgt, // llvm.x86.3dnow.pfcmpgt
23 x86_3dnow_pfmax, // llvm.x86.3dnow.pfmax
24 x86_3dnow_pfmin, // llvm.x86.3dnow.pfmin
25 x86_3dnow_pfmul, // llvm.x86.3dnow.pfmul
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
9 // This file provides X86 specific target descriptions.
74 return MI.getFlags() & X86::IP_HAS_LOCK; in hasLockPrefix()
79 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
89 {codeview::RegisterId::AL, X86::AL}, in initLLVMToSEHAndCVRegMapping()
90 {codeview::RegisterId::CL, X86::CL}, in initLLVMToSEHAndCVRegMapping()
91 {codeview::RegisterId::DL, X86::DL}, in initLLVMToSEHAndCVRegMapping()
92 {codeview::RegisterId::BL, X86::BL}, in initLLVMToSEHAndCVRegMapping()
93 {codeview::RegisterId::AH, X86::AH}, in initLLVMToSEHAndCVRegMapping()
94 {codeview::RegisterId::CH, X86::CH}, in initLLVMToSEHAndCVRegMapping()
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DX86InstPrinterCommon.cpp1 //===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===//
110 case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break; in printVPCOMMnemonic()
111 case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break; in printVPCOMMnemonic()
112 case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break; in printVPCOMMnemonic()
113 case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break; in printVPCOMMnemonic()
114 case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break; in printVPCOMMnemonic()
115 case X86::VPCOMUQmi: case X86::VPCOMUQri: OS << "uq\t"; break; in printVPCOMMnemonic()
116 case X86::VPCOMUWmi: case X86::VPCOMUWri: OS << "uw\t"; break; in printVPCOMMnemonic()
117 case X86::VPCOMWmi: case X86::VPCOMWri: OS << "w\t"; break; in printVPCOMMnemonic()
129 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri: in printVPCMPMnemonic()
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DX86IntelInstPrinter.cpp45 if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
46 STI.getFeatureBits()[X86::Mode16Bit]) { in printInst()
72 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
73 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
74 case X86::CMPSDrm: case X86::CMPSDrr: in printVecCompareInstr()
75 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: in printVecCompareInstr()
76 case X86::CMPSSrm: case X86::CMPSSrr: in printVecCompareInstr()
77 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: in printVecCompareInstr()
99 case X86::VCMPPDrmi: case X86::VCMPPDrri: in printVecCompareInstr()
100 case X86::VCMPPDYrmi: case X86::VCMPPDYrri: in printVecCompareInstr()
[all …]
DX86ATTInstPrinter.cpp56 if (MI->getOpcode() == X86::CALLpcrel32 && in printInst()
57 (STI.getFeatureBits()[X86::Mode64Bit])) { in printInst()
66 else if (MI->getOpcode() == X86::DATA16_PREFIX && in printInst()
67 STI.getFeatureBits()[X86::Mode16Bit]) { in printInst()
92 case X86::CMPPDrmi: case X86::CMPPDrri: in printVecCompareInstr()
93 case X86::CMPPSrmi: case X86::CMPPSrri: in printVecCompareInstr()
94 case X86::CMPSDrm: case X86::CMPSDrr: in printVecCompareInstr()
95 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: in printVecCompareInstr()
96 case X86::CMPSSrm: case X86::CMPSSrr: in printVecCompareInstr()
97 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: in printVecCompareInstr()
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DX86BaseInfo.h1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
10 // the X86 target useful for the compiler back-end and the MC libraries.
26 namespace X86 {
73 // X86 specific condition code. These correspond to X86_*_COND in
97 // which can't be represented on x86 with a single condition. These
139 case X86::TEST16i16: in classifyFirstOpcodeInMacroFusion()
140 case X86::TEST16mr: in classifyFirstOpcodeInMacroFusion()
141 case X86::TEST16ri: in classifyFirstOpcodeInMacroFusion()
142 case X86::TEST16rr: in classifyFirstOpcodeInMacroFusion()
143 case X86::TEST32i32: in classifyFirstOpcodeInMacroFusion()
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DX86AsmBackend.cpp1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
38 /// A wrapper for holding a mask of the values from X86::AlignBranchBoundaryKind
51 addKind(X86::AlignBranchFused); in operator =()
53 addKind(X86::AlignBranchJcc); in operator =()
55 addKind(X86::AlignBranchJmp); in operator =()
57 addKind(X86::AlignBranchCall); in operator =()
59 addKind(X86::AlignBranchRet); in operator =()
61 addKind(X86::AlignBranchIndirect); in operator =()
64 "'-x86-align-branch 'The branches's type is combination of jcc, " in operator =()
72 void addKind(X86::AlignBranchBoundaryKind Value) { AlignBranchKind |= Value; } in addKind()
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/third_party/ffmpeg/libavcodec/x86/
DMakefile1 OBJS += x86/constants.o \
4 OBJS-$(CONFIG_AC3DSP) += x86/ac3dsp_init.o
5 OBJS-$(CONFIG_AUDIODSP) += x86/audiodsp_init.o
6 OBJS-$(CONFIG_BLOCKDSP) += x86/blockdsp_init.o
7 OBJS-$(CONFIG_BSWAPDSP) += x86/bswapdsp_init.o
8 OBJS-$(CONFIG_DCT) += x86/dct_init.o
9 OBJS-$(CONFIG_DIRAC_DECODER) += x86/diracdsp_init.o \
10 x86/dirac_dwt_init.o
11 OBJS-$(CONFIG_FDCTDSP) += x86/fdctdsp_init.o
12 OBJS-$(CONFIG_FFT) += x86/fft_init.o
[all …]
/third_party/openssl/fuzz/
Doids.txt1 OBJ_rsadsi="\x2A\x86\x48\x86\xF7\x0D"
2 OBJ_pkcs="\x2A\x86\x48\x86\xF7\x0D\x01"
3 OBJ_md2="\x2A\x86\x48\x86\xF7\x0D\x02\x02"
4 OBJ_md5="\x2A\x86\x48\x86\xF7\x0D\x02\x05"
5 OBJ_rc4="\x2A\x86\x48\x86\xF7\x0D\x03\x04"
6 OBJ_rsaEncryption="\x2A\x86\x48\x86\xF7\x0D\x01\x01\x01"
7 OBJ_md2WithRSAEncryption="\x2A\x86\x48\x86\xF7\x0D\x01\x01\x02"
8 OBJ_md5WithRSAEncryption="\x2A\x86\x48\x86\xF7\x0D\x01\x01\x04"
9 OBJ_pbeWithMD2AndDES_CBC="\x2A\x86\x48\x86\xF7\x0D\x01\x05\x01"
10 OBJ_pbeWithMD5AndDES_CBC="\x2A\x86\x48\x86\xF7\x0D\x01\x05\x03"
[all …]
/third_party/ffmpeg/libavfilter/x86/
DMakefile1 OBJS-$(CONFIG_SCENE_SAD) += x86/scene_sad_init.o
3 OBJS-$(CONFIG_AFIR_FILTER) += x86/af_afir_init.o
4 OBJS-$(CONFIG_ANLMDN_FILTER) += x86/af_anlmdn_init.o
5 OBJS-$(CONFIG_ATADENOISE_FILTER) += x86/vf_atadenoise_init.o
6 OBJS-$(CONFIG_BLEND_FILTER) += x86/vf_blend_init.o
7 OBJS-$(CONFIG_BWDIF_FILTER) += x86/vf_bwdif_init.o
8 OBJS-$(CONFIG_COLORSPACE_FILTER) += x86/colorspacedsp_init.o
9 OBJS-$(CONFIG_CONVOLUTION_FILTER) += x86/vf_convolution_init.o
10 OBJS-$(CONFIG_EQ_FILTER) += x86/vf_eq_init.o
11 OBJS-$(CONFIG_FSPP_FILTER) += x86/vf_fspp_init.o
[all …]
/third_party/ninja/src/
Dclparser_perftest.cc24 …"Note: including file: C:\\Program Files (x86)\\Microsoft Visual Studio 14.0\\VC\\INCLUDE\\iostrea… in main()
25 …"Note: including file: C:\\Program Files (x86)\\Microsoft Visual Studio 14.0\\VC\\INCLUDE\\istrea… in main()
26 …"Note: including file: C:\\Program Files (x86)\\Microsoft Visual Studio 14.0\\VC\\INCLUDE\\ostre… in main()
27 …"Note: including file: C:\\Program Files (x86)\\Microsoft Visual Studio 14.0\\VC\\INCLUDE\\ios\… in main()
28 …"Note: including file: C:\\Program Files (x86)\\Microsoft Visual Studio 14.0\\VC\\INCLUDE\\xlo… in main()
29 …"Note: including file: C:\\Program Files (x86)\\Microsoft Visual Studio 14.0\\VC\\INCLUDE\\cl… in main()
30 …"Note: including file: C:\\Program Files (x86)\\Microsoft Visual Studio 14.0\\VC\\INCLUDE\\y… in main()
31 …"Note: including file: C:\\Program Files (x86)\\Microsoft Visual Studio 14.0\\VC\\INCLUDE\\… in main()
32 …"Note: including file: C:\\Program Files (x86)\\Microsoft Visual Studio 14.0\\VC\\INCLUDE\\… in main()
33 …"Note: including file: C:\\Program Files (x86)\\Microsoft Visual Studio 14.0\\VC\\INCLUDE\… in main()
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