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26<div class="titlepage"><div><div><h2 class="title" style="clear: both">
27<a name="fiber.speculation"></a><a name="speculation"></a><a class="link" href="speculation.html" title="Specualtive execution">Specualtive
28    execution</a>
29</h2></div></div></div>
30<h4>
31<a name="fiber.speculation.h0"></a>
32      <span class="phrase"><a name="fiber.speculation.hardware_transactional_memory"></a></span><a class="link" href="speculation.html#fiber.speculation.hardware_transactional_memory">Hardware
33      transactional memory</a>
34    </h4>
35<p>
36      With help of hardware transactional memory multiple logical processors execute
37      a critical region speculatively, e.g. without explicit synchronization.<br>
38      If the transactional execution completes successfully, then all memory operations
39      performed within the transactional region are commited without any inter-thread
40      serialization.<br> When the optimistic execution fails, the processor aborts
41      the transaction and discards all performed modifications.<br> In non-transactional
42      code a single lock serializes the access to a critical region. With a transactional
43      memory, multiple logical processor start a transaction and update the memory
44      (the data) inside the ciritical region. Unless some logical processors try
45      to update the same data, the transactions would always succeed.
46    </p>
47<h4>
48<a name="fiber.speculation.h1"></a>
49      <span class="phrase"><a name="fiber.speculation.intel_transactional_synchronisation_extensions__tsx_"></a></span><a class="link" href="speculation.html#fiber.speculation.intel_transactional_synchronisation_extensions__tsx_">Intel
50      Transactional Synchronisation Extensions (TSX)</a>
51    </h4>
52<p>
53      TSX is Intel's implementation of hardware transactional memory in modern Intel
54      processors<a href="#ftn.fiber.speculation.f0" class="footnote" name="fiber.speculation.f0"><sup class="footnote">[7]</sup></a>.<br> In TSX the hardware keeps track of which cachelines have
55      been read from and which have been written to in a transaction. The cache-line
56      size (64-byte) and the n-way set associative cache determine the maximum size
57      of memory in a transaction. For instance if a transaction modifies 9 cache-lines
58      at a processor with a 8-way set associative cache, the transaction will always
59      be aborted.
60    </p>
61<div class="note"><table border="0" summary="Note">
62<tr>
63<td rowspan="2" align="center" valign="top" width="25"><img alt="[Note]" src="../../../../../doc/src/images/note.png"></td>
64<th align="left">Note</th>
65</tr>
66<tr><td align="left" valign="top"><p>
67        TXS is enabled if property <code class="computeroutput"><span class="identifier">htm</span><span class="special">=</span><span class="identifier">tsx</span></code> is
68        specified at b2 command-line and <code class="computeroutput"><span class="identifier">BOOST_USE_TSX</span></code>
69        is applied to the compiler.
70      </p></td></tr>
71</table></div>
72<div class="note"><table border="0" summary="Note">
73<tr>
74<td rowspan="2" align="center" valign="top" width="25"><img alt="[Note]" src="../../../../../doc/src/images/note.png"></td>
75<th align="left">Note</th>
76</tr>
77<tr><td align="left" valign="top"><p>
78        A TSX-transaction will be aborted if the floating point state is modified
79        inside a critical region. As a consequence floating point operations, e.g.
80        store/load of floating point related registers during a fiber (context) switch
81        are disabled.
82      </p></td></tr>
83</table></div>
84<div class="important"><table border="0" summary="Important">
85<tr>
86<td rowspan="2" align="center" valign="top" width="25"><img alt="[Important]" src="../../../../../doc/src/images/important.png"></td>
87<th align="left">Important</th>
88</tr>
89<tr><td align="left" valign="top"><p>
90        TSX can not be used together with MSVC at this time!
91      </p></td></tr>
92</table></div>
93<p>
94      Boost.Fiber uses TSX-enabled spinlocks to protect critical regions (see section
95      <a class="link" href="tuning.html#tuning">Tuning</a>).
96    </p>
97<div class="footnotes">
98<br><hr style="width:100; text-align:left;margin-left: 0">
99<div id="ftn.fiber.speculation.f0" class="footnote"><p><a href="#fiber.speculation.f0" class="para"><sup class="para">[7] </sup></a>
100        intel.com: <a href="https://software.intel.com/en-us/node/695149" target="_top">Intel
101        Transactional Synchronization Extensions</a>
102      </p></div>
103</div>
104</div>
105<table xmlns:rev="http://www.cs.rpi.edu/~gregod/boost/tools/doc/revision" width="100%"><tr>
106<td align="left"></td>
107<td align="right"><div class="copyright-footer">Copyright © 2013 Oliver Kowalke<p>
108        Distributed under the Boost Software License, Version 1.0. (See accompanying
109        file LICENSE_1_0.txt or copy at <a href="http://www.boost.org/LICENSE_1_0.txt" target="_top">http://www.boost.org/LICENSE_1_0.txt</a>)
110      </p>
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