1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23 #include "main/mtypes.h"
24
25 #include "isl/isl.h"
26
27 #include "brw_context.h"
28 #include "brw_state.h"
29 #include "brw_defines.h"
30
31 enum isl_format
brw_isl_format_for_mesa_format(mesa_format mesa_format)32 brw_isl_format_for_mesa_format(mesa_format mesa_format)
33 {
34 /* This table is ordered according to the enum ordering in formats.h. We do
35 * expect that enum to be extended without our explicit initialization
36 * staying in sync, so we initialize to 0 even though
37 * ISL_FORMAT_R32G32B32A32_FLOAT happens to also be 0.
38 */
39 static const enum isl_format table[MESA_FORMAT_COUNT] = {
40 [0 ... MESA_FORMAT_COUNT-1] = ISL_FORMAT_UNSUPPORTED,
41
42 [MESA_FORMAT_R8G8B8A8_UNORM] = ISL_FORMAT_R8G8B8A8_UNORM,
43 [MESA_FORMAT_B8G8R8A8_UNORM] = ISL_FORMAT_B8G8R8A8_UNORM,
44 [MESA_FORMAT_R8G8B8X8_UNORM] = ISL_FORMAT_R8G8B8X8_UNORM,
45 [MESA_FORMAT_B8G8R8X8_UNORM] = ISL_FORMAT_B8G8R8X8_UNORM,
46 [MESA_FORMAT_RGB_UNORM8] = ISL_FORMAT_R8G8B8_UNORM,
47 [MESA_FORMAT_B5G6R5_UNORM] = ISL_FORMAT_B5G6R5_UNORM,
48 [MESA_FORMAT_B4G4R4A4_UNORM] = ISL_FORMAT_B4G4R4A4_UNORM,
49 [MESA_FORMAT_B5G5R5A1_UNORM] = ISL_FORMAT_B5G5R5A1_UNORM,
50 [MESA_FORMAT_LA_UNORM8] = ISL_FORMAT_L8A8_UNORM,
51 [MESA_FORMAT_LA_UNORM16] = ISL_FORMAT_L16A16_UNORM,
52 [MESA_FORMAT_A_UNORM8] = ISL_FORMAT_A8_UNORM,
53 [MESA_FORMAT_A_UNORM16] = ISL_FORMAT_A16_UNORM,
54 [MESA_FORMAT_L_UNORM8] = ISL_FORMAT_L8_UNORM,
55 [MESA_FORMAT_L_UNORM16] = ISL_FORMAT_L16_UNORM,
56 [MESA_FORMAT_I_UNORM8] = ISL_FORMAT_I8_UNORM,
57 [MESA_FORMAT_I_UNORM16] = ISL_FORMAT_I16_UNORM,
58 [MESA_FORMAT_YCBCR_REV] = ISL_FORMAT_YCRCB_NORMAL,
59 [MESA_FORMAT_YCBCR] = ISL_FORMAT_YCRCB_SWAPUVY,
60 [MESA_FORMAT_R_UNORM8] = ISL_FORMAT_R8_UNORM,
61 [MESA_FORMAT_RG_UNORM8] = ISL_FORMAT_R8G8_UNORM,
62 [MESA_FORMAT_R_UNORM16] = ISL_FORMAT_R16_UNORM,
63 [MESA_FORMAT_RG_UNORM16] = ISL_FORMAT_R16G16_UNORM,
64 [MESA_FORMAT_B10G10R10A2_UNORM] = ISL_FORMAT_B10G10R10A2_UNORM,
65 [MESA_FORMAT_S_UINT8] = ISL_FORMAT_R8_UINT,
66
67 [MESA_FORMAT_B8G8R8A8_SRGB] = ISL_FORMAT_B8G8R8A8_UNORM_SRGB,
68 [MESA_FORMAT_R8G8B8A8_SRGB] = ISL_FORMAT_R8G8B8A8_UNORM_SRGB,
69 [MESA_FORMAT_B8G8R8X8_SRGB] = ISL_FORMAT_B8G8R8X8_UNORM_SRGB,
70 [MESA_FORMAT_R_SRGB8] = ISL_FORMAT_L8_UNORM_SRGB,
71 [MESA_FORMAT_L_SRGB8] = ISL_FORMAT_L8_UNORM_SRGB,
72 [MESA_FORMAT_LA_SRGB8] = ISL_FORMAT_L8A8_UNORM_SRGB,
73 [MESA_FORMAT_SRGB_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
74 [MESA_FORMAT_SRGBA_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
75 [MESA_FORMAT_SRGBA_DXT3] = ISL_FORMAT_BC2_UNORM_SRGB,
76 [MESA_FORMAT_SRGBA_DXT5] = ISL_FORMAT_BC3_UNORM_SRGB,
77
78 [MESA_FORMAT_RGB_FXT1] = ISL_FORMAT_FXT1,
79 [MESA_FORMAT_RGBA_FXT1] = ISL_FORMAT_FXT1,
80 [MESA_FORMAT_RGB_DXT1] = ISL_FORMAT_BC1_UNORM,
81 [MESA_FORMAT_RGBA_DXT1] = ISL_FORMAT_BC1_UNORM,
82 [MESA_FORMAT_RGBA_DXT3] = ISL_FORMAT_BC2_UNORM,
83 [MESA_FORMAT_RGBA_DXT5] = ISL_FORMAT_BC3_UNORM,
84
85 [MESA_FORMAT_RGBA_FLOAT32] = ISL_FORMAT_R32G32B32A32_FLOAT,
86 [MESA_FORMAT_RGBA_FLOAT16] = ISL_FORMAT_R16G16B16A16_FLOAT,
87 [MESA_FORMAT_RGB_FLOAT32] = ISL_FORMAT_R32G32B32_FLOAT,
88 [MESA_FORMAT_A_FLOAT32] = ISL_FORMAT_A32_FLOAT,
89 [MESA_FORMAT_A_FLOAT16] = ISL_FORMAT_A16_FLOAT,
90 [MESA_FORMAT_L_FLOAT32] = ISL_FORMAT_L32_FLOAT,
91 [MESA_FORMAT_L_FLOAT16] = ISL_FORMAT_L16_FLOAT,
92 [MESA_FORMAT_LA_FLOAT32] = ISL_FORMAT_L32A32_FLOAT,
93 [MESA_FORMAT_LA_FLOAT16] = ISL_FORMAT_L16A16_FLOAT,
94 [MESA_FORMAT_I_FLOAT32] = ISL_FORMAT_I32_FLOAT,
95 [MESA_FORMAT_I_FLOAT16] = ISL_FORMAT_I16_FLOAT,
96 [MESA_FORMAT_R_FLOAT32] = ISL_FORMAT_R32_FLOAT,
97 [MESA_FORMAT_R_FLOAT16] = ISL_FORMAT_R16_FLOAT,
98 [MESA_FORMAT_RG_FLOAT32] = ISL_FORMAT_R32G32_FLOAT,
99 [MESA_FORMAT_RG_FLOAT16] = ISL_FORMAT_R16G16_FLOAT,
100
101 [MESA_FORMAT_R_SINT8] = ISL_FORMAT_R8_SINT,
102 [MESA_FORMAT_RG_SINT8] = ISL_FORMAT_R8G8_SINT,
103 [MESA_FORMAT_RGB_SINT8] = ISL_FORMAT_R8G8B8_SINT,
104 [MESA_FORMAT_RGBA_SINT8] = ISL_FORMAT_R8G8B8A8_SINT,
105 [MESA_FORMAT_R_SINT16] = ISL_FORMAT_R16_SINT,
106 [MESA_FORMAT_RG_SINT16] = ISL_FORMAT_R16G16_SINT,
107 [MESA_FORMAT_RGB_SINT16] = ISL_FORMAT_R16G16B16_SINT,
108 [MESA_FORMAT_RGBA_SINT16] = ISL_FORMAT_R16G16B16A16_SINT,
109 [MESA_FORMAT_R_SINT32] = ISL_FORMAT_R32_SINT,
110 [MESA_FORMAT_RG_SINT32] = ISL_FORMAT_R32G32_SINT,
111 [MESA_FORMAT_RGB_SINT32] = ISL_FORMAT_R32G32B32_SINT,
112 [MESA_FORMAT_RGBA_SINT32] = ISL_FORMAT_R32G32B32A32_SINT,
113
114 [MESA_FORMAT_R_UINT8] = ISL_FORMAT_R8_UINT,
115 [MESA_FORMAT_RG_UINT8] = ISL_FORMAT_R8G8_UINT,
116 [MESA_FORMAT_RGB_UINT8] = ISL_FORMAT_R8G8B8_UINT,
117 [MESA_FORMAT_RGBA_UINT8] = ISL_FORMAT_R8G8B8A8_UINT,
118 [MESA_FORMAT_R_UINT16] = ISL_FORMAT_R16_UINT,
119 [MESA_FORMAT_RG_UINT16] = ISL_FORMAT_R16G16_UINT,
120 [MESA_FORMAT_RGB_UINT16] = ISL_FORMAT_R16G16B16_UINT,
121 [MESA_FORMAT_RGBA_UINT16] = ISL_FORMAT_R16G16B16A16_UINT,
122 [MESA_FORMAT_R_UINT32] = ISL_FORMAT_R32_UINT,
123 [MESA_FORMAT_RG_UINT32] = ISL_FORMAT_R32G32_UINT,
124 [MESA_FORMAT_RGB_UINT32] = ISL_FORMAT_R32G32B32_UINT,
125 [MESA_FORMAT_RGBA_UINT32] = ISL_FORMAT_R32G32B32A32_UINT,
126
127 [MESA_FORMAT_R_SNORM8] = ISL_FORMAT_R8_SNORM,
128 [MESA_FORMAT_RG_SNORM8] = ISL_FORMAT_R8G8_SNORM,
129 [MESA_FORMAT_R8G8B8A8_SNORM] = ISL_FORMAT_R8G8B8A8_SNORM,
130 [MESA_FORMAT_R_SNORM16] = ISL_FORMAT_R16_SNORM,
131 [MESA_FORMAT_RG_SNORM16] = ISL_FORMAT_R16G16_SNORM,
132 [MESA_FORMAT_RGB_SNORM16] = ISL_FORMAT_R16G16B16_SNORM,
133 [MESA_FORMAT_RGBA_SNORM16] = ISL_FORMAT_R16G16B16A16_SNORM,
134 [MESA_FORMAT_RGBA_UNORM16] = ISL_FORMAT_R16G16B16A16_UNORM,
135
136 [MESA_FORMAT_R_RGTC1_UNORM] = ISL_FORMAT_BC4_UNORM,
137 [MESA_FORMAT_R_RGTC1_SNORM] = ISL_FORMAT_BC4_SNORM,
138 [MESA_FORMAT_RG_RGTC2_UNORM] = ISL_FORMAT_BC5_UNORM,
139 [MESA_FORMAT_RG_RGTC2_SNORM] = ISL_FORMAT_BC5_SNORM,
140
141 [MESA_FORMAT_ETC1_RGB8] = ISL_FORMAT_ETC1_RGB8,
142 [MESA_FORMAT_ETC2_RGB8] = ISL_FORMAT_ETC2_RGB8,
143 [MESA_FORMAT_ETC2_SRGB8] = ISL_FORMAT_ETC2_SRGB8,
144 [MESA_FORMAT_ETC2_RGBA8_EAC] = ISL_FORMAT_ETC2_EAC_RGBA8,
145 [MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = ISL_FORMAT_ETC2_EAC_SRGB8_A8,
146 [MESA_FORMAT_ETC2_R11_EAC] = ISL_FORMAT_EAC_R11,
147 [MESA_FORMAT_ETC2_RG11_EAC] = ISL_FORMAT_EAC_RG11,
148 [MESA_FORMAT_ETC2_SIGNED_R11_EAC] = ISL_FORMAT_EAC_SIGNED_R11,
149 [MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = ISL_FORMAT_EAC_SIGNED_RG11,
150 [MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = ISL_FORMAT_ETC2_RGB8_PTA,
151 [MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = ISL_FORMAT_ETC2_SRGB8_PTA,
152
153 [MESA_FORMAT_BPTC_RGBA_UNORM] = ISL_FORMAT_BC7_UNORM,
154 [MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM] = ISL_FORMAT_BC7_UNORM_SRGB,
155 [MESA_FORMAT_BPTC_RGB_SIGNED_FLOAT] = ISL_FORMAT_BC6H_SF16,
156 [MESA_FORMAT_BPTC_RGB_UNSIGNED_FLOAT] = ISL_FORMAT_BC6H_UF16,
157
158 [MESA_FORMAT_RGBA_ASTC_4x4] = ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16,
159 [MESA_FORMAT_RGBA_ASTC_5x4] = ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16,
160 [MESA_FORMAT_RGBA_ASTC_5x5] = ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16,
161 [MESA_FORMAT_RGBA_ASTC_6x5] = ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16,
162 [MESA_FORMAT_RGBA_ASTC_6x6] = ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16,
163 [MESA_FORMAT_RGBA_ASTC_8x5] = ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16,
164 [MESA_FORMAT_RGBA_ASTC_8x6] = ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16,
165 [MESA_FORMAT_RGBA_ASTC_8x8] = ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16,
166 [MESA_FORMAT_RGBA_ASTC_10x5] = ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16,
167 [MESA_FORMAT_RGBA_ASTC_10x6] = ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16,
168 [MESA_FORMAT_RGBA_ASTC_10x8] = ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16,
169 [MESA_FORMAT_RGBA_ASTC_10x10] = ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16,
170 [MESA_FORMAT_RGBA_ASTC_12x10] = ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16,
171 [MESA_FORMAT_RGBA_ASTC_12x12] = ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16,
172 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4] = ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB,
173 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4] = ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB,
174 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5] = ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB,
175 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5] = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB,
176 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6] = ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB,
177 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x5] = ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB,
178 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x6] = ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB,
179 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x8] = ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB,
180 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x5] = ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB,
181 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x6] = ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB,
182 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x8] = ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB,
183 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x10] = ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB,
184 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10] = ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB,
185 [MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12] = ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB,
186
187 [MESA_FORMAT_R9G9B9E5_FLOAT] = ISL_FORMAT_R9G9B9E5_SHAREDEXP,
188 [MESA_FORMAT_R11G11B10_FLOAT] = ISL_FORMAT_R11G11B10_FLOAT,
189
190 [MESA_FORMAT_R10G10B10A2_UNORM] = ISL_FORMAT_R10G10B10A2_UNORM,
191 [MESA_FORMAT_B10G10R10A2_UINT] = ISL_FORMAT_B10G10R10A2_UINT,
192 [MESA_FORMAT_R10G10B10A2_UINT] = ISL_FORMAT_R10G10B10A2_UINT,
193
194 [MESA_FORMAT_B5G5R5X1_UNORM] = ISL_FORMAT_B5G5R5X1_UNORM,
195 [MESA_FORMAT_R8G8B8X8_SRGB] = ISL_FORMAT_R8G8B8X8_UNORM_SRGB,
196 [MESA_FORMAT_B10G10R10X2_UNORM] = ISL_FORMAT_B10G10R10X2_UNORM,
197 [MESA_FORMAT_RGBX_UNORM16] = ISL_FORMAT_R16G16B16X16_UNORM,
198 [MESA_FORMAT_RGBX_FLOAT16] = ISL_FORMAT_R16G16B16X16_FLOAT,
199 [MESA_FORMAT_RGBX_FLOAT32] = ISL_FORMAT_R32G32B32X32_FLOAT,
200 };
201
202 assert(mesa_format < MESA_FORMAT_COUNT);
203 return table[mesa_format];
204 }
205
206 void
brw_screen_init_surface_formats(struct brw_screen * screen)207 brw_screen_init_surface_formats(struct brw_screen *screen)
208 {
209 const struct intel_device_info *devinfo = &screen->devinfo;
210 mesa_format format;
211
212 memset(&screen->mesa_format_supports_texture, 0,
213 sizeof(screen->mesa_format_supports_texture));
214
215 for (format = MESA_FORMAT_NONE + 1; format < MESA_FORMAT_COUNT; format++) {
216 if (!_mesa_get_format_name(format))
217 continue;
218 enum isl_format texture, render;
219 bool is_integer = _mesa_is_format_integer_color(format);
220
221 render = texture = brw_isl_format_for_mesa_format(format);
222
223 /* Only exposed with EXT_memory_object_* support which
224 * is not for older gens.
225 */
226 if (devinfo->ver < 7 && format == MESA_FORMAT_Z_UNORM16)
227 continue;
228
229 if (texture == ISL_FORMAT_UNSUPPORTED)
230 continue;
231
232 /* Don't advertise 8 and 16-bit RGB formats to core mesa. This ensures
233 * that they are renderable from an API perspective since core mesa will
234 * fall back to RGBA or RGBX (we can't render to non-power-of-two
235 * formats). For 8-bit, formats, this also keeps us from hitting some
236 * nasty corners in brw_miptree_map_blit if you ever try to map one.
237 */
238 int format_size = _mesa_get_format_bytes(format);
239 if (format_size == 3 || format_size == 6)
240 continue;
241
242 if (isl_format_supports_sampling(devinfo, texture) &&
243 (isl_format_supports_filtering(devinfo, texture) || is_integer))
244 screen->mesa_format_supports_texture[format] = true;
245
246 /* Re-map some render target formats to make them supported when they
247 * wouldn't be using their format for texturing.
248 */
249 switch (render) {
250 /* For these formats, we just need to read/write the first
251 * channel into R, which is to say that we just treat them as
252 * GL_RED.
253 */
254 case ISL_FORMAT_I32_FLOAT:
255 case ISL_FORMAT_L32_FLOAT:
256 render = ISL_FORMAT_R32_FLOAT;
257 break;
258 case ISL_FORMAT_I16_FLOAT:
259 case ISL_FORMAT_L16_FLOAT:
260 render = ISL_FORMAT_R16_FLOAT;
261 break;
262 case ISL_FORMAT_I8_UNORM:
263 case ISL_FORMAT_L8_UNORM:
264 render = ISL_FORMAT_R8_UNORM;
265 break;
266 case ISL_FORMAT_I16_UNORM:
267 case ISL_FORMAT_L16_UNORM:
268 render = ISL_FORMAT_R16_UNORM;
269 break;
270 case ISL_FORMAT_R16G16B16X16_UNORM:
271 render = ISL_FORMAT_R16G16B16A16_UNORM;
272 break;
273 case ISL_FORMAT_R16G16B16X16_FLOAT:
274 render = ISL_FORMAT_R16G16B16A16_FLOAT;
275 break;
276 case ISL_FORMAT_B8G8R8X8_UNORM:
277 /* XRGB is handled as ARGB because the chips in this family
278 * cannot render to XRGB targets. This means that we have to
279 * mask writes to alpha (ala glColorMask) and reconfigure the
280 * alpha blending hardware to use GL_ONE (or GL_ZERO) for
281 * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
282 * used. On Gfx8+ BGRX is actually allowed (but not RGBX).
283 */
284 if (!isl_format_supports_rendering(devinfo, texture))
285 render = ISL_FORMAT_B8G8R8A8_UNORM;
286 break;
287 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB:
288 if (!isl_format_supports_rendering(devinfo, texture))
289 render = ISL_FORMAT_B8G8R8A8_UNORM_SRGB;
290 break;
291 case ISL_FORMAT_R8G8B8X8_UNORM:
292 render = ISL_FORMAT_R8G8B8A8_UNORM;
293 break;
294 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB:
295 render = ISL_FORMAT_R8G8B8A8_UNORM_SRGB;
296 break;
297 default:
298 break;
299 }
300
301 /* Note that GL_EXT_texture_integer says that blending doesn't occur for
302 * integer, so we don't need hardware support for blending on it. Other
303 * than that, GL in general requires alpha blending for render targets,
304 * even though we don't support it for some formats.
305 */
306 if (isl_format_supports_rendering(devinfo, render) &&
307 (isl_format_supports_alpha_blending(devinfo, render) || is_integer)) {
308 screen->mesa_to_isl_render_format[format] = render;
309 screen->mesa_format_supports_render[format] = true;
310 }
311 }
312
313 /* We will check this table for FBO completeness, but the surface format
314 * table above only covered color rendering.
315 */
316 screen->mesa_format_supports_render[MESA_FORMAT_Z24_UNORM_S8_UINT] = true;
317 screen->mesa_format_supports_render[MESA_FORMAT_Z24_UNORM_X8_UINT] = true;
318 screen->mesa_format_supports_render[MESA_FORMAT_S_UINT8] = true;
319 screen->mesa_format_supports_render[MESA_FORMAT_Z_FLOAT32] = true;
320 screen->mesa_format_supports_render[MESA_FORMAT_Z32_FLOAT_S8X24_UINT] = true;
321 if (devinfo->ver >= 8)
322 screen->mesa_format_supports_render[MESA_FORMAT_Z_UNORM16] = true;
323
324 /* We remap depth formats to a supported texturing format in
325 * translate_tex_format().
326 */
327 screen->mesa_format_supports_texture[MESA_FORMAT_Z24_UNORM_S8_UINT] = true;
328 screen->mesa_format_supports_texture[MESA_FORMAT_Z24_UNORM_X8_UINT] = true;
329 screen->mesa_format_supports_texture[MESA_FORMAT_Z_FLOAT32] = true;
330 screen->mesa_format_supports_texture[MESA_FORMAT_Z32_FLOAT_S8X24_UINT] = true;
331 screen->mesa_format_supports_texture[MESA_FORMAT_S_UINT8] = true;
332
333 /* Benchmarking shows that Z16 is slower than Z24, so there's no reason to
334 * use it unless you're under memory (not memory bandwidth) pressure.
335 *
336 * Apparently, the GPU's depth scoreboarding works on a 32-bit granularity,
337 * which corresponds to one pixel in the depth buffer for Z24 or Z32 formats.
338 * However, it corresponds to two pixels with Z16, which means both need to
339 * hit the early depth case in order for it to happen.
340 *
341 * Other speculation is that we may be hitting increased fragment shader
342 * execution from GL_LEQUAL/GL_EQUAL depth tests at reduced precision.
343 *
344 * With the PMA stall workaround in place, Z16 is faster than Z24, as it
345 * should be.
346 */
347 if (devinfo->ver >= 8)
348 screen->mesa_format_supports_texture[MESA_FORMAT_Z_UNORM16] = true;
349
350 /* The RGBX formats are not renderable. Normally these get mapped
351 * internally to RGBA formats when rendering. However on Gfx9+ when this
352 * internal override is used fast clears don't work so they are disabled in
353 * brw_meta_fast_clear. To avoid this problem we can just pretend not to
354 * support RGBX formats at all. This will cause the upper layers of Mesa to
355 * pick the RGBA formats instead. This works fine because when it is used
356 * as a texture source the swizzle state is programmed to force the alpha
357 * channel to 1.0 anyway. We could also do this for all gens except that
358 * it's a bit more difficult when the hardware doesn't support texture
359 * swizzling. Gens using the blorp have further problems because that
360 * doesn't implement this swizzle override. We don't need to do this for
361 * BGRX because that actually is supported natively on Gfx8+.
362 */
363 if (devinfo->ver >= 9) {
364 static const mesa_format rgbx_formats[] = {
365 MESA_FORMAT_R8G8B8X8_UNORM,
366 MESA_FORMAT_R8G8B8X8_SRGB,
367 MESA_FORMAT_RGBX_UNORM16,
368 MESA_FORMAT_RGBX_FLOAT16,
369 MESA_FORMAT_RGBX_FLOAT32
370 };
371
372 for (int i = 0; i < ARRAY_SIZE(rgbx_formats); i++) {
373 screen->mesa_format_supports_texture[rgbx_formats[i]] = false;
374 screen->mesa_format_supports_render[rgbx_formats[i]] = false;
375 }
376 }
377
378 /* On hardware that lacks support for ETC1, we map ETC1 to RGBX
379 * during glCompressedTexImage2D(). See brw_mipmap_tree::wraps_etc1.
380 */
381 screen->mesa_format_supports_texture[MESA_FORMAT_ETC1_RGB8] = true;
382
383 /* On hardware that lacks support for ETC2, we map ETC2 to a suitable
384 * MESA_FORMAT during glCompressedTexImage2D().
385 * See brw_mipmap_tree::wraps_etc2.
386 */
387 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_RGB8] = true;
388 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SRGB8] = true;
389 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_RGBA8_EAC] = true;
390 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC] = true;
391 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_R11_EAC] = true;
392 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_RG11_EAC] = true;
393 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SIGNED_R11_EAC] = true;
394 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SIGNED_RG11_EAC] = true;
395 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1] = true;
396 screen->mesa_format_supports_texture[MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1] = true;
397 }
398
399 void
brw_init_surface_formats(struct brw_context * brw)400 brw_init_surface_formats(struct brw_context *brw)
401 {
402 struct brw_screen *screen = brw->screen;
403 struct gl_context *ctx = &brw->ctx;
404
405 brw->mesa_format_supports_render = screen->mesa_format_supports_render;
406 brw->mesa_to_isl_render_format = screen->mesa_to_isl_render_format;
407
408 STATIC_ASSERT(ARRAY_SIZE(ctx->TextureFormatSupported) ==
409 ARRAY_SIZE(screen->mesa_format_supports_texture));
410
411 for (unsigned i = 0; i < ARRAY_SIZE(ctx->TextureFormatSupported); ++i) {
412 ctx->TextureFormatSupported[i] = screen->mesa_format_supports_texture[i];
413 }
414 }
415
416 bool
brw_render_target_supported(struct brw_context * brw,struct gl_renderbuffer * rb)417 brw_render_target_supported(struct brw_context *brw,
418 struct gl_renderbuffer *rb)
419 {
420 const struct intel_device_info *devinfo = &brw->screen->devinfo;
421 mesa_format format = rb->Format;
422
423 /* Many integer formats are promoted to RGBA (like XRGB8888 is), which means
424 * we would consider them renderable even though we don't have surface
425 * support for their alpha behavior and don't have the blending unit
426 * available to fake it like we do for XRGB8888. Force them to being
427 * unsupported.
428 */
429 if (_mesa_is_format_integer_color(format) &&
430 rb->_BaseFormat != GL_RGBA &&
431 rb->_BaseFormat != GL_RG &&
432 rb->_BaseFormat != GL_RED)
433 return false;
434
435 /* Under some conditions, MSAA is not supported for formats whose width is
436 * more than 64 bits.
437 */
438 if (devinfo->ver < 8 &&
439 rb->NumSamples > 0 && _mesa_get_format_bytes(format) > 8) {
440 /* Gfx6: MSAA on >64 bit formats is unsupported. */
441 if (devinfo->ver <= 6)
442 return false;
443
444 /* Gfx7: 8x MSAA on >64 bit formats is unsupported. */
445 if (rb->NumSamples >= 8)
446 return false;
447 }
448
449 return brw->mesa_format_supports_render[format];
450 }
451
452 enum isl_format
translate_tex_format(struct brw_context * brw,mesa_format mesa_format,GLenum srgb_decode)453 translate_tex_format(struct brw_context *brw,
454 mesa_format mesa_format,
455 GLenum srgb_decode)
456 {
457 struct gl_context *ctx = &brw->ctx;
458 if (srgb_decode == GL_SKIP_DECODE_EXT)
459 mesa_format = _mesa_get_srgb_format_linear(mesa_format);
460
461 switch( mesa_format ) {
462
463 case MESA_FORMAT_Z_UNORM16:
464 return ISL_FORMAT_R16_UNORM;
465
466 case MESA_FORMAT_Z24_UNORM_S8_UINT:
467 case MESA_FORMAT_Z24_UNORM_X8_UINT:
468 return ISL_FORMAT_R24_UNORM_X8_TYPELESS;
469
470 case MESA_FORMAT_Z_FLOAT32:
471 return ISL_FORMAT_R32_FLOAT;
472
473 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
474 return ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS;
475
476 case MESA_FORMAT_RGBA_FLOAT32:
477 /* The value of this ISL surface format is 0, which tricks the
478 * assertion below.
479 */
480 return ISL_FORMAT_R32G32B32A32_FLOAT;
481
482 case MESA_FORMAT_RGBA_ASTC_4x4:
483 case MESA_FORMAT_RGBA_ASTC_5x4:
484 case MESA_FORMAT_RGBA_ASTC_5x5:
485 case MESA_FORMAT_RGBA_ASTC_6x5:
486 case MESA_FORMAT_RGBA_ASTC_6x6:
487 case MESA_FORMAT_RGBA_ASTC_8x5:
488 case MESA_FORMAT_RGBA_ASTC_8x6:
489 case MESA_FORMAT_RGBA_ASTC_8x8:
490 case MESA_FORMAT_RGBA_ASTC_10x5:
491 case MESA_FORMAT_RGBA_ASTC_10x6:
492 case MESA_FORMAT_RGBA_ASTC_10x8:
493 case MESA_FORMAT_RGBA_ASTC_10x10:
494 case MESA_FORMAT_RGBA_ASTC_12x10:
495 case MESA_FORMAT_RGBA_ASTC_12x12: {
496 enum isl_format isl_fmt =
497 brw_isl_format_for_mesa_format(mesa_format);
498
499 /**
500 * It is possible to process these formats using the LDR Profile
501 * or the Full Profile mode of the hardware. Because, it isn't
502 * possible to determine if an HDR or LDR texture is being rendered, we
503 * can't determine which mode to enable in the hardware. Therefore, to
504 * handle all cases, always default to Full profile unless we are
505 * processing sRGBs, which are incompatible with this mode.
506 */
507 if (ctx->Extensions.KHR_texture_compression_astc_hdr)
508 isl_fmt |= GFX9_SURFACE_ASTC_HDR_FORMAT_BIT;
509
510 return isl_fmt;
511 }
512
513 default:
514 return brw_isl_format_for_mesa_format(mesa_format);
515 }
516 }
517
518 /**
519 * Convert a MESA_FORMAT to the corresponding BRW_DEPTHFORMAT enum.
520 */
521 uint32_t
brw_depth_format(struct brw_context * brw,mesa_format format)522 brw_depth_format(struct brw_context *brw, mesa_format format)
523 {
524 const struct intel_device_info *devinfo = &brw->screen->devinfo;
525
526 switch (format) {
527 case MESA_FORMAT_Z_UNORM16:
528 return BRW_DEPTHFORMAT_D16_UNORM;
529 case MESA_FORMAT_Z_FLOAT32:
530 return BRW_DEPTHFORMAT_D32_FLOAT;
531 case MESA_FORMAT_Z24_UNORM_X8_UINT:
532 if (devinfo->ver >= 6) {
533 return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
534 } else {
535 /* Use D24_UNORM_S8, not D24_UNORM_X8.
536 *
537 * D24_UNORM_X8 was not introduced until Gfx5. (See the Ironlake PRM,
538 * Volume 2, Part 1, Section 8.4.6 "Depth/Stencil Buffer State", Bits
539 * 3DSTATE_DEPTH_BUFFER.Surface_Format).
540 *
541 * However, on Gfx5, D24_UNORM_X8 may be used only if separate
542 * stencil is enabled, and we never enable it. From the Ironlake PRM,
543 * same section as above, 3DSTATE_DEPTH_BUFFER's
544 * "Separate Stencil Buffer Enable" bit:
545 *
546 * "If this field is disabled, the Surface Format of the depth
547 * buffer cannot be D24_UNORM_X8_UINT."
548 */
549 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
550 }
551 case MESA_FORMAT_Z24_UNORM_S8_UINT:
552 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
553 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
554 return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT;
555 default:
556 unreachable("Unexpected depth format.");
557 }
558 }
559