1 /******************************************************************************* 2 Copyright (c) 2016 NVIDIA Corporation 3 4 Permission is hereby granted, free of charge, to any person obtaining a copy 5 of this software and associated documentation files (the "Software"), to 6 deal in the Software without restriction, including without limitation the 7 rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 8 sell copies of the Software, and to permit persons to whom the Software is 9 furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice shall be 12 included in all copies or substantial portions of the Software. 13 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 DEALINGS IN THE SOFTWARE. 21 22 *******************************************************************************/ 23 24 /* AUTO GENERATED FILE -- DO NOT EDIT */ 25 26 #ifndef __CLC0C0QMD_H__ 27 #define __CLC0C0QMD_H__ 28 29 /* 30 ** Queue Meta Data, Version 01_07 31 */ 32 33 // The below C preprocessor definitions describe "multi-word" structures, where 34 // fields may have bit numbers beyond 32. For example, MW(127:96) means 35 // the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" 36 // syntax is to distinguish from similar "X:Y" single-word definitions: the 37 // macros historically used for single-word definitions would fail with 38 // multi-word definitions. 39 // 40 // See nvmisc.h:DRF_VAL_MW() in the source code of the kernel 41 // interface layer of nvidia.ko for an example of how to manipulate 42 // these MW(X:Y) definitions. 43 44 #define NVC0C0_QMDV01_07_OUTER_PUT MW(30:0) 45 #define NVC0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) 46 #define NVC0C0_QMDV01_07_OUTER_GET MW(62:32) 47 #define NVC0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) 48 #define NVC0C0_QMDV01_07_INNER_GET MW(94:64) 49 #define NVC0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) 50 #define NVC0C0_QMDV01_07_INNER_PUT MW(126:96) 51 #define NVC0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) 52 #define NVC0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) 53 #define NVC0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) 54 #define NVC0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) 55 #define NVC0C0_QMDV01_07_SM_GLOBAL_CACHING_ENABLE MW(198:198) 56 #define NVC0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) 57 #define NVC0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 58 #define NVC0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 59 #define NVC0C0_QMDV01_07_IS_QUEUE MW(200:200) 60 #define NVC0C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 61 #define NVC0C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 62 #define NVC0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) 63 #define NVC0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 64 #define NVC0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 65 #define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) 66 #define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 67 #define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 68 #define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) 69 #define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 70 #define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 71 #define NVC0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) 72 #define NVC0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 73 #define NVC0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 74 #define NVC0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) 75 #define NVC0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 76 #define NVC0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 77 #define NVC0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) 78 #define NVC0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 79 #define NVC0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 80 #define NVC0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) 81 #define NVC0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 82 #define NVC0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 83 #define NVC0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) 84 #define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) 85 #define NVC0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) 86 #define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) 87 #define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 88 #define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 89 #define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) 90 #define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 91 #define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 92 #define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) 93 #define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 94 #define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 95 #define NVC0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) 96 #define NVC0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 97 #define NVC0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 98 #define NVC0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) 99 #define NVC0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 100 #define NVC0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 101 #define NVC0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) 102 #define NVC0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 103 #define NVC0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 104 #define NVC0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) 105 #define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) 106 #define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) 107 #define NVC0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) 108 #define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) 109 #define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) 110 #define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) 111 #define NVC0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) 112 #define NVC0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 113 #define NVC0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 114 #define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) 115 #define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 116 #define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 117 #define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) 118 #define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 119 #define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 120 #define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 121 #define NVC0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) 122 #define NVC0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 123 #define NVC0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 124 #define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) 125 #define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 126 #define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 127 #define NVC0C0_QMDV01_07_THROTTLED MW(372:372) 128 #define NVC0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 129 #define NVC0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 130 #define NVC0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) 131 #define NVC0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 132 #define NVC0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 133 #define NVC0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) 134 #define NVC0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 135 #define NVC0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 136 #define NVC0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) 137 #define NVC0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 138 #define NVC0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 139 #define NVC0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) 140 #define NVC0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 141 #define NVC0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 142 #define NVC0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) 143 #define NVC0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 144 #define NVC0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 145 #define NVC0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) 146 #define NVC0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 147 #define NVC0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 148 #define NVC0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) 149 #define NVC0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) 150 #define NVC0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) 151 #define NVC0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) 152 #define NVC0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) 153 #define NVC0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) 154 #define NVC0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) 155 #define NVC0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) 156 #define NVC0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) 157 #define NVC0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) 158 #define NVC0C0_QMDV01_07_QMD_VERSION MW(579:576) 159 #define NVC0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) 160 #define NVC0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) 161 #define NVC0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) 162 #define NVC0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) 163 #define NVC0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) 164 #define NVC0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) 165 #define NVC0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 166 #define NVC0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 167 #define NVC0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) 168 #define NVC0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) 169 #define NVC0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 170 #define NVC0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 171 #define NVC0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 172 #define NVC0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) 173 #define NVC0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) 174 #define NVC0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) 175 #define NVC0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) 176 #define NVC0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) 177 #define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) 178 #define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 179 #define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 180 #define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 181 #define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 182 #define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 183 #define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 184 #define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 185 #define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 186 #define NVC0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) 187 #define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) 188 #define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 189 #define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 190 #define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) 191 #define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 192 #define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 193 #define NVC0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) 194 #define NVC0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 195 #define NVC0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 196 #define NVC0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) 197 #define NVC0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) 198 #define NVC0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) 199 #define NVC0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) 200 #define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) 201 #define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 202 #define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 203 #define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 204 #define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 205 #define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 206 #define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 207 #define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 208 #define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 209 #define NVC0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) 210 #define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) 211 #define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 212 #define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 213 #define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) 214 #define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 215 #define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 216 #define NVC0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) 217 #define NVC0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 218 #define NVC0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 219 #define NVC0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) 220 #define NVC0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) 221 #define NVC0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) 222 #define NVC0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) 223 #define NVC0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) 224 #define NVC0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 225 #define NVC0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 226 #define NVC0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) 227 #define NVC0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) 228 #define NVC0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) 229 #define NVC0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) 230 #define NVC0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) 231 #define NVC0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) 232 #define NVC0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) 233 #define NVC0C0_QMDV01_07_SASS_VERSION MW(1535:1528) 234 #define NVC0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) 235 #define NVC0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) 236 #define NVC0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) 237 #define NVC0C0_QMDV01_07_HW_ONLY_SCG_TYPE MW(1599:1599) 238 #define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) 239 #define NVC0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) 240 #define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) 241 #define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 242 #define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 243 #define NVC0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) 244 #define NVC0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) 245 #define NVC0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) 246 #define NVC0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) 247 #define NVC0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) 248 #define NVC0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) 249 #define NVC0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) 250 #define NVC0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) 251 #define NVC0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) 252 #define NVC0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) 253 #define NVC0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) 254 #define NVC0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) 255 #define NVC0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) 256 257 258 /* 259 ** Queue Meta Data, Version 02_00 260 */ 261 262 #define NVC0C0_QMDV02_00_OUTER_PUT MW(30:0) 263 #define NVC0C0_QMDV02_00_OUTER_OVERFLOW MW(31:31) 264 #define NVC0C0_QMDV02_00_OUTER_GET MW(62:32) 265 #define NVC0C0_QMDV02_00_OUTER_STICKY_OVERFLOW MW(63:63) 266 #define NVC0C0_QMDV02_00_INNER_GET MW(94:64) 267 #define NVC0C0_QMDV02_00_INNER_OVERFLOW MW(95:95) 268 #define NVC0C0_QMDV02_00_INNER_PUT MW(126:96) 269 #define NVC0C0_QMDV02_00_INNER_STICKY_OVERFLOW MW(127:127) 270 #define NVC0C0_QMDV02_00_QMD_RESERVED_A_A MW(159:128) 271 #define NVC0C0_QMDV02_00_DEPENDENT_QMD_POINTER MW(191:160) 272 #define NVC0C0_QMDV02_00_QMD_GROUP_ID MW(197:192) 273 #define NVC0C0_QMDV02_00_SM_GLOBAL_CACHING_ENABLE MW(198:198) 274 #define NVC0C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) 275 #define NVC0C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 276 #define NVC0C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 277 #define NVC0C0_QMDV02_00_IS_QUEUE MW(200:200) 278 #define NVC0C0_QMDV02_00_IS_QUEUE_FALSE 0x00000000 279 #define NVC0C0_QMDV02_00_IS_QUEUE_TRUE 0x00000001 280 #define NVC0C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) 281 #define NVC0C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 282 #define NVC0C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 283 #define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) 284 #define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 285 #define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 286 #define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) 287 #define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 288 #define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 289 #define NVC0C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS MW(204:204) 290 #define NVC0C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 291 #define NVC0C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 292 #define NVC0C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) 293 #define NVC0C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 294 #define NVC0C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 295 #define NVC0C0_QMDV02_00_DEPENDENT_QMD_TYPE MW(206:206) 296 #define NVC0C0_QMDV02_00_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 297 #define NVC0C0_QMDV02_00_DEPENDENT_QMD_TYPE_GRID 0x00000001 298 #define NVC0C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY MW(207:207) 299 #define NVC0C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 300 #define NVC0C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 301 #define NVC0C0_QMDV02_00_QMD_RESERVED_B MW(223:208) 302 #define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_SIZE MW(248:224) 303 #define NVC0C0_QMDV02_00_QMD_RESERVED_C MW(249:249) 304 #define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) 305 #define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 306 #define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 307 #define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) 308 #define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 309 #define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 310 #define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) 311 #define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 312 #define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 313 #define NVC0C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE MW(253:253) 314 #define NVC0C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 315 #define NVC0C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 316 #define NVC0C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE MW(254:254) 317 #define NVC0C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 318 #define NVC0C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 319 #define NVC0C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) 320 #define NVC0C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 321 #define NVC0C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 322 #define NVC0C0_QMDV02_00_PROGRAM_OFFSET MW(287:256) 323 #define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) 324 #define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) 325 #define NVC0C0_QMDV02_00_QMD_RESERVED_D MW(335:328) 326 #define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) 327 #define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_ID MW(357:352) 328 #define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) 329 #define NVC0C0_QMDV02_00_RELEASE_MEMBAR_TYPE MW(366:366) 330 #define NVC0C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 331 #define NVC0C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 332 #define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) 333 #define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 334 #define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 335 #define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE MW(369:368) 336 #define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 337 #define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 338 #define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 339 #define NVC0C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS MW(370:370) 340 #define NVC0C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 341 #define NVC0C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 342 #define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) 343 #define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 344 #define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 345 #define NVC0C0_QMDV02_00_THROTTLED MW(372:372) 346 #define NVC0C0_QMDV02_00_THROTTLED_FALSE 0x00000000 347 #define NVC0C0_QMDV02_00_THROTTLED_TRUE 0x00000001 348 #define NVC0C0_QMDV02_00_API_VISIBLE_CALL_LIMIT MW(378:378) 349 #define NVC0C0_QMDV02_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 350 #define NVC0C0_QMDV02_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 351 #define NVC0C0_QMDV02_00_SAMPLER_INDEX MW(382:382) 352 #define NVC0C0_QMDV02_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 353 #define NVC0C0_QMDV02_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 354 #define NVC0C0_QMDV02_00_CTA_RASTER_WIDTH MW(415:384) 355 #define NVC0C0_QMDV02_00_CTA_RASTER_HEIGHT MW(431:416) 356 #define NVC0C0_QMDV02_00_QMD_RESERVED13A MW(447:432) 357 #define NVC0C0_QMDV02_00_CTA_RASTER_DEPTH MW(463:448) 358 #define NVC0C0_QMDV02_00_QMD_RESERVED14A MW(479:464) 359 #define NVC0C0_QMDV02_00_QMD_RESERVED15A MW(511:480) 360 #define NVC0C0_QMDV02_00_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) 361 #define NVC0C0_QMDV02_00_COALESCE_WAITING_PERIOD MW(529:522) 362 #define NVC0C0_QMDV02_00_SHARED_MEMORY_SIZE MW(561:544) 363 #define NVC0C0_QMDV02_00_QMD_RESERVED_G MW(575:562) 364 #define NVC0C0_QMDV02_00_QMD_VERSION MW(579:576) 365 #define NVC0C0_QMDV02_00_QMD_MAJOR_VERSION MW(583:580) 366 #define NVC0C0_QMDV02_00_QMD_RESERVED_H MW(591:584) 367 #define NVC0C0_QMDV02_00_CTA_THREAD_DIMENSION0 MW(607:592) 368 #define NVC0C0_QMDV02_00_CTA_THREAD_DIMENSION1 MW(623:608) 369 #define NVC0C0_QMDV02_00_CTA_THREAD_DIMENSION2 MW(639:624) 370 #define NVC0C0_QMDV02_00_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) 371 #define NVC0C0_QMDV02_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 372 #define NVC0C0_QMDV02_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 373 #define NVC0C0_QMDV02_00_QMD_RESERVED_I MW(671:648) 374 #define NVC0C0_QMDV02_00_SM_DISABLE_MASK_LOWER MW(703:672) 375 #define NVC0C0_QMDV02_00_SM_DISABLE_MASK_UPPER MW(735:704) 376 #define NVC0C0_QMDV02_00_RELEASE0_ADDRESS_LOWER MW(767:736) 377 #define NVC0C0_QMDV02_00_RELEASE0_ADDRESS_UPPER MW(775:768) 378 #define NVC0C0_QMDV02_00_QMD_RESERVED_J MW(783:776) 379 #define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP MW(790:788) 380 #define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 381 #define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 382 #define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 383 #define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 384 #define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 385 #define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 386 #define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 387 #define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 388 #define NVC0C0_QMDV02_00_QMD_RESERVED_K MW(791:791) 389 #define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT MW(793:792) 390 #define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 391 #define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 392 #define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE MW(794:794) 393 #define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 394 #define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 395 #define NVC0C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE MW(799:799) 396 #define NVC0C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 397 #define NVC0C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 398 #define NVC0C0_QMDV02_00_RELEASE0_PAYLOAD MW(831:800) 399 #define NVC0C0_QMDV02_00_RELEASE1_ADDRESS_LOWER MW(863:832) 400 #define NVC0C0_QMDV02_00_RELEASE1_ADDRESS_UPPER MW(871:864) 401 #define NVC0C0_QMDV02_00_QMD_RESERVED_L MW(879:872) 402 #define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP MW(886:884) 403 #define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 404 #define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 405 #define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 406 #define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 407 #define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 408 #define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 409 #define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 410 #define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 411 #define NVC0C0_QMDV02_00_QMD_RESERVED_M MW(887:887) 412 #define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT MW(889:888) 413 #define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 414 #define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 415 #define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE MW(890:890) 416 #define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 417 #define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 418 #define NVC0C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE MW(895:895) 419 #define NVC0C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 420 #define NVC0C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 421 #define NVC0C0_QMDV02_00_RELEASE1_PAYLOAD MW(927:896) 422 #define NVC0C0_QMDV02_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) 423 #define NVC0C0_QMDV02_00_QMD_RESERVED_N MW(954:952) 424 #define NVC0C0_QMDV02_00_BARRIER_COUNT MW(959:955) 425 #define NVC0C0_QMDV02_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) 426 #define NVC0C0_QMDV02_00_REGISTER_COUNT MW(991:984) 427 #define NVC0C0_QMDV02_00_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) 428 #define NVC0C0_QMDV02_00_SASS_VERSION MW(1023:1016) 429 #define NVC0C0_QMDV02_00_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) 430 #define NVC0C0_QMDV02_00_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) 431 #define NVC0C0_QMDV02_00_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) 432 #define NVC0C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) 433 #define NVC0C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 434 #define NVC0C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 435 #define NVC0C0_QMDV02_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) 436 #define NVC0C0_QMDV02_00_HW_ONLY_INNER_GET MW(1566:1536) 437 #define NVC0C0_QMDV02_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) 438 #define NVC0C0_QMDV02_00_HW_ONLY_INNER_PUT MW(1598:1568) 439 #define NVC0C0_QMDV02_00_HW_ONLY_SCG_TYPE MW(1599:1599) 440 #define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) 441 #define NVC0C0_QMDV02_00_QMD_RESERVED_Q MW(1630:1630) 442 #define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) 443 #define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 444 #define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 445 #define NVC0C0_QMDV02_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) 446 #define NVC0C0_QMDV02_00_CTA_RASTER_WIDTH_RESUME MW(1695:1664) 447 #define NVC0C0_QMDV02_00_CTA_RASTER_HEIGHT_RESUME MW(1711:1696) 448 #define NVC0C0_QMDV02_00_CTA_RASTER_DEPTH_RESUME MW(1727:1712) 449 #define NVC0C0_QMDV02_00_QMD_SPARE_G MW(1759:1728) 450 #define NVC0C0_QMDV02_00_QMD_SPARE_H MW(1791:1760) 451 #define NVC0C0_QMDV02_00_QMD_SPARE_I MW(1823:1792) 452 #define NVC0C0_QMDV02_00_QMD_SPARE_J MW(1855:1824) 453 #define NVC0C0_QMDV02_00_QMD_SPARE_K MW(1887:1856) 454 #define NVC0C0_QMDV02_00_QMD_SPARE_L MW(1919:1888) 455 #define NVC0C0_QMDV02_00_QMD_SPARE_M MW(1951:1920) 456 #define NVC0C0_QMDV02_00_QMD_SPARE_N MW(1983:1952) 457 #define NVC0C0_QMDV02_00_DEBUG_ID_UPPER MW(2015:1984) 458 #define NVC0C0_QMDV02_00_DEBUG_ID_LOWER MW(2047:2016) 459 460 461 /* 462 ** Queue Meta Data, Version 02_01 463 */ 464 465 #define NVC0C0_QMDV02_01_OUTER_PUT MW(30:0) 466 #define NVC0C0_QMDV02_01_OUTER_OVERFLOW MW(31:31) 467 #define NVC0C0_QMDV02_01_OUTER_GET MW(62:32) 468 #define NVC0C0_QMDV02_01_OUTER_STICKY_OVERFLOW MW(63:63) 469 #define NVC0C0_QMDV02_01_INNER_GET MW(94:64) 470 #define NVC0C0_QMDV02_01_INNER_OVERFLOW MW(95:95) 471 #define NVC0C0_QMDV02_01_INNER_PUT MW(126:96) 472 #define NVC0C0_QMDV02_01_INNER_STICKY_OVERFLOW MW(127:127) 473 #define NVC0C0_QMDV02_01_QMD_GROUP_ID MW(133:128) 474 #define NVC0C0_QMDV02_01_SM_GLOBAL_CACHING_ENABLE MW(134:134) 475 #define NVC0C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) 476 #define NVC0C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 477 #define NVC0C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 478 #define NVC0C0_QMDV02_01_IS_QUEUE MW(136:136) 479 #define NVC0C0_QMDV02_01_IS_QUEUE_FALSE 0x00000000 480 #define NVC0C0_QMDV02_01_IS_QUEUE_TRUE 0x00000001 481 #define NVC0C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) 482 #define NVC0C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 483 #define NVC0C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 484 #define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) 485 #define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 486 #define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 487 #define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) 488 #define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 489 #define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 490 #define NVC0C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS MW(140:140) 491 #define NVC0C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 492 #define NVC0C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 493 #define NVC0C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) 494 #define NVC0C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 495 #define NVC0C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 496 #define NVC0C0_QMDV02_01_DEPENDENT_QMD_TYPE MW(142:142) 497 #define NVC0C0_QMDV02_01_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 498 #define NVC0C0_QMDV02_01_DEPENDENT_QMD_TYPE_GRID 0x00000001 499 #define NVC0C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY MW(143:143) 500 #define NVC0C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 501 #define NVC0C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 502 #define NVC0C0_QMDV02_01_QMD_RESERVED_B MW(159:144) 503 #define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_SIZE MW(184:160) 504 #define NVC0C0_QMDV02_01_QMD_RESERVED_C MW(185:185) 505 #define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) 506 #define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 507 #define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 508 #define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) 509 #define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 510 #define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 511 #define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) 512 #define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 513 #define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 514 #define NVC0C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE MW(189:189) 515 #define NVC0C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 516 #define NVC0C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 517 #define NVC0C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE MW(190:190) 518 #define NVC0C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 519 #define NVC0C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 520 #define NVC0C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) 521 #define NVC0C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 522 #define NVC0C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 523 #define NVC0C0_QMDV02_01_CTA_RASTER_WIDTH_RESUME MW(223:192) 524 #define NVC0C0_QMDV02_01_CTA_RASTER_HEIGHT_RESUME MW(239:224) 525 #define NVC0C0_QMDV02_01_CTA_RASTER_DEPTH_RESUME MW(255:240) 526 #define NVC0C0_QMDV02_01_PROGRAM_OFFSET MW(287:256) 527 #define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) 528 #define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) 529 #define NVC0C0_QMDV02_01_QMD_RESERVED_D MW(335:328) 530 #define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) 531 #define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_ID MW(357:352) 532 #define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) 533 #define NVC0C0_QMDV02_01_RELEASE_MEMBAR_TYPE MW(366:366) 534 #define NVC0C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 535 #define NVC0C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 536 #define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) 537 #define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 538 #define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 539 #define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE MW(369:368) 540 #define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 541 #define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 542 #define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 543 #define NVC0C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS MW(370:370) 544 #define NVC0C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 545 #define NVC0C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 546 #define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) 547 #define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 548 #define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 549 #define NVC0C0_QMDV02_01_THROTTLED MW(372:372) 550 #define NVC0C0_QMDV02_01_THROTTLED_FALSE 0x00000000 551 #define NVC0C0_QMDV02_01_THROTTLED_TRUE 0x00000001 552 #define NVC0C0_QMDV02_01_API_VISIBLE_CALL_LIMIT MW(378:378) 553 #define NVC0C0_QMDV02_01_API_VISIBLE_CALL_LIMIT__32 0x00000000 554 #define NVC0C0_QMDV02_01_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 555 #define NVC0C0_QMDV02_01_SAMPLER_INDEX MW(382:382) 556 #define NVC0C0_QMDV02_01_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 557 #define NVC0C0_QMDV02_01_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 558 #define NVC0C0_QMDV02_01_CTA_RASTER_WIDTH MW(415:384) 559 #define NVC0C0_QMDV02_01_CTA_RASTER_HEIGHT MW(431:416) 560 #define NVC0C0_QMDV02_01_QMD_RESERVED13A MW(447:432) 561 #define NVC0C0_QMDV02_01_CTA_RASTER_DEPTH MW(463:448) 562 #define NVC0C0_QMDV02_01_QMD_RESERVED14A MW(479:464) 563 #define NVC0C0_QMDV02_01_DEPENDENT_QMD_POINTER MW(511:480) 564 #define NVC0C0_QMDV02_01_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) 565 #define NVC0C0_QMDV02_01_COALESCE_WAITING_PERIOD MW(529:522) 566 #define NVC0C0_QMDV02_01_SHARED_MEMORY_SIZE MW(561:544) 567 #define NVC0C0_QMDV02_01_QMD_RESERVED_G MW(575:562) 568 #define NVC0C0_QMDV02_01_QMD_VERSION MW(579:576) 569 #define NVC0C0_QMDV02_01_QMD_MAJOR_VERSION MW(583:580) 570 #define NVC0C0_QMDV02_01_QMD_RESERVED_H MW(591:584) 571 #define NVC0C0_QMDV02_01_CTA_THREAD_DIMENSION0 MW(607:592) 572 #define NVC0C0_QMDV02_01_CTA_THREAD_DIMENSION1 MW(623:608) 573 #define NVC0C0_QMDV02_01_CTA_THREAD_DIMENSION2 MW(639:624) 574 #define NVC0C0_QMDV02_01_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) 575 #define NVC0C0_QMDV02_01_CONSTANT_BUFFER_VALID_FALSE 0x00000000 576 #define NVC0C0_QMDV02_01_CONSTANT_BUFFER_VALID_TRUE 0x00000001 577 #define NVC0C0_QMDV02_01_QMD_RESERVED_I MW(671:648) 578 #define NVC0C0_QMDV02_01_SM_DISABLE_MASK_LOWER MW(703:672) 579 #define NVC0C0_QMDV02_01_SM_DISABLE_MASK_UPPER MW(735:704) 580 #define NVC0C0_QMDV02_01_RELEASE0_ADDRESS_LOWER MW(767:736) 581 #define NVC0C0_QMDV02_01_RELEASE0_ADDRESS_UPPER MW(775:768) 582 #define NVC0C0_QMDV02_01_QMD_RESERVED_J MW(783:776) 583 #define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP MW(790:788) 584 #define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 585 #define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 586 #define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 587 #define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 588 #define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 589 #define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 590 #define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 591 #define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 592 #define NVC0C0_QMDV02_01_QMD_RESERVED_K MW(791:791) 593 #define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT MW(793:792) 594 #define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 595 #define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 596 #define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE MW(794:794) 597 #define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 598 #define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 599 #define NVC0C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE MW(799:799) 600 #define NVC0C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 601 #define NVC0C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 602 #define NVC0C0_QMDV02_01_RELEASE0_PAYLOAD MW(831:800) 603 #define NVC0C0_QMDV02_01_RELEASE1_ADDRESS_LOWER MW(863:832) 604 #define NVC0C0_QMDV02_01_RELEASE1_ADDRESS_UPPER MW(871:864) 605 #define NVC0C0_QMDV02_01_QMD_RESERVED_L MW(879:872) 606 #define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP MW(886:884) 607 #define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 608 #define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 609 #define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 610 #define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 611 #define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 612 #define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 613 #define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 614 #define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 615 #define NVC0C0_QMDV02_01_QMD_RESERVED_M MW(887:887) 616 #define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT MW(889:888) 617 #define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 618 #define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 619 #define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE MW(890:890) 620 #define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 621 #define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 622 #define NVC0C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE MW(895:895) 623 #define NVC0C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 624 #define NVC0C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 625 #define NVC0C0_QMDV02_01_RELEASE1_PAYLOAD MW(927:896) 626 #define NVC0C0_QMDV02_01_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) 627 #define NVC0C0_QMDV02_01_QMD_RESERVED_N MW(954:952) 628 #define NVC0C0_QMDV02_01_BARRIER_COUNT MW(959:955) 629 #define NVC0C0_QMDV02_01_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) 630 #define NVC0C0_QMDV02_01_REGISTER_COUNT MW(991:984) 631 #define NVC0C0_QMDV02_01_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) 632 #define NVC0C0_QMDV02_01_SASS_VERSION MW(1023:1016) 633 #define NVC0C0_QMDV02_01_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) 634 #define NVC0C0_QMDV02_01_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) 635 #define NVC0C0_QMDV02_01_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) 636 #define NVC0C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) 637 #define NVC0C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 638 #define NVC0C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 639 #define NVC0C0_QMDV02_01_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) 640 #define NVC0C0_QMDV02_01_QMD_RESERVED_R MW(1567:1536) 641 #define NVC0C0_QMDV02_01_QMD_RESERVED_S MW(1599:1568) 642 #define NVC0C0_QMDV02_01_HW_ONLY_INNER_GET MW(1630:1600) 643 #define NVC0C0_QMDV02_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) 644 #define NVC0C0_QMDV02_01_HW_ONLY_INNER_PUT MW(1662:1632) 645 #define NVC0C0_QMDV02_01_HW_ONLY_SCG_TYPE MW(1663:1663) 646 #define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) 647 #define NVC0C0_QMDV02_01_QMD_RESERVED_Q MW(1694:1694) 648 #define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) 649 #define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 650 #define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 651 #define NVC0C0_QMDV02_01_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) 652 #define NVC0C0_QMDV02_01_QMD_SPARE_G MW(1759:1728) 653 #define NVC0C0_QMDV02_01_QMD_SPARE_H MW(1791:1760) 654 #define NVC0C0_QMDV02_01_QMD_SPARE_I MW(1823:1792) 655 #define NVC0C0_QMDV02_01_QMD_SPARE_J MW(1855:1824) 656 #define NVC0C0_QMDV02_01_QMD_SPARE_K MW(1887:1856) 657 #define NVC0C0_QMDV02_01_QMD_SPARE_L MW(1919:1888) 658 #define NVC0C0_QMDV02_01_QMD_SPARE_M MW(1951:1920) 659 #define NVC0C0_QMDV02_01_QMD_SPARE_N MW(1983:1952) 660 #define NVC0C0_QMDV02_01_DEBUG_ID_UPPER MW(2015:1984) 661 #define NVC0C0_QMDV02_01_DEBUG_ID_LOWER MW(2047:2016) 662 663 664 665 #endif // #ifndef __CLC0C0QMD_H__ 666