1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 /**
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
30 */
31
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
34
35 #include <stdio.h>
36
37 #include "radeon/radeon_winsys.h"
38
39 #include "util/disk_cache.h"
40 #include "util/u_blitter.h"
41 #include "util/list.h"
42 #include "util/u_range.h"
43 #include "util/slab.h"
44 #include "util/u_suballoc.h"
45 #include "util/u_transfer.h"
46 #include "util/u_threaded_context.h"
47
48 #include "compiler/nir/nir.h"
49
50 struct u_log_context;
51 #define ATI_VENDOR_ID 0x1002
52
53 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
54 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
55 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
56 #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
57
58 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
59 /* Pipeline & streamout query controls. */
60 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
61 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
62 #define R600_CONTEXT_FLUSH_FOR_RENDER_COND (1u << 3)
63 #define R600_CONTEXT_PRIVATE_FLAG (1u << 4)
64
65 /* special primitive types */
66 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
67
68 #define R600_NOT_QUERY 0xffffffff
69
70 /* Debug flags. */
71 #define DBG_VS (1 << PIPE_SHADER_VERTEX)
72 #define DBG_PS (1 << PIPE_SHADER_FRAGMENT)
73 #define DBG_GS (1 << PIPE_SHADER_GEOMETRY)
74 #define DBG_TCS (1 << PIPE_SHADER_TESS_CTRL)
75 #define DBG_TES (1 << PIPE_SHADER_TESS_EVAL)
76 #define DBG_CS (1 << PIPE_SHADER_COMPUTE)
77 #define DBG_ALL_SHADERS (DBG_FS - 1)
78 #define DBG_FS (1 << 6) /* fetch shader */
79 #define DBG_TEX (1 << 7)
80 #define DBG_NIR (1 << 8)
81 #define DBG_COMPUTE (1 << 9)
82 /* gap */
83 #define DBG_VM (1 << 11)
84 #define DBG_NO_IR (1 << 12)
85 #define DBG_NO_TGSI (1 << 13)
86 #define DBG_NO_ASM (1 << 14)
87 #define DBG_PREOPT_IR (1 << 15)
88 #define DBG_CHECK_IR (1 << 16)
89 #define DBG_NO_OPT_VARIANT (1 << 17)
90 #define DBG_FS_CORRECT_DERIVS_AFTER_KILL (1 << 18)
91 /* gaps */
92 #define DBG_TEST_DMA (1 << 20)
93 /* Bits 21-31 are reserved for the r600g driver. */
94 /* features */
95 #define DBG_NO_ASYNC_DMA (1ull << 32)
96 #define DBG_NO_HYPERZ (1ull << 33)
97 #define DBG_NO_DISCARD_RANGE (1ull << 34)
98 #define DBG_NO_2D_TILING (1ull << 35)
99 #define DBG_NO_TILING (1ull << 36)
100 #define DBG_SWITCH_ON_EOP (1ull << 37)
101 #define DBG_FORCE_DMA (1ull << 38)
102 #define DBG_PRECOMPILE (1ull << 39)
103 #define DBG_INFO (1ull << 40)
104 #define DBG_NO_WC (1ull << 41)
105 #define DBG_CHECK_VM (1ull << 42)
106 /* gap */
107 #define DBG_UNSAFE_MATH (1ull << 49)
108 #define DBG_TEST_VMFAULT_CP (1ull << 51)
109 #define DBG_TEST_VMFAULT_SDMA (1ull << 52)
110 #define DBG_TEST_VMFAULT_SHADER (1ull << 53)
111
112 #define R600_MAP_BUFFER_ALIGNMENT 64
113 #define R600_MAX_VIEWPORTS 16
114
115 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
116
117 enum r600_coherency {
118 R600_COHERENCY_NONE, /* no cache flushes needed */
119 R600_COHERENCY_SHADER,
120 R600_COHERENCY_CB_META,
121 };
122
123 #if UTIL_ARCH_BIG_ENDIAN
124 #define R600_BIG_ENDIAN 1
125 #else
126 #define R600_BIG_ENDIAN 0
127 #endif
128
129 struct r600_common_context;
130 struct r600_perfcounters;
131 struct tgsi_shader_info;
132 struct r600_qbo_state;
133
134 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
135 * at the moment.
136 */
137 struct r600_resource {
138 struct threaded_resource b;
139
140 /* Winsys objects. */
141 struct pb_buffer *buf;
142 uint64_t gpu_address;
143 /* Memory usage if the buffer placement is optimal. */
144 uint64_t vram_usage;
145 uint64_t gart_usage;
146
147 /* Resource properties. */
148 uint64_t bo_size;
149 unsigned bo_alignment;
150 enum radeon_bo_domain domains;
151 enum radeon_bo_flag flags;
152 unsigned bind_history;
153
154 /* The buffer range which is initialized (with a write transfer,
155 * streamout, DMA, or as a random access target). The rest of
156 * the buffer is considered invalid and can be mapped unsynchronized.
157 *
158 * This allows unsychronized mapping of a buffer range which hasn't
159 * been used yet. It's for applications which forget to use
160 * the unsynchronized map flag and expect the driver to figure it out.
161 */
162 struct util_range valid_buffer_range;
163
164 /* Whether the resource has been exported via resource_get_handle. */
165 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
166
167 /* Whether this resource is referenced by bindless handles. */
168 bool texture_handle_allocated;
169 bool image_handle_allocated;
170 bool compute_global_bo;
171
172 /*
173 * EG/Cayman only - for RAT operations hw need an immediate buffer
174 * to store results in.
175 */
176 struct r600_resource *immed_buffer;
177 };
178
179 struct r600_transfer {
180 struct threaded_transfer b;
181 struct r600_resource *staging;
182 };
183
184 struct r600_fmask_info {
185 uint64_t offset;
186 uint64_t size;
187 unsigned alignment;
188 unsigned pitch_in_pixels;
189 unsigned bank_height;
190 unsigned slice_tile_max;
191 unsigned tile_mode_index;
192 unsigned tile_swizzle;
193 };
194
195 struct r600_cmask_info {
196 uint64_t offset;
197 uint64_t size;
198 unsigned alignment;
199 unsigned slice_tile_max;
200 uint64_t base_address_reg;
201 };
202
203 struct r600_texture {
204 struct r600_resource resource;
205
206 uint64_t size;
207 unsigned num_level0_transfers;
208 enum pipe_format db_render_format;
209 bool is_depth;
210 bool db_compatible;
211 bool can_sample_z;
212 bool can_sample_s;
213 unsigned dirty_level_mask; /* each bit says if that mipmap is compressed */
214 unsigned stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
215 struct r600_texture *flushed_depth_texture;
216 struct radeon_surf surface;
217
218 /* Colorbuffer compression and fast clear. */
219 struct r600_fmask_info fmask;
220 struct r600_cmask_info cmask;
221 struct r600_resource *cmask_buffer;
222 unsigned cb_color_info; /* fast clear enable bit */
223 unsigned color_clear_value[2];
224 unsigned last_msaa_resolve_target_micro_mode;
225
226 /* Depth buffer compression and fast clear. */
227 uint64_t htile_offset;
228 bool depth_cleared; /* if it was cleared at least once */
229 float depth_clear_value;
230 bool stencil_cleared; /* if it was cleared at least once */
231 uint8_t stencil_clear_value;
232
233 bool non_disp_tiling; /* R600-Cayman only */
234
235 /* Counter that should be non-zero if the texture is bound to a
236 * framebuffer. Implemented in radeonsi only.
237 */
238 uint32_t framebuffers_bound;
239 };
240
241 struct r600_surface {
242 struct pipe_surface base;
243
244 /* These can vary with block-compressed textures. */
245 unsigned width0;
246 unsigned height0;
247
248 bool color_initialized;
249 bool depth_initialized;
250
251 /* Misc. color flags. */
252 bool alphatest_bypass;
253 bool export_16bpc;
254 bool color_is_int8;
255 bool color_is_int10;
256
257 /* Color registers. */
258 unsigned cb_color_info;
259 unsigned cb_color_base;
260 unsigned cb_color_view;
261 unsigned cb_color_size; /* R600 only */
262 unsigned cb_color_dim; /* EG only */
263 unsigned cb_color_pitch; /* EG and later */
264 unsigned cb_color_slice; /* EG and later */
265 unsigned cb_color_attrib; /* EG and later */
266 unsigned cb_color_fmask; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
267 unsigned cb_color_fmask_slice; /* EG and later */
268 unsigned cb_color_cmask; /* CB_COLORn_TILE (r600 only) */
269 unsigned cb_color_mask; /* R600 only */
270 struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
271 struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
272
273 /* DB registers. */
274 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
275 uint64_t db_stencil_base; /* EG and later */
276 uint64_t db_htile_data_base;
277 unsigned db_depth_info; /* R600 only, then SI and later */
278 unsigned db_z_info; /* EG and later */
279 unsigned db_depth_view;
280 unsigned db_depth_size;
281 unsigned db_depth_slice; /* EG and later */
282 unsigned db_stencil_info; /* EG and later */
283 unsigned db_prefetch_limit; /* R600 only */
284 unsigned db_htile_surface;
285 unsigned db_preload_control; /* EG and later */
286 };
287
288 struct r600_mmio_counter {
289 unsigned busy;
290 unsigned idle;
291 };
292
293 union r600_mmio_counters {
294 struct r600_mmio_counters_named {
295 /* For global GPU load including SDMA. */
296 struct r600_mmio_counter gpu;
297
298 /* GRBM_STATUS */
299 struct r600_mmio_counter spi;
300 struct r600_mmio_counter gui;
301 struct r600_mmio_counter ta;
302 struct r600_mmio_counter gds;
303 struct r600_mmio_counter vgt;
304 struct r600_mmio_counter ia;
305 struct r600_mmio_counter sx;
306 struct r600_mmio_counter wd;
307 struct r600_mmio_counter bci;
308 struct r600_mmio_counter sc;
309 struct r600_mmio_counter pa;
310 struct r600_mmio_counter db;
311 struct r600_mmio_counter cp;
312 struct r600_mmio_counter cb;
313
314 /* SRBM_STATUS2 */
315 struct r600_mmio_counter sdma;
316
317 /* CP_STAT */
318 struct r600_mmio_counter pfp;
319 struct r600_mmio_counter meq;
320 struct r600_mmio_counter me;
321 struct r600_mmio_counter surf_sync;
322 struct r600_mmio_counter cp_dma;
323 struct r600_mmio_counter scratch_ram;
324 } named;
325 unsigned array[sizeof(struct r600_mmio_counters_named) / sizeof(unsigned)];
326 };
327
328 struct r600_memory_object {
329 struct pipe_memory_object b;
330 struct pb_buffer *buf;
331 uint32_t stride;
332 uint32_t offset;
333 };
334
335 struct r600_common_screen {
336 struct pipe_screen b;
337 struct radeon_winsys *ws;
338 enum radeon_family family;
339 enum chip_class chip_class;
340 struct radeon_info info;
341 uint64_t debug_flags;
342 bool has_cp_dma;
343 bool has_streamout;
344
345 struct disk_cache *disk_shader_cache;
346
347 struct slab_parent_pool pool_transfers;
348
349 /* Texture filter settings. */
350 int force_aniso; /* -1 = disabled */
351
352 /* Auxiliary context. Mainly used to initialize resources.
353 * It must be locked prior to using and flushed before unlocking. */
354 struct pipe_context *aux_context;
355 mtx_t aux_context_lock;
356
357 /* This must be in the screen, because UE4 uses one context for
358 * compilation and another one for rendering.
359 */
360 unsigned num_compilations;
361 /* Along with ST_DEBUG=precompile, this should show if applications
362 * are loading shaders on demand. This is a monotonic counter.
363 */
364 unsigned num_shaders_created;
365 unsigned num_shader_cache_hits;
366
367 /* GPU load thread. */
368 mtx_t gpu_load_mutex;
369 thrd_t gpu_load_thread;
370 union r600_mmio_counters mmio_counters;
371 volatile unsigned gpu_load_stop_thread; /* bool */
372
373 char renderer_string[100];
374
375 /* Performance counters. */
376 struct r600_perfcounters *perfcounters;
377
378 /* If pipe_screen wants to recompute and re-emit the framebuffer,
379 * sampler, and image states of all contexts, it should atomically
380 * increment this.
381 *
382 * Each context will compare this with its own last known value of
383 * the counter before drawing and re-emit the states accordingly.
384 */
385 unsigned dirty_tex_counter;
386
387 /* Atomically increment this counter when an existing texture's
388 * metadata is enabled or disabled in a way that requires changing
389 * contexts' compressed texture binding masks.
390 */
391 unsigned compressed_colortex_counter;
392
393 struct {
394 /* Context flags to set so that all writes from earlier jobs
395 * in the CP are seen by L2 clients.
396 */
397 unsigned cp_to_L2;
398
399 /* Context flags to set so that all writes from earlier jobs
400 * that end in L2 are seen by CP.
401 */
402 unsigned L2_to_cp;
403
404 /* Context flags to set so that all writes from earlier
405 * compute jobs are seen by L2 clients.
406 */
407 unsigned compute_to_L2;
408 } barrier_flags;
409
410 struct nir_shader_compiler_options nir_options;
411 };
412
413 /* This encapsulates a state or an operation which can emitted into the GPU
414 * command stream. */
415 struct r600_atom {
416 void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
417 unsigned num_dw;
418 unsigned short id;
419 };
420
421 struct r600_so_target {
422 struct pipe_stream_output_target b;
423
424 /* The buffer where BUFFER_FILLED_SIZE is stored. */
425 struct r600_resource *buf_filled_size;
426 unsigned buf_filled_size_offset;
427 bool buf_filled_size_valid;
428
429 unsigned stride_in_dw;
430 };
431
432 struct r600_streamout {
433 struct r600_atom begin_atom;
434 bool begin_emitted;
435 unsigned num_dw_for_end;
436
437 unsigned enabled_mask;
438 unsigned num_targets;
439 struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
440
441 unsigned append_bitmask;
442 bool suspended;
443
444 /* External state which comes from the vertex shader,
445 * it must be set explicitly when binding a shader. */
446 uint16_t *stride_in_dw;
447 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
448
449 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
450 unsigned hw_enabled_mask;
451
452 /* The state of VGT_STRMOUT_(CONFIG|EN). */
453 struct r600_atom enable_atom;
454 bool streamout_enabled;
455 bool prims_gen_query_enabled;
456 int num_prims_gen_queries;
457 };
458
459 struct r600_signed_scissor {
460 int minx;
461 int miny;
462 int maxx;
463 int maxy;
464 };
465
466 struct r600_scissors {
467 struct r600_atom atom;
468 unsigned dirty_mask;
469 struct pipe_scissor_state states[R600_MAX_VIEWPORTS];
470 };
471
472 struct r600_viewports {
473 struct r600_atom atom;
474 unsigned dirty_mask;
475 unsigned depth_range_dirty_mask;
476 struct pipe_viewport_state states[R600_MAX_VIEWPORTS];
477 struct r600_signed_scissor as_scissor[R600_MAX_VIEWPORTS];
478 };
479
480 struct r600_ring {
481 struct radeon_cmdbuf cs;
482 void (*flush)(void *ctx, unsigned flags,
483 struct pipe_fence_handle **fence);
484 };
485
486 /* Saved CS data for debugging features. */
487 struct radeon_saved_cs {
488 uint32_t *ib;
489 unsigned num_dw;
490
491 struct radeon_bo_list_item *bo_list;
492 unsigned bo_count;
493 };
494
495 struct r600_common_context {
496 struct pipe_context b; /* base class */
497
498 struct r600_common_screen *screen;
499 struct radeon_winsys *ws;
500 struct radeon_winsys_ctx *ctx;
501 enum radeon_family family;
502 enum chip_class chip_class;
503 struct r600_ring gfx;
504 struct r600_ring dma;
505 struct pipe_fence_handle *last_gfx_fence;
506 struct pipe_fence_handle *last_sdma_fence;
507 struct r600_resource *eop_bug_scratch;
508 unsigned num_gfx_cs_flushes;
509 unsigned initial_gfx_cs_size;
510 unsigned last_dirty_tex_counter;
511 unsigned last_compressed_colortex_counter;
512 unsigned last_num_draw_calls;
513
514 struct threaded_context *tc;
515 struct u_suballocator allocator_zeroed_memory;
516 struct slab_child_pool pool_transfers;
517 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
518
519 /* Current unaccounted memory usage. */
520 uint64_t vram;
521 uint64_t gtt;
522
523 /* States. */
524 struct r600_streamout streamout;
525 struct r600_scissors scissors;
526 struct r600_viewports viewports;
527 bool scissor_enabled;
528 bool clip_halfz;
529 bool vs_writes_viewport_index;
530 bool vs_disables_clipping_viewport;
531
532 /* Additional context states. */
533 unsigned flags; /* flush flags */
534
535 /* Queries. */
536 /* Maintain the list of active queries for pausing between IBs. */
537 int num_occlusion_queries;
538 int num_perfect_occlusion_queries;
539 struct list_head active_queries;
540 unsigned num_cs_dw_queries_suspend;
541 /* Misc stats. */
542 unsigned num_draw_calls;
543 unsigned num_decompress_calls;
544 unsigned num_mrt_draw_calls;
545 unsigned num_prim_restart_calls;
546 unsigned num_spill_draw_calls;
547 unsigned num_compute_calls;
548 unsigned num_spill_compute_calls;
549 unsigned num_dma_calls;
550 unsigned num_cp_dma_calls;
551 unsigned num_vs_flushes;
552 unsigned num_ps_flushes;
553 unsigned num_cs_flushes;
554 unsigned num_cb_cache_flushes;
555 unsigned num_db_cache_flushes;
556 unsigned num_resident_handles;
557 uint64_t num_alloc_tex_transfer_bytes;
558
559 /* Render condition. */
560 struct r600_atom render_cond_atom;
561 struct pipe_query *render_cond;
562 unsigned render_cond_mode;
563 bool render_cond_invert;
564 bool render_cond_force_off; /* for u_blitter */
565
566 /* MSAA sample locations.
567 * The first index is the sample index.
568 * The second index is the coordinate: X, Y. */
569 float sample_locations_1x[1][2];
570 float sample_locations_2x[2][2];
571 float sample_locations_4x[4][2];
572 float sample_locations_8x[8][2];
573 float sample_locations_16x[16][2];
574
575 struct pipe_debug_callback debug;
576 struct pipe_device_reset_callback device_reset_callback;
577 struct u_log_context *log;
578
579 void *query_result_shader;
580
581 /* Copy one resource to another using async DMA. */
582 void (*dma_copy)(struct pipe_context *ctx,
583 struct pipe_resource *dst,
584 unsigned dst_level,
585 unsigned dst_x, unsigned dst_y, unsigned dst_z,
586 struct pipe_resource *src,
587 unsigned src_level,
588 const struct pipe_box *src_box);
589
590 void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
591 uint64_t offset, uint64_t size, unsigned value);
592
593 void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
594 uint64_t offset, uint64_t size, unsigned value,
595 enum r600_coherency coher);
596
597 void (*blit_decompress_depth)(struct pipe_context *ctx,
598 struct r600_texture *texture,
599 struct r600_texture *staging,
600 unsigned first_level, unsigned last_level,
601 unsigned first_layer, unsigned last_layer,
602 unsigned first_sample, unsigned last_sample);
603
604 /* Reallocate the buffer and update all resource bindings where
605 * the buffer is bound, including all resource descriptors. */
606 void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
607
608 /* Update all resource bindings where the buffer is bound, including
609 * all resource descriptors. This is invalidate_buffer without
610 * the invalidation. */
611 void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource *buf,
612 uint64_t old_gpu_address);
613
614 void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
615
616 /* This ensures there is enough space in the command stream. */
617 void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
618 bool include_draw_vbo);
619
620 void (*set_atom_dirty)(struct r600_common_context *ctx,
621 struct r600_atom *atom, bool dirty);
622
623 void (*check_vm_faults)(struct r600_common_context *ctx,
624 struct radeon_saved_cs *saved,
625 enum ring_type ring);
626 };
627
628 /* r600_buffer_common.c */
629 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
630 struct pb_buffer *buf,
631 enum radeon_bo_usage usage);
632 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
633 struct r600_resource *resource,
634 unsigned usage);
635 void r600_buffer_subdata(struct pipe_context *ctx,
636 struct pipe_resource *buffer,
637 unsigned usage, unsigned offset,
638 unsigned size, const void *data);
639 void r600_init_resource_fields(struct r600_common_screen *rscreen,
640 struct r600_resource *res,
641 uint64_t size, unsigned alignment);
642 bool r600_alloc_resource(struct r600_common_screen *rscreen,
643 struct r600_resource *res);
644 void r600_buffer_destroy(struct pipe_screen *screen, struct pipe_resource *buf);
645 void r600_buffer_flush_region(struct pipe_context *ctx,
646 struct pipe_transfer *transfer,
647 const struct pipe_box *rel_box);
648 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
649 const struct pipe_resource *templ,
650 unsigned alignment);
651 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
652 unsigned flags,
653 unsigned usage,
654 unsigned size,
655 unsigned alignment);
656 struct pipe_resource *
657 r600_buffer_from_user_memory(struct pipe_screen *screen,
658 const struct pipe_resource *templ,
659 void *user_memory);
660 void
661 r600_invalidate_resource(struct pipe_context *ctx,
662 struct pipe_resource *resource);
663 void r600_replace_buffer_storage(struct pipe_context *ctx,
664 struct pipe_resource *dst,
665 struct pipe_resource *src);
666 void *r600_buffer_transfer_map(struct pipe_context *ctx,
667 struct pipe_resource *resource,
668 unsigned level,
669 unsigned usage,
670 const struct pipe_box *box,
671 struct pipe_transfer **ptransfer);
672 void r600_buffer_transfer_unmap(struct pipe_context *ctx,
673 struct pipe_transfer *transfer);
674
675 /* r600_common_pipe.c */
676 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
677 unsigned event, unsigned event_flags,
678 unsigned data_sel,
679 struct r600_resource *buf, uint64_t va,
680 uint32_t new_fence, unsigned query_type);
681 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
682 void r600_gfx_wait_fence(struct r600_common_context *ctx,
683 struct r600_resource *buf,
684 uint64_t va, uint32_t ref, uint32_t mask);
685 void r600_draw_rectangle(struct blitter_context *blitter,
686 void *vertex_elements_cso,
687 blitter_get_vs_func get_vs,
688 int x1, int y1, int x2, int y2,
689 float depth, unsigned num_instances,
690 enum blitter_attrib_type type,
691 const union blitter_attrib *attrib);
692 bool r600_common_screen_init(struct r600_common_screen *rscreen,
693 struct radeon_winsys *ws);
694 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
695 void r600_preflush_suspend_features(struct r600_common_context *ctx);
696 void r600_postflush_resume_features(struct r600_common_context *ctx);
697 bool r600_common_context_init(struct r600_common_context *rctx,
698 struct r600_common_screen *rscreen,
699 unsigned context_flags);
700 void r600_common_context_cleanup(struct r600_common_context *rctx);
701 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
702 unsigned processor);
703 bool r600_extra_shader_checks(struct r600_common_screen *rscreen,
704 unsigned processor);
705 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
706 uint64_t offset, uint64_t size, unsigned value);
707 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
708 const struct pipe_resource *templ);
709 const char *r600_get_llvm_processor_name(enum radeon_family family);
710 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
711 struct r600_resource *dst, struct r600_resource *src);
712 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
713 struct radeon_saved_cs *saved, bool get_buffer_list);
714 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
715 bool r600_check_device_reset(struct r600_common_context *rctx);
716
717 /* r600_gpu_load.c */
718 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
719 uint64_t r600_begin_counter(struct r600_common_screen *rscreen, unsigned type);
720 unsigned r600_end_counter(struct r600_common_screen *rscreen, unsigned type,
721 uint64_t begin);
722
723 /* r600_perfcounters.c */
724 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
725
726 /* r600_query.c */
727 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
728 void r600_query_init(struct r600_common_context *rctx);
729 void r600_suspend_queries(struct r600_common_context *ctx);
730 void r600_resume_queries(struct r600_common_context *ctx);
731 void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen);
732
733 /* r600_streamout.c */
734 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
735 void r600_set_streamout_targets(struct pipe_context *ctx,
736 unsigned num_targets,
737 struct pipe_stream_output_target **targets,
738 const unsigned *offset);
739 void r600_emit_streamout_end(struct r600_common_context *rctx);
740 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
741 unsigned type, int diff);
742 void r600_streamout_init(struct r600_common_context *rctx);
743
744 /* r600_test_dma.c */
745 void r600_test_dma(struct r600_common_screen *rscreen);
746
747 /* r600_texture.c */
748 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
749 struct r600_texture *rdst,
750 unsigned dst_level, unsigned dstx,
751 unsigned dsty, unsigned dstz,
752 struct r600_texture *rsrc,
753 unsigned src_level,
754 const struct pipe_box *src_box);
755 void r600_texture_destroy(struct pipe_screen *screen, struct pipe_resource *ptex);
756 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
757 struct r600_texture *rtex,
758 unsigned nr_samples,
759 struct r600_fmask_info *out);
760 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
761 struct r600_texture *rtex,
762 struct r600_cmask_info *out);
763 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
764 struct pipe_resource *texture,
765 struct r600_texture **staging);
766 void r600_print_texture_info(struct r600_common_screen *rscreen,
767 struct r600_texture *rtex, struct u_log_context *log);
768 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
769 const struct pipe_resource *templ);
770 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
771 struct pipe_resource *texture,
772 const struct pipe_surface *templ,
773 unsigned width0, unsigned height0,
774 unsigned width, unsigned height);
775 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
776 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
777 struct pipe_framebuffer_state *fb,
778 struct r600_atom *fb_state,
779 unsigned *buffers, ubyte *dirty_cbufs,
780 const union pipe_color_union *color);
781 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
782 void r600_init_context_texture_functions(struct r600_common_context *rctx);
783 void eg_resource_alloc_immed(struct r600_common_screen *rscreen,
784 struct r600_resource *res,
785 unsigned immed_size);
786 void *r600_texture_transfer_map(struct pipe_context *ctx,
787 struct pipe_resource *texture,
788 unsigned level,
789 unsigned usage,
790 const struct pipe_box *box,
791 struct pipe_transfer **ptransfer);
792 void r600_texture_transfer_unmap(struct pipe_context *ctx,
793 struct pipe_transfer* transfer);
794
795 /* r600_viewport.c */
796 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
797 struct pipe_scissor_state *scissor);
798 void r600_viewport_set_rast_deps(struct r600_common_context *rctx,
799 bool scissor_enable, bool clip_halfz);
800 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
801 struct tgsi_shader_info *info);
802 void r600_init_viewport_functions(struct r600_common_context *rctx);
803
804 /* cayman_msaa.c */
805 extern const uint32_t eg_sample_locs_2x[4];
806 extern const unsigned eg_max_dist_2x;
807 extern const uint32_t eg_sample_locs_4x[4];
808 extern const unsigned eg_max_dist_4x;
809 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
810 unsigned sample_index, float *out_value);
811 void cayman_init_msaa(struct pipe_context *ctx);
812 void cayman_emit_msaa_state(struct radeon_cmdbuf *cs, int nr_samples,
813 int ps_iter_samples, int overrast_samples);
814
815
816 /* Inline helpers. */
817
r600_resource(struct pipe_resource * r)818 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
819 {
820 return (struct r600_resource*)r;
821 }
822
823 static inline void
r600_resource_reference(struct r600_resource ** ptr,struct r600_resource * res)824 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
825 {
826 pipe_resource_reference((struct pipe_resource **)ptr,
827 (struct pipe_resource *)res);
828 }
829
830 static inline void
r600_texture_reference(struct r600_texture ** ptr,struct r600_texture * res)831 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
832 {
833 pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
834 }
835
836 static inline void
r600_context_add_resource_size(struct pipe_context * ctx,struct pipe_resource * r)837 r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
838 {
839 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
840 struct r600_resource *res = (struct r600_resource *)r;
841
842 if (res) {
843 /* Add memory usage for need_gfx_cs_space */
844 rctx->vram += res->vram_usage;
845 rctx->gtt += res->gart_usage;
846 }
847 }
848
r600_get_strmout_en(struct r600_common_context * rctx)849 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
850 {
851 return rctx->streamout.streamout_enabled ||
852 rctx->streamout.prims_gen_query_enabled;
853 }
854
855 #define SQ_TEX_XY_FILTER_POINT 0x00
856 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
857 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
858 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
859
eg_tex_filter(unsigned filter,unsigned max_aniso)860 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
861 {
862 if (filter == PIPE_TEX_FILTER_LINEAR)
863 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
864 : SQ_TEX_XY_FILTER_BILINEAR;
865 else
866 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
867 : SQ_TEX_XY_FILTER_POINT;
868 }
869
r600_tex_aniso_filter(unsigned filter)870 static inline unsigned r600_tex_aniso_filter(unsigned filter)
871 {
872 if (filter < 2)
873 return 0;
874 if (filter < 4)
875 return 1;
876 if (filter < 8)
877 return 2;
878 if (filter < 16)
879 return 3;
880 return 4;
881 }
882
r600_wavefront_size(enum radeon_family family)883 static inline unsigned r600_wavefront_size(enum radeon_family family)
884 {
885 switch (family) {
886 case CHIP_RV610:
887 case CHIP_RS780:
888 case CHIP_RV620:
889 case CHIP_RS880:
890 return 16;
891 case CHIP_RV630:
892 case CHIP_RV635:
893 case CHIP_RV730:
894 case CHIP_RV710:
895 case CHIP_PALM:
896 case CHIP_CEDAR:
897 return 32;
898 default:
899 return 64;
900 }
901 }
902
903 static inline enum radeon_bo_priority
r600_get_sampler_view_priority(struct r600_resource * res)904 r600_get_sampler_view_priority(struct r600_resource *res)
905 {
906 if (res->b.b.target == PIPE_BUFFER)
907 return RADEON_PRIO_SAMPLER_BUFFER;
908
909 if (res->b.b.nr_samples > 1)
910 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
911
912 return RADEON_PRIO_SAMPLER_TEXTURE;
913 }
914
915 static inline bool
r600_can_sample_zs(struct r600_texture * tex,bool stencil_sampler)916 r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
917 {
918 return (stencil_sampler && tex->can_sample_s) ||
919 (!stencil_sampler && tex->can_sample_z);
920 }
921
922 static inline bool
r600_htile_enabled(struct r600_texture * tex,unsigned level)923 r600_htile_enabled(struct r600_texture *tex, unsigned level)
924 {
925 return tex->htile_offset && level == 0;
926 }
927
928 #define COMPUTE_DBG(rscreen, fmt, args...) \
929 do { \
930 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
931 } while (0);
932
933 #define R600_ERR(fmt, args...) \
934 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
935
936 /* For MSAA sample positions. */
937 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
938 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
939 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
940 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
941 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
942
S_FIXED(float value,unsigned frac_bits)943 static inline int S_FIXED(float value, unsigned frac_bits)
944 {
945 return value * (1 << frac_bits);
946 }
947
948 #endif
949