1 /** 2 * Copyright 2020-2021 Huawei Technologies Co., Ltd 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 #ifndef MINDSPORE_LITE_SRC_DELEGATE_TENSORRT_OP_ELEMENTWISE_TENSORRT_H_ 17 #define MINDSPORE_LITE_SRC_DELEGATE_TENSORRT_OP_ELEMENTWISE_TENSORRT_H_ 18 #include <string> 19 #include <vector> 20 #include <map> 21 #include "src/delegate/tensorrt/op/tensorrt_op.h" 22 23 namespace mindspore::lite { 24 class ElementWiseTensorRT : public TensorRTOp { 25 public: ElementWiseTensorRT(const schema::Primitive * primitive,const std::vector<mindspore::MSTensor> & in_tensors,const std::vector<mindspore::MSTensor> & out_tensors,const std::string & name)26 ElementWiseTensorRT(const schema::Primitive *primitive, const std::vector<mindspore::MSTensor> &in_tensors, 27 const std::vector<mindspore::MSTensor> &out_tensors, const std::string &name) 28 : TensorRTOp(primitive, in_tensors, out_tensors, name) {} 29 30 ~ElementWiseTensorRT() override = default; 31 32 int AddInnerOp(nvinfer1::INetworkDefinition *network) override; 33 34 int IsSupport(const schema::Primitive *primitive, const std::vector<mindspore::MSTensor> &in_tensors, 35 const std::vector<mindspore::MSTensor> &out_tensors) override; 36 37 private: 38 nvinfer1::ITensor *AddActivation(nvinfer1::INetworkDefinition *network, nvinfer1::ITensor *in_tensor); 39 40 int AddConstTensor(nvinfer1::INetworkDefinition *network); 41 42 nvinfer1::ElementWiseOperation element_wise_op_; 43 44 // index of first input MSTensor in the trt input tensor vector 45 size_t first_in_tensor_index_ = 0; 46 }; 47 } // namespace mindspore::lite 48 #endif // MINDSPORE_LITE_SRC_DELEGATE_TENSORRT_OP_ELEMENTWISE_TENSORRT_H_ 49