1 /*
2 * Copyright © 2014-2015 Broadcom
3 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/blob.h"
26 #include "util/debug.h"
27 #include "util/disk_cache.h"
28 #include "util/u_memory.h"
29 #include "util/ralloc.h"
30 #include "pipe/p_screen.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir/nir_control_flow.h"
34 #include "compiler/nir/nir_builder.h"
35 #include "compiler/nir/nir_serialize.h"
36 #include "compiler/shader_enums.h"
37
38 #include "tgsi_to_nir.h"
39 #include "tgsi/tgsi_parse.h"
40 #include "tgsi/tgsi_dump.h"
41 #include "tgsi/tgsi_info.h"
42 #include "tgsi/tgsi_scan.h"
43 #include "tgsi/tgsi_from_mesa.h"
44
45 #define SWIZ(X, Y, Z, W) (unsigned[4]){ \
46 TGSI_SWIZZLE_##X, \
47 TGSI_SWIZZLE_##Y, \
48 TGSI_SWIZZLE_##Z, \
49 TGSI_SWIZZLE_##W, \
50 }
51
52 struct ttn_reg_info {
53 /** nir register containing this TGSI index. */
54 nir_register *reg;
55 nir_variable *var;
56 /** Offset (in vec4s) from the start of var for this TGSI index. */
57 int offset;
58 };
59
60 struct ttn_compile {
61 union tgsi_full_token *token;
62 nir_builder build;
63 struct tgsi_shader_info *scan;
64
65 struct ttn_reg_info *output_regs;
66 struct ttn_reg_info *temp_regs;
67 nir_ssa_def **imm_defs;
68
69 unsigned num_samp_types;
70 nir_alu_type *samp_types;
71
72 nir_register *addr_reg;
73
74 nir_variable **inputs;
75 nir_variable **outputs;
76 nir_variable *samplers[PIPE_MAX_SAMPLERS];
77 nir_variable *images[PIPE_MAX_SHADER_IMAGES];
78 nir_variable *ssbo[PIPE_MAX_SHADER_BUFFERS];
79 uint32_t ubo_sizes[PIPE_MAX_CONSTANT_BUFFERS];
80
81 unsigned num_samplers;
82 unsigned num_images;
83 unsigned num_msaa_images;
84
85 nir_variable *input_var_face;
86 nir_variable *input_var_position;
87 nir_variable *input_var_point;
88
89 /* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */
90 unsigned next_imm;
91
92 bool cap_face_is_sysval;
93 bool cap_position_is_sysval;
94 bool cap_point_is_sysval;
95 bool cap_samplers_as_deref;
96 };
97
98 #define ttn_swizzle(b, src, x, y, z, w) \
99 nir_swizzle(b, src, SWIZ(x, y, z, w), 4)
100 #define ttn_channel(b, src, swiz) \
101 nir_channel(b, src, TGSI_SWIZZLE_##swiz)
102
103 gl_varying_slot
tgsi_varying_semantic_to_slot(unsigned semantic,unsigned index)104 tgsi_varying_semantic_to_slot(unsigned semantic, unsigned index)
105 {
106 switch (semantic) {
107 case TGSI_SEMANTIC_POSITION:
108 return VARYING_SLOT_POS;
109 case TGSI_SEMANTIC_COLOR:
110 if (index == 0)
111 return VARYING_SLOT_COL0;
112 else
113 return VARYING_SLOT_COL1;
114 case TGSI_SEMANTIC_BCOLOR:
115 if (index == 0)
116 return VARYING_SLOT_BFC0;
117 else
118 return VARYING_SLOT_BFC1;
119 case TGSI_SEMANTIC_FOG:
120 return VARYING_SLOT_FOGC;
121 case TGSI_SEMANTIC_PSIZE:
122 return VARYING_SLOT_PSIZ;
123 case TGSI_SEMANTIC_GENERIC:
124 assert(index < 32);
125 return VARYING_SLOT_VAR0 + index;
126 case TGSI_SEMANTIC_FACE:
127 return VARYING_SLOT_FACE;
128 case TGSI_SEMANTIC_EDGEFLAG:
129 return VARYING_SLOT_EDGE;
130 case TGSI_SEMANTIC_PRIMID:
131 return VARYING_SLOT_PRIMITIVE_ID;
132 case TGSI_SEMANTIC_CLIPDIST:
133 if (index == 0)
134 return VARYING_SLOT_CLIP_DIST0;
135 else
136 return VARYING_SLOT_CLIP_DIST1;
137 case TGSI_SEMANTIC_CLIPVERTEX:
138 return VARYING_SLOT_CLIP_VERTEX;
139 case TGSI_SEMANTIC_TEXCOORD:
140 assert(index < 8);
141 return VARYING_SLOT_TEX0 + index;
142 case TGSI_SEMANTIC_PCOORD:
143 return VARYING_SLOT_PNTC;
144 case TGSI_SEMANTIC_VIEWPORT_INDEX:
145 return VARYING_SLOT_VIEWPORT;
146 case TGSI_SEMANTIC_LAYER:
147 return VARYING_SLOT_LAYER;
148 case TGSI_SEMANTIC_TESSINNER:
149 return VARYING_SLOT_TESS_LEVEL_INNER;
150 case TGSI_SEMANTIC_TESSOUTER:
151 return VARYING_SLOT_TESS_LEVEL_OUTER;
152 default:
153 fprintf(stderr, "Bad TGSI semantic: %d/%d\n", semantic, index);
154 abort();
155 }
156 }
157
158 static enum gl_frag_depth_layout
ttn_get_depth_layout(unsigned tgsi_fs_depth_layout)159 ttn_get_depth_layout(unsigned tgsi_fs_depth_layout)
160 {
161 switch (tgsi_fs_depth_layout) {
162 case TGSI_FS_DEPTH_LAYOUT_NONE:
163 return FRAG_DEPTH_LAYOUT_NONE;
164 case TGSI_FS_DEPTH_LAYOUT_ANY:
165 return FRAG_DEPTH_LAYOUT_ANY;
166 case TGSI_FS_DEPTH_LAYOUT_GREATER:
167 return FRAG_DEPTH_LAYOUT_GREATER;
168 case TGSI_FS_DEPTH_LAYOUT_LESS:
169 return FRAG_DEPTH_LAYOUT_LESS;
170 case TGSI_FS_DEPTH_LAYOUT_UNCHANGED:
171 return FRAG_DEPTH_LAYOUT_UNCHANGED;
172 default:
173 unreachable("bad TGSI FS depth layout");
174 }
175 }
176
177 static nir_ssa_def *
ttn_src_for_dest(nir_builder * b,nir_alu_dest * dest)178 ttn_src_for_dest(nir_builder *b, nir_alu_dest *dest)
179 {
180 nir_alu_src src;
181 memset(&src, 0, sizeof(src));
182
183 if (dest->dest.is_ssa)
184 src.src = nir_src_for_ssa(&dest->dest.ssa);
185 else {
186 assert(!dest->dest.reg.indirect);
187 src.src = nir_src_for_reg(dest->dest.reg.reg);
188 src.src.reg.base_offset = dest->dest.reg.base_offset;
189 }
190
191 for (int i = 0; i < 4; i++)
192 src.swizzle[i] = i;
193
194 return nir_mov_alu(b, src, 4);
195 }
196
197 static enum glsl_interp_mode
ttn_translate_interp_mode(unsigned tgsi_interp)198 ttn_translate_interp_mode(unsigned tgsi_interp)
199 {
200 switch (tgsi_interp) {
201 case TGSI_INTERPOLATE_CONSTANT:
202 return INTERP_MODE_FLAT;
203 case TGSI_INTERPOLATE_LINEAR:
204 return INTERP_MODE_NOPERSPECTIVE;
205 case TGSI_INTERPOLATE_PERSPECTIVE:
206 return INTERP_MODE_SMOOTH;
207 case TGSI_INTERPOLATE_COLOR:
208 return INTERP_MODE_NONE;
209 default:
210 unreachable("bad TGSI interpolation mode");
211 }
212 }
213
214 static void
ttn_emit_declaration(struct ttn_compile * c)215 ttn_emit_declaration(struct ttn_compile *c)
216 {
217 nir_builder *b = &c->build;
218 struct tgsi_full_declaration *decl = &c->token->FullDeclaration;
219 unsigned array_size = decl->Range.Last - decl->Range.First + 1;
220 unsigned file = decl->Declaration.File;
221 unsigned i;
222
223 if (file == TGSI_FILE_TEMPORARY) {
224 if (decl->Declaration.Array) {
225 /* for arrays, we create variables instead of registers: */
226 nir_variable *var =
227 nir_variable_create(b->shader, nir_var_shader_temp,
228 glsl_array_type(glsl_vec4_type(), array_size, 0),
229 ralloc_asprintf(b->shader, "arr_%d",
230 decl->Array.ArrayID));
231
232 for (i = 0; i < array_size; i++) {
233 /* point all the matching slots to the same var,
234 * with appropriate offset set, mostly just so
235 * we know what to do when tgsi does a non-indirect
236 * access
237 */
238 c->temp_regs[decl->Range.First + i].reg = NULL;
239 c->temp_regs[decl->Range.First + i].var = var;
240 c->temp_regs[decl->Range.First + i].offset = i;
241 }
242 } else {
243 for (i = 0; i < array_size; i++) {
244 nir_register *reg = nir_local_reg_create(b->impl);
245 reg->num_components = 4;
246 c->temp_regs[decl->Range.First + i].reg = reg;
247 c->temp_regs[decl->Range.First + i].var = NULL;
248 c->temp_regs[decl->Range.First + i].offset = 0;
249 }
250 }
251 } else if (file == TGSI_FILE_ADDRESS) {
252 c->addr_reg = nir_local_reg_create(b->impl);
253 c->addr_reg->num_components = 4;
254 } else if (file == TGSI_FILE_SYSTEM_VALUE) {
255 /* Nothing to record for system values. */
256 } else if (file == TGSI_FILE_BUFFER) {
257 /* Nothing to record for buffers. */
258 } else if (file == TGSI_FILE_IMAGE) {
259 /* Nothing to record for images. */
260 } else if (file == TGSI_FILE_SAMPLER) {
261 /* Nothing to record for samplers. */
262 } else if (file == TGSI_FILE_SAMPLER_VIEW) {
263 struct tgsi_declaration_sampler_view *sview = &decl->SamplerView;
264 nir_alu_type type;
265
266 assert((sview->ReturnTypeX == sview->ReturnTypeY) &&
267 (sview->ReturnTypeX == sview->ReturnTypeZ) &&
268 (sview->ReturnTypeX == sview->ReturnTypeW));
269
270 switch (sview->ReturnTypeX) {
271 case TGSI_RETURN_TYPE_SINT:
272 type = nir_type_int32;
273 break;
274 case TGSI_RETURN_TYPE_UINT:
275 type = nir_type_uint32;
276 break;
277 case TGSI_RETURN_TYPE_FLOAT:
278 default:
279 type = nir_type_float32;
280 break;
281 }
282
283 for (i = 0; i < array_size; i++) {
284 c->samp_types[decl->Range.First + i] = type;
285 }
286 } else {
287 bool is_array = (array_size > 1);
288
289 assert(file == TGSI_FILE_INPUT ||
290 file == TGSI_FILE_OUTPUT ||
291 file == TGSI_FILE_CONSTANT);
292
293 /* nothing to do for UBOs: */
294 if ((file == TGSI_FILE_CONSTANT) && decl->Declaration.Dimension &&
295 decl->Dim.Index2D != 0) {
296 b->shader->info.num_ubos =
297 MAX2(b->shader->info.num_ubos, decl->Dim.Index2D);
298 c->ubo_sizes[decl->Dim.Index2D] =
299 MAX2(c->ubo_sizes[decl->Dim.Index2D], decl->Range.Last * 16);
300 return;
301 }
302
303 if ((file == TGSI_FILE_INPUT) || (file == TGSI_FILE_OUTPUT)) {
304 is_array = (is_array && decl->Declaration.Array &&
305 (decl->Array.ArrayID != 0));
306 }
307
308 for (i = 0; i < array_size; i++) {
309 unsigned idx = decl->Range.First + i;
310 nir_variable *var = rzalloc(b->shader, nir_variable);
311
312 var->data.driver_location = idx;
313
314 var->type = glsl_vec4_type();
315 if (is_array)
316 var->type = glsl_array_type(var->type, array_size, 0);
317
318 switch (file) {
319 case TGSI_FILE_INPUT:
320 var->data.read_only = true;
321 var->data.mode = nir_var_shader_in;
322 var->name = ralloc_asprintf(var, "in_%d", idx);
323
324 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
325 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
326 var->type = glsl_bool_type();
327 if (c->cap_face_is_sysval) {
328 var->data.mode = nir_var_system_value;
329 var->data.location = SYSTEM_VALUE_FRONT_FACE;
330 } else {
331 var->data.location = VARYING_SLOT_FACE;
332 }
333 c->input_var_face = var;
334 } else if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
335 if (c->cap_position_is_sysval) {
336 var->data.mode = nir_var_system_value;
337 var->data.location = SYSTEM_VALUE_FRAG_COORD;
338 } else {
339 var->data.location = VARYING_SLOT_POS;
340 }
341 c->input_var_position = var;
342 } else if (decl->Semantic.Name == TGSI_SEMANTIC_PCOORD) {
343 if (c->cap_point_is_sysval) {
344 var->data.mode = nir_var_system_value;
345 var->data.location = SYSTEM_VALUE_POINT_COORD;
346 } else {
347 var->data.location = VARYING_SLOT_PNTC;
348 }
349 c->input_var_point = var;
350 } else {
351 var->data.location =
352 tgsi_varying_semantic_to_slot(decl->Semantic.Name,
353 decl->Semantic.Index);
354 }
355 } else {
356 assert(!decl->Declaration.Semantic);
357 var->data.location = VERT_ATTRIB_GENERIC0 + idx;
358 }
359 var->data.index = 0;
360 var->data.interpolation =
361 ttn_translate_interp_mode(decl->Interp.Interpolate);
362
363 c->inputs[idx] = var;
364
365 for (int i = 0; i < array_size; i++)
366 b->shader->info.inputs_read |= 1ull << (var->data.location + i);
367
368 break;
369 case TGSI_FILE_OUTPUT: {
370 int semantic_name = decl->Semantic.Name;
371 int semantic_index = decl->Semantic.Index;
372 /* Since we can't load from outputs in the IR, we make temporaries
373 * for the outputs and emit stores to the real outputs at the end of
374 * the shader.
375 */
376 nir_register *reg = nir_local_reg_create(b->impl);
377 reg->num_components = 4;
378 if (is_array)
379 reg->num_array_elems = array_size;
380
381 var->data.mode = nir_var_shader_out;
382 var->name = ralloc_asprintf(var, "out_%d", idx);
383 var->data.index = 0;
384 var->data.interpolation =
385 ttn_translate_interp_mode(decl->Interp.Interpolate);
386 var->data.patch = semantic_name == TGSI_SEMANTIC_TESSINNER ||
387 semantic_name == TGSI_SEMANTIC_TESSOUTER ||
388 semantic_name == TGSI_SEMANTIC_PATCH;
389
390 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
391 switch (semantic_name) {
392 case TGSI_SEMANTIC_COLOR: {
393 /* TODO tgsi loses some information, so we cannot
394 * actually differentiate here between DSB and MRT
395 * at this point. But so far no drivers using tgsi-
396 * to-nir support dual source blend:
397 */
398 bool dual_src_blend = false;
399 if (dual_src_blend && (semantic_index == 1)) {
400 var->data.location = FRAG_RESULT_DATA0;
401 var->data.index = 1;
402 } else {
403 if (c->scan->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
404 var->data.location = FRAG_RESULT_COLOR;
405 else
406 var->data.location = FRAG_RESULT_DATA0 + semantic_index;
407 }
408 break;
409 }
410 case TGSI_SEMANTIC_POSITION:
411 var->data.location = FRAG_RESULT_DEPTH;
412 var->type = glsl_float_type();
413 break;
414 case TGSI_SEMANTIC_STENCIL:
415 var->data.location = FRAG_RESULT_STENCIL;
416 var->type = glsl_int_type();
417 break;
418 case TGSI_SEMANTIC_SAMPLEMASK:
419 var->data.location = FRAG_RESULT_SAMPLE_MASK;
420 var->type = glsl_int_type();
421 break;
422
423 default:
424 fprintf(stderr, "Bad TGSI semantic: %d/%d\n",
425 decl->Semantic.Name, decl->Semantic.Index);
426 abort();
427 }
428 } else {
429 var->data.location =
430 tgsi_varying_semantic_to_slot(semantic_name, semantic_index);
431 if (var->data.location == VARYING_SLOT_FOGC ||
432 var->data.location == VARYING_SLOT_PSIZ) {
433 var->type = glsl_float_type();
434 } else if (var->data.location == VARYING_SLOT_LAYER) {
435 var->type = glsl_int_type();
436 }
437 }
438
439 if (is_array) {
440 unsigned j;
441 for (j = 0; j < array_size; j++) {
442 c->output_regs[idx + j].offset = i + j;
443 c->output_regs[idx + j].reg = reg;
444 }
445 } else {
446 c->output_regs[idx].offset = i;
447 c->output_regs[idx].reg = reg;
448 }
449
450 c->outputs[idx] = var;
451
452 for (int i = 0; i < array_size; i++)
453 b->shader->info.outputs_written |= 1ull << (var->data.location + i);
454 }
455 break;
456 case TGSI_FILE_CONSTANT:
457 var->data.mode = nir_var_uniform;
458 var->name = ralloc_asprintf(var, "uniform_%d", idx);
459 var->data.location = idx;
460 break;
461 default:
462 unreachable("bad declaration file");
463 return;
464 }
465
466 nir_shader_add_variable(b->shader, var);
467
468 if (is_array)
469 break;
470 }
471
472 }
473 }
474
475 static void
ttn_emit_immediate(struct ttn_compile * c)476 ttn_emit_immediate(struct ttn_compile *c)
477 {
478 nir_builder *b = &c->build;
479 struct tgsi_full_immediate *tgsi_imm = &c->token->FullImmediate;
480 nir_load_const_instr *load_const;
481 int i;
482
483 load_const = nir_load_const_instr_create(b->shader, 4, 32);
484 c->imm_defs[c->next_imm] = &load_const->def;
485 c->next_imm++;
486
487 for (i = 0; i < load_const->def.num_components; i++)
488 load_const->value[i].u32 = tgsi_imm->u[i].Uint;
489
490 nir_builder_instr_insert(b, &load_const->instr);
491 }
492
493 static nir_ssa_def *
494 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect);
495
496 /* generate either a constant or indirect deref chain for accessing an
497 * array variable.
498 */
499 static nir_deref_instr *
ttn_array_deref(struct ttn_compile * c,nir_variable * var,unsigned offset,struct tgsi_ind_register * indirect)500 ttn_array_deref(struct ttn_compile *c, nir_variable *var, unsigned offset,
501 struct tgsi_ind_register *indirect)
502 {
503 nir_deref_instr *deref = nir_build_deref_var(&c->build, var);
504 nir_ssa_def *index = nir_imm_int(&c->build, offset);
505 if (indirect)
506 index = nir_iadd(&c->build, index, ttn_src_for_indirect(c, indirect));
507 return nir_build_deref_array(&c->build, deref, index);
508 }
509
510 /* Special case: Turn the frontface varying into a load of the
511 * frontface variable, and create the vector as required by TGSI.
512 */
513 static nir_ssa_def *
ttn_emulate_tgsi_front_face(struct ttn_compile * c)514 ttn_emulate_tgsi_front_face(struct ttn_compile *c)
515 {
516 nir_ssa_def *tgsi_frontface[4];
517
518 if (c->cap_face_is_sysval) {
519 /* When it's a system value, it should be an integer vector: (F, 0, 0, 1)
520 * F is 0xffffffff if front-facing, 0 if not.
521 */
522
523 nir_ssa_def *frontface = nir_load_front_face(&c->build, 1);
524
525 tgsi_frontface[0] = nir_bcsel(&c->build,
526 frontface,
527 nir_imm_int(&c->build, 0xffffffff),
528 nir_imm_int(&c->build, 0));
529 tgsi_frontface[1] = nir_imm_int(&c->build, 0);
530 tgsi_frontface[2] = nir_imm_int(&c->build, 0);
531 tgsi_frontface[3] = nir_imm_int(&c->build, 1);
532 } else {
533 /* When it's an input, it should be a float vector: (F, 0.0, 0.0, 1.0)
534 * F is positive if front-facing, negative if not.
535 */
536
537 assert(c->input_var_face);
538 nir_ssa_def *frontface = nir_load_var(&c->build, c->input_var_face);
539
540 tgsi_frontface[0] = nir_bcsel(&c->build,
541 frontface,
542 nir_imm_float(&c->build, 1.0),
543 nir_imm_float(&c->build, -1.0));
544 tgsi_frontface[1] = nir_imm_float(&c->build, 0.0);
545 tgsi_frontface[2] = nir_imm_float(&c->build, 0.0);
546 tgsi_frontface[3] = nir_imm_float(&c->build, 1.0);
547 }
548
549 return nir_vec(&c->build, tgsi_frontface, 4);
550 }
551
552 static nir_src
ttn_src_for_file_and_index(struct ttn_compile * c,unsigned file,unsigned index,struct tgsi_ind_register * indirect,struct tgsi_dimension * dim,struct tgsi_ind_register * dimind,bool src_is_float)553 ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index,
554 struct tgsi_ind_register *indirect,
555 struct tgsi_dimension *dim,
556 struct tgsi_ind_register *dimind,
557 bool src_is_float)
558 {
559 nir_builder *b = &c->build;
560 nir_src src;
561
562 memset(&src, 0, sizeof(src));
563
564 switch (file) {
565 case TGSI_FILE_TEMPORARY:
566 if (c->temp_regs[index].var) {
567 unsigned offset = c->temp_regs[index].offset;
568 nir_variable *var = c->temp_regs[index].var;
569 nir_ssa_def *load = nir_load_deref(&c->build,
570 ttn_array_deref(c, var, offset, indirect));
571
572 src = nir_src_for_ssa(load);
573 } else {
574 assert(!indirect);
575 src.reg.reg = c->temp_regs[index].reg;
576 }
577 assert(!dim);
578 break;
579
580 case TGSI_FILE_ADDRESS:
581 src.reg.reg = c->addr_reg;
582 assert(!dim);
583 break;
584
585 case TGSI_FILE_IMMEDIATE:
586 src = nir_src_for_ssa(c->imm_defs[index]);
587 assert(!indirect);
588 assert(!dim);
589 break;
590
591 case TGSI_FILE_SYSTEM_VALUE: {
592 nir_ssa_def *load;
593
594 assert(!indirect);
595 assert(!dim);
596
597 switch (c->scan->system_value_semantic_name[index]) {
598 case TGSI_SEMANTIC_VERTEXID_NOBASE:
599 load = nir_load_vertex_id_zero_base(b);
600 break;
601 case TGSI_SEMANTIC_VERTEXID:
602 load = nir_load_vertex_id(b);
603 break;
604 case TGSI_SEMANTIC_BASEVERTEX:
605 load = nir_load_base_vertex(b);
606 break;
607 case TGSI_SEMANTIC_INSTANCEID:
608 load = nir_load_instance_id(b);
609 break;
610 case TGSI_SEMANTIC_FACE:
611 assert(c->cap_face_is_sysval);
612 load = ttn_emulate_tgsi_front_face(c);
613 break;
614 case TGSI_SEMANTIC_POSITION:
615 assert(c->cap_position_is_sysval);
616 load = nir_load_frag_coord(b);
617 break;
618 case TGSI_SEMANTIC_PCOORD:
619 assert(c->cap_point_is_sysval);
620 load = nir_load_point_coord(b);
621 break;
622 case TGSI_SEMANTIC_THREAD_ID:
623 load = nir_load_local_invocation_id(b);
624 break;
625 case TGSI_SEMANTIC_BLOCK_ID:
626 load = nir_load_workgroup_id(b, 32);
627 break;
628 case TGSI_SEMANTIC_BLOCK_SIZE:
629 load = nir_load_workgroup_size(b);
630 break;
631 case TGSI_SEMANTIC_CS_USER_DATA_AMD:
632 load = nir_load_user_data_amd(b);
633 break;
634 case TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL:
635 load = nir_load_tess_level_inner_default(b);
636 break;
637 case TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL:
638 load = nir_load_tess_level_outer_default(b);
639 break;
640 case TGSI_SEMANTIC_SAMPLEID:
641 load = nir_load_sample_id(b);
642 break;
643 default:
644 unreachable("bad system value");
645 }
646
647 if (load->num_components == 2)
648 load = nir_swizzle(b, load, SWIZ(X, Y, Y, Y), 4);
649 else if (load->num_components == 3)
650 load = nir_swizzle(b, load, SWIZ(X, Y, Z, Z), 4);
651
652 src = nir_src_for_ssa(load);
653 break;
654 }
655
656 case TGSI_FILE_INPUT:
657 if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
658 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_FACE) {
659 assert(!c->cap_face_is_sysval && c->input_var_face);
660 return nir_src_for_ssa(ttn_emulate_tgsi_front_face(c));
661 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
662 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_POSITION) {
663 assert(!c->cap_position_is_sysval && c->input_var_position);
664 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_position));
665 } else if (c->scan->processor == PIPE_SHADER_FRAGMENT &&
666 c->scan->input_semantic_name[index] == TGSI_SEMANTIC_PCOORD) {
667 assert(!c->cap_point_is_sysval && c->input_var_point);
668 return nir_src_for_ssa(nir_load_var(&c->build, c->input_var_point));
669 } else {
670 /* Indirection on input arrays isn't supported by TTN. */
671 assert(!dim);
672 nir_deref_instr *deref = nir_build_deref_var(&c->build,
673 c->inputs[index]);
674 return nir_src_for_ssa(nir_load_deref(&c->build, deref));
675 }
676 break;
677
678 case TGSI_FILE_OUTPUT:
679 if (c->scan->processor == PIPE_SHADER_FRAGMENT) {
680 c->outputs[index]->data.fb_fetch_output = 1;
681 nir_deref_instr *deref = nir_build_deref_var(&c->build,
682 c->outputs[index]);
683 return nir_src_for_ssa(nir_load_deref(&c->build, deref));
684 }
685 unreachable("unsupported output read");
686 break;
687
688 case TGSI_FILE_CONSTANT: {
689 nir_intrinsic_instr *load;
690 nir_intrinsic_op op;
691 unsigned srcn = 0;
692
693 if (dim && (dim->Index > 0 || dim->Indirect)) {
694 op = nir_intrinsic_load_ubo;
695 } else {
696 op = nir_intrinsic_load_uniform;
697 }
698
699 load = nir_intrinsic_instr_create(b->shader, op);
700 if (op == nir_intrinsic_load_uniform) {
701 nir_intrinsic_set_dest_type(load, src_is_float ? nir_type_float :
702 nir_type_int);
703 }
704
705 load->num_components = 4;
706 if (dim && (dim->Index > 0 || dim->Indirect)) {
707 if (dimind) {
708 load->src[srcn] =
709 ttn_src_for_file_and_index(c, dimind->File, dimind->Index,
710 NULL, NULL, NULL, false);
711 } else {
712 /* UBOs start at index 1 in TGSI: */
713 load->src[srcn] =
714 nir_src_for_ssa(nir_imm_int(b, dim->Index - 1));
715 }
716 srcn++;
717 }
718
719 nir_ssa_def *offset;
720 if (op == nir_intrinsic_load_ubo) {
721 /* UBO loads don't have a base offset. */
722 offset = nir_imm_int(b, index);
723 if (indirect) {
724 offset = nir_iadd(b, offset, ttn_src_for_indirect(c, indirect));
725 }
726 /* UBO offsets are in bytes, but TGSI gives them to us in vec4's */
727 offset = nir_ishl(b, offset, nir_imm_int(b, 4));
728 nir_intrinsic_set_align(load, 16, 0);
729
730 /* Set a very conservative base/range of the access: 16 bytes if not
731 * indirect at all, offset to the end of the UBO if the offset is
732 * indirect, and totally unknown if the block number is indirect.
733 */
734 uint32_t base = index * 16;
735 nir_intrinsic_set_range_base(load, base);
736 if (dimind)
737 nir_intrinsic_set_range(load, ~0);
738 else if (indirect)
739 nir_intrinsic_set_range(load, c->ubo_sizes[dim->Index] - base);
740 else
741 nir_intrinsic_set_range(load, base + 16);
742 } else {
743 nir_intrinsic_set_base(load, index);
744 if (indirect) {
745 offset = ttn_src_for_indirect(c, indirect);
746 nir_intrinsic_set_range(load, c->build.shader->num_uniforms * 16 - index);
747 } else {
748 offset = nir_imm_int(b, 0);
749 nir_intrinsic_set_range(load, 1);
750 }
751 }
752 load->src[srcn++] = nir_src_for_ssa(offset);
753
754 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
755 nir_builder_instr_insert(b, &load->instr);
756
757 src = nir_src_for_ssa(&load->dest.ssa);
758 break;
759 }
760
761 default:
762 unreachable("bad src file");
763 }
764
765
766 return src;
767 }
768
769 static nir_ssa_def *
ttn_src_for_indirect(struct ttn_compile * c,struct tgsi_ind_register * indirect)770 ttn_src_for_indirect(struct ttn_compile *c, struct tgsi_ind_register *indirect)
771 {
772 nir_builder *b = &c->build;
773 nir_alu_src src;
774 memset(&src, 0, sizeof(src));
775 for (int i = 0; i < 4; i++)
776 src.swizzle[i] = indirect->Swizzle;
777 src.src = ttn_src_for_file_and_index(c,
778 indirect->File,
779 indirect->Index,
780 NULL, NULL, NULL,
781 false);
782 return nir_mov_alu(b, src, 1);
783 }
784
785 static nir_alu_dest
ttn_get_dest(struct ttn_compile * c,struct tgsi_full_dst_register * tgsi_fdst)786 ttn_get_dest(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
787 {
788 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
789 nir_alu_dest dest;
790 unsigned index = tgsi_dst->Index;
791
792 memset(&dest, 0, sizeof(dest));
793
794 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
795 if (c->temp_regs[index].var) {
796 nir_register *reg;
797
798 /* this works, because TGSI will give us a base offset
799 * (in case of indirect index) that points back into
800 * the array. Access can be direct or indirect, we
801 * don't really care. Just create a one-shot dst reg
802 * that will get store_var'd back into the array var
803 * at the end of ttn_emit_instruction()
804 */
805 reg = nir_local_reg_create(c->build.impl);
806 reg->num_components = 4;
807 dest.dest.reg.reg = reg;
808 dest.dest.reg.base_offset = 0;
809 } else {
810 assert(!tgsi_dst->Indirect);
811 dest.dest.reg.reg = c->temp_regs[index].reg;
812 dest.dest.reg.base_offset = c->temp_regs[index].offset;
813 }
814 } else if (tgsi_dst->File == TGSI_FILE_OUTPUT) {
815 dest.dest.reg.reg = c->output_regs[index].reg;
816 dest.dest.reg.base_offset = c->output_regs[index].offset;
817 } else if (tgsi_dst->File == TGSI_FILE_ADDRESS) {
818 assert(index == 0);
819 dest.dest.reg.reg = c->addr_reg;
820 }
821
822 dest.write_mask = tgsi_dst->WriteMask;
823 dest.saturate = false;
824
825 if (tgsi_dst->Indirect && (tgsi_dst->File != TGSI_FILE_TEMPORARY)) {
826 nir_src *indirect = malloc(sizeof(nir_src));
827 *indirect = nir_src_for_ssa(ttn_src_for_indirect(c, &tgsi_fdst->Indirect));
828 dest.dest.reg.indirect = indirect;
829 }
830
831 return dest;
832 }
833
834 static nir_variable *
ttn_get_var(struct ttn_compile * c,struct tgsi_full_dst_register * tgsi_fdst)835 ttn_get_var(struct ttn_compile *c, struct tgsi_full_dst_register *tgsi_fdst)
836 {
837 struct tgsi_dst_register *tgsi_dst = &tgsi_fdst->Register;
838 unsigned index = tgsi_dst->Index;
839
840 if (tgsi_dst->File == TGSI_FILE_TEMPORARY) {
841 /* we should not have an indirect when there is no var! */
842 if (!c->temp_regs[index].var)
843 assert(!tgsi_dst->Indirect);
844 return c->temp_regs[index].var;
845 }
846
847 return NULL;
848 }
849
850 static nir_ssa_def *
ttn_get_src(struct ttn_compile * c,struct tgsi_full_src_register * tgsi_fsrc,int src_idx)851 ttn_get_src(struct ttn_compile *c, struct tgsi_full_src_register *tgsi_fsrc,
852 int src_idx)
853 {
854 nir_builder *b = &c->build;
855 struct tgsi_src_register *tgsi_src = &tgsi_fsrc->Register;
856 enum tgsi_opcode opcode = c->token->FullInstruction.Instruction.Opcode;
857 unsigned tgsi_src_type = tgsi_opcode_infer_src_type(opcode, src_idx);
858 bool src_is_float = (tgsi_src_type == TGSI_TYPE_FLOAT ||
859 tgsi_src_type == TGSI_TYPE_DOUBLE ||
860 tgsi_src_type == TGSI_TYPE_UNTYPED);
861 nir_alu_src src;
862
863 memset(&src, 0, sizeof(src));
864
865 if (tgsi_src->File == TGSI_FILE_NULL) {
866 return nir_imm_float(b, 0.0);
867 } else if (tgsi_src->File == TGSI_FILE_SAMPLER ||
868 tgsi_src->File == TGSI_FILE_IMAGE ||
869 tgsi_src->File == TGSI_FILE_BUFFER) {
870 /* Only the index of the resource gets used in texturing, and it will
871 * handle looking that up on its own instead of using the nir_alu_src.
872 */
873 assert(!tgsi_src->Indirect);
874 return NULL;
875 } else {
876 struct tgsi_ind_register *ind = NULL;
877 struct tgsi_dimension *dim = NULL;
878 struct tgsi_ind_register *dimind = NULL;
879 if (tgsi_src->Indirect)
880 ind = &tgsi_fsrc->Indirect;
881 if (tgsi_src->Dimension) {
882 dim = &tgsi_fsrc->Dimension;
883 if (dim->Indirect)
884 dimind = &tgsi_fsrc->DimIndirect;
885 }
886 src.src = ttn_src_for_file_and_index(c,
887 tgsi_src->File,
888 tgsi_src->Index,
889 ind, dim, dimind,
890 src_is_float);
891 }
892
893 src.swizzle[0] = tgsi_src->SwizzleX;
894 src.swizzle[1] = tgsi_src->SwizzleY;
895 src.swizzle[2] = tgsi_src->SwizzleZ;
896 src.swizzle[3] = tgsi_src->SwizzleW;
897
898 nir_ssa_def *def = nir_mov_alu(b, src, 4);
899
900 if (tgsi_type_is_64bit(tgsi_src_type))
901 def = nir_bitcast_vector(b, def, 64);
902
903 if (tgsi_src->Absolute) {
904 assert(src_is_float);
905 def = nir_fabs(b, def);
906 }
907
908 if (tgsi_src->Negate) {
909 if (src_is_float)
910 def = nir_fneg(b, def);
911 else
912 def = nir_ineg(b, def);
913 }
914
915 return def;
916 }
917
918 static void
ttn_move_dest_masked(nir_builder * b,nir_alu_dest dest,nir_ssa_def * def,unsigned write_mask)919 ttn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
920 nir_ssa_def *def, unsigned write_mask)
921 {
922 if (!(dest.write_mask & write_mask))
923 return;
924
925 nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
926 mov->dest = dest;
927 mov->dest.write_mask &= write_mask;
928 mov->src[0].src = nir_src_for_ssa(def);
929 for (unsigned i = def->num_components; i < 4; i++)
930 mov->src[0].swizzle[i] = def->num_components - 1;
931 nir_builder_instr_insert(b, &mov->instr);
932 }
933
934 static void
ttn_move_dest(nir_builder * b,nir_alu_dest dest,nir_ssa_def * def)935 ttn_move_dest(nir_builder *b, nir_alu_dest dest, nir_ssa_def *def)
936 {
937 ttn_move_dest_masked(b, dest, def, TGSI_WRITEMASK_XYZW);
938 }
939
940 static void
ttn_alu(nir_builder * b,nir_op op,nir_alu_dest dest,unsigned dest_bitsize,nir_ssa_def ** src)941 ttn_alu(nir_builder *b, nir_op op, nir_alu_dest dest, unsigned dest_bitsize,
942 nir_ssa_def **src)
943 {
944 nir_ssa_def *def = nir_build_alu_src_arr(b, op, src);
945 if (def->bit_size == 1)
946 def = nir_ineg(b, nir_b2i(b, def, dest_bitsize));
947 assert(def->bit_size == dest_bitsize);
948 if (dest_bitsize == 64) {
949 if (def->num_components > 2) {
950 /* 32 -> 64 bit conversion ops are supposed to only convert the first
951 * two components, and we need to truncate here to avoid creating a
952 * vec8 after bitcasting the destination.
953 */
954 def = nir_channels(b, def, 0x3);
955 }
956 def = nir_bitcast_vector(b, def, 32);
957 }
958 ttn_move_dest(b, dest, def);
959 }
960
961 static void
ttn_arl(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)962 ttn_arl(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
963 {
964 ttn_move_dest(b, dest, nir_f2i32(b, nir_ffloor(b, src[0])));
965 }
966
967 /* EXP - Approximate Exponential Base 2
968 * dst.x = 2^{\lfloor src.x\rfloor}
969 * dst.y = src.x - \lfloor src.x\rfloor
970 * dst.z = 2^{src.x}
971 * dst.w = 1.0
972 */
973 static void
ttn_exp(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)974 ttn_exp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
975 {
976 nir_ssa_def *srcx = ttn_channel(b, src[0], X);
977
978 ttn_move_dest_masked(b, dest, nir_fexp2(b, nir_ffloor(b, srcx)),
979 TGSI_WRITEMASK_X);
980 ttn_move_dest_masked(b, dest, nir_fsub(b, srcx, nir_ffloor(b, srcx)),
981 TGSI_WRITEMASK_Y);
982 ttn_move_dest_masked(b, dest, nir_fexp2(b, srcx), TGSI_WRITEMASK_Z);
983 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
984 }
985
986 /* LOG - Approximate Logarithm Base 2
987 * dst.x = \lfloor\log_2{|src.x|}\rfloor
988 * dst.y = \frac{|src.x|}{2^{\lfloor\log_2{|src.x|}\rfloor}}
989 * dst.z = \log_2{|src.x|}
990 * dst.w = 1.0
991 */
992 static void
ttn_log(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)993 ttn_log(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
994 {
995 nir_ssa_def *abs_srcx = nir_fabs(b, ttn_channel(b, src[0], X));
996 nir_ssa_def *log2 = nir_flog2(b, abs_srcx);
997
998 ttn_move_dest_masked(b, dest, nir_ffloor(b, log2), TGSI_WRITEMASK_X);
999 ttn_move_dest_masked(b, dest,
1000 nir_fdiv(b, abs_srcx, nir_fexp2(b, nir_ffloor(b, log2))),
1001 TGSI_WRITEMASK_Y);
1002 ttn_move_dest_masked(b, dest, nir_flog2(b, abs_srcx), TGSI_WRITEMASK_Z);
1003 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_W);
1004 }
1005
1006 /* DST - Distance Vector
1007 * dst.x = 1.0
1008 * dst.y = src0.y \times src1.y
1009 * dst.z = src0.z
1010 * dst.w = src1.w
1011 */
1012 static void
ttn_dst(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1013 ttn_dst(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1014 {
1015 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_X);
1016 ttn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), TGSI_WRITEMASK_Y);
1017 ttn_move_dest_masked(b, dest, nir_mov(b, src[0]), TGSI_WRITEMASK_Z);
1018 ttn_move_dest_masked(b, dest, nir_mov(b, src[1]), TGSI_WRITEMASK_W);
1019 }
1020
1021 /* LIT - Light Coefficients
1022 * dst.x = 1.0
1023 * dst.y = max(src.x, 0.0)
1024 * dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0
1025 * dst.w = 1.0
1026 */
1027 static void
ttn_lit(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1028 ttn_lit(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1029 {
1030 ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_XW);
1031
1032 ttn_move_dest_masked(b, dest, nir_fmax(b, ttn_channel(b, src[0], X),
1033 nir_imm_float(b, 0.0)), TGSI_WRITEMASK_Y);
1034
1035 if (dest.write_mask & TGSI_WRITEMASK_Z) {
1036 nir_ssa_def *src0_y = ttn_channel(b, src[0], Y);
1037 nir_ssa_def *wclamp = nir_fmax(b, nir_fmin(b, ttn_channel(b, src[0], W),
1038 nir_imm_float(b, 128.0)),
1039 nir_imm_float(b, -128.0));
1040 nir_ssa_def *pow = nir_fpow(b, nir_fmax(b, src0_y, nir_imm_float(b, 0.0)),
1041 wclamp);
1042
1043 ttn_move_dest_masked(b, dest,
1044 nir_bcsel(b,
1045 nir_flt(b,
1046 ttn_channel(b, src[0], X),
1047 nir_imm_float(b, 0.0)),
1048 nir_imm_float(b, 0.0),
1049 pow),
1050 TGSI_WRITEMASK_Z);
1051 }
1052 }
1053
1054 static void
ttn_sle(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1055 ttn_sle(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1056 {
1057 ttn_move_dest(b, dest, nir_sge(b, src[1], src[0]));
1058 }
1059
1060 static void
ttn_sgt(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1061 ttn_sgt(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1062 {
1063 ttn_move_dest(b, dest, nir_slt(b, src[1], src[0]));
1064 }
1065
1066 static void
ttn_dp2(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1067 ttn_dp2(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1068 {
1069 ttn_move_dest(b, dest, nir_fdot2(b, src[0], src[1]));
1070 }
1071
1072 static void
ttn_dp3(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1073 ttn_dp3(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1074 {
1075 ttn_move_dest(b, dest, nir_fdot3(b, src[0], src[1]));
1076 }
1077
1078 static void
ttn_dp4(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1079 ttn_dp4(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1080 {
1081 ttn_move_dest(b, dest, nir_fdot4(b, src[0], src[1]));
1082 }
1083
1084 static void
ttn_umad(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1085 ttn_umad(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1086 {
1087 ttn_move_dest(b, dest, nir_iadd(b, nir_imul(b, src[0], src[1]), src[2]));
1088 }
1089
1090 static void
ttn_arr(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1091 ttn_arr(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1092 {
1093 ttn_move_dest(b, dest, nir_f2i32(b, nir_fround_even(b, src[0])));
1094 }
1095
1096 static void
ttn_cmp(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1097 ttn_cmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1098 {
1099 ttn_move_dest(b, dest, nir_bcsel(b,
1100 nir_flt(b, src[0], nir_imm_float(b, 0.0)),
1101 src[1], src[2]));
1102 }
1103
1104 static void
ttn_ucmp(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1105 ttn_ucmp(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1106 {
1107 ttn_move_dest(b, dest, nir_bcsel(b,
1108 nir_ine(b, src[0], nir_imm_int(b, 0)),
1109 src[1], src[2]));
1110 }
1111
1112 static void
ttn_barrier(nir_builder * b)1113 ttn_barrier(nir_builder *b)
1114 {
1115 nir_control_barrier(b);
1116 }
1117
1118 static void
ttn_kill(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1119 ttn_kill(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1120 {
1121 nir_discard(b);
1122 b->shader->info.fs.uses_discard = true;
1123 }
1124
1125 static void
ttn_kill_if(nir_builder * b,nir_op op,nir_alu_dest dest,nir_ssa_def ** src)1126 ttn_kill_if(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
1127 {
1128 /* flt must be exact, because NaN shouldn't discard. (apps rely on this) */
1129 b->exact = true;
1130 nir_ssa_def *cmp = nir_bany(b, nir_flt(b, src[0], nir_imm_float(b, 0.0)));
1131 b->exact = false;
1132
1133 nir_discard_if(b, cmp);
1134 b->shader->info.fs.uses_discard = true;
1135 }
1136
1137 static void
get_texture_info(unsigned texture,enum glsl_sampler_dim * dim,bool * is_shadow,bool * is_array)1138 get_texture_info(unsigned texture,
1139 enum glsl_sampler_dim *dim,
1140 bool *is_shadow,
1141 bool *is_array)
1142 {
1143 assert(is_array);
1144 *is_array = false;
1145
1146 if (is_shadow)
1147 *is_shadow = false;
1148
1149 switch (texture) {
1150 case TGSI_TEXTURE_BUFFER:
1151 *dim = GLSL_SAMPLER_DIM_BUF;
1152 break;
1153 case TGSI_TEXTURE_1D:
1154 *dim = GLSL_SAMPLER_DIM_1D;
1155 break;
1156 case TGSI_TEXTURE_1D_ARRAY:
1157 *dim = GLSL_SAMPLER_DIM_1D;
1158 *is_array = true;
1159 break;
1160 case TGSI_TEXTURE_SHADOW1D:
1161 *dim = GLSL_SAMPLER_DIM_1D;
1162 *is_shadow = true;
1163 break;
1164 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1165 *dim = GLSL_SAMPLER_DIM_1D;
1166 *is_shadow = true;
1167 *is_array = true;
1168 break;
1169 case TGSI_TEXTURE_2D:
1170 *dim = GLSL_SAMPLER_DIM_2D;
1171 break;
1172 case TGSI_TEXTURE_2D_ARRAY:
1173 *dim = GLSL_SAMPLER_DIM_2D;
1174 *is_array = true;
1175 break;
1176 case TGSI_TEXTURE_2D_MSAA:
1177 *dim = GLSL_SAMPLER_DIM_MS;
1178 break;
1179 case TGSI_TEXTURE_2D_ARRAY_MSAA:
1180 *dim = GLSL_SAMPLER_DIM_MS;
1181 *is_array = true;
1182 break;
1183 case TGSI_TEXTURE_SHADOW2D:
1184 *dim = GLSL_SAMPLER_DIM_2D;
1185 *is_shadow = true;
1186 break;
1187 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1188 *dim = GLSL_SAMPLER_DIM_2D;
1189 *is_shadow = true;
1190 *is_array = true;
1191 break;
1192 case TGSI_TEXTURE_3D:
1193 *dim = GLSL_SAMPLER_DIM_3D;
1194 break;
1195 case TGSI_TEXTURE_CUBE:
1196 *dim = GLSL_SAMPLER_DIM_CUBE;
1197 break;
1198 case TGSI_TEXTURE_CUBE_ARRAY:
1199 *dim = GLSL_SAMPLER_DIM_CUBE;
1200 *is_array = true;
1201 break;
1202 case TGSI_TEXTURE_SHADOWCUBE:
1203 *dim = GLSL_SAMPLER_DIM_CUBE;
1204 *is_shadow = true;
1205 break;
1206 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1207 *dim = GLSL_SAMPLER_DIM_CUBE;
1208 *is_shadow = true;
1209 *is_array = true;
1210 break;
1211 case TGSI_TEXTURE_RECT:
1212 *dim = GLSL_SAMPLER_DIM_RECT;
1213 break;
1214 case TGSI_TEXTURE_SHADOWRECT:
1215 *dim = GLSL_SAMPLER_DIM_RECT;
1216 *is_shadow = true;
1217 break;
1218 default:
1219 fprintf(stderr, "Unknown TGSI texture target %d\n", texture);
1220 abort();
1221 }
1222 }
1223
1224 static enum glsl_base_type
base_type_for_alu_type(nir_alu_type type)1225 base_type_for_alu_type(nir_alu_type type)
1226 {
1227 type = nir_alu_type_get_base_type(type);
1228
1229 switch (type) {
1230 case nir_type_float:
1231 return GLSL_TYPE_FLOAT;
1232 case nir_type_int:
1233 return GLSL_TYPE_INT;
1234 case nir_type_uint:
1235 return GLSL_TYPE_UINT;
1236 default:
1237 unreachable("invalid type");
1238 }
1239 }
1240
1241 static nir_variable *
get_sampler_var(struct ttn_compile * c,int binding,enum glsl_sampler_dim dim,bool is_shadow,bool is_array,enum glsl_base_type base_type,nir_texop op)1242 get_sampler_var(struct ttn_compile *c, int binding,
1243 enum glsl_sampler_dim dim,
1244 bool is_shadow,
1245 bool is_array,
1246 enum glsl_base_type base_type,
1247 nir_texop op)
1248 {
1249 nir_variable *var = c->samplers[binding];
1250 if (!var) {
1251 const struct glsl_type *type =
1252 glsl_sampler_type(dim, is_shadow, is_array, base_type);
1253 var = nir_variable_create(c->build.shader, nir_var_uniform, type,
1254 "sampler");
1255 var->data.binding = binding;
1256 var->data.explicit_binding = true;
1257
1258 c->samplers[binding] = var;
1259 c->num_samplers = MAX2(c->num_samplers, binding + 1);
1260
1261 /* Record textures used */
1262 BITSET_SET(c->build.shader->info.textures_used, binding);
1263 if (op == nir_texop_txf || op == nir_texop_txf_ms)
1264 BITSET_SET(c->build.shader->info.textures_used_by_txf, binding);
1265 }
1266
1267 return var;
1268 }
1269
1270 static nir_variable *
get_image_var(struct ttn_compile * c,int binding,enum glsl_sampler_dim dim,bool is_array,enum glsl_base_type base_type,enum gl_access_qualifier access,enum pipe_format format)1271 get_image_var(struct ttn_compile *c, int binding,
1272 enum glsl_sampler_dim dim,
1273 bool is_array,
1274 enum glsl_base_type base_type,
1275 enum gl_access_qualifier access,
1276 enum pipe_format format)
1277 {
1278 nir_variable *var = c->images[binding];
1279
1280 if (!var) {
1281 const struct glsl_type *type = glsl_image_type(dim, is_array, base_type);
1282
1283 var = nir_variable_create(c->build.shader, nir_var_uniform, type, "image");
1284 var->data.binding = binding;
1285 var->data.explicit_binding = true;
1286 var->data.access = access;
1287 var->data.image.format = format;
1288
1289 c->images[binding] = var;
1290 c->num_images = MAX2(c->num_images, binding + 1);
1291 if (dim == GLSL_SAMPLER_DIM_MS)
1292 c->num_msaa_images = c->num_images;
1293 }
1294
1295 return var;
1296 }
1297
1298 static void
add_ssbo_var(struct ttn_compile * c,int binding)1299 add_ssbo_var(struct ttn_compile *c, int binding)
1300 {
1301 nir_variable *var = c->ssbo[binding];
1302
1303 if (!var) {
1304 /* A length of 0 is used to denote unsized arrays */
1305 const struct glsl_type *type = glsl_array_type(glsl_uint_type(), 0, 0);
1306
1307 struct glsl_struct_field field = {
1308 .type = type,
1309 .name = "data",
1310 .location = -1,
1311 };
1312
1313 var = nir_variable_create(c->build.shader, nir_var_mem_ssbo, type, "ssbo");
1314 var->data.binding = binding;
1315 var->interface_type =
1316 glsl_interface_type(&field, 1, GLSL_INTERFACE_PACKING_STD430,
1317 false, "data");
1318 c->ssbo[binding] = var;
1319 }
1320 }
1321
1322 static void
ttn_tex(struct ttn_compile * c,nir_alu_dest dest,nir_ssa_def ** src)1323 ttn_tex(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1324 {
1325 nir_builder *b = &c->build;
1326 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1327 nir_tex_instr *instr;
1328 nir_texop op;
1329 unsigned num_srcs, samp = 1, sview, i;
1330
1331 switch (tgsi_inst->Instruction.Opcode) {
1332 case TGSI_OPCODE_TEX:
1333 op = nir_texop_tex;
1334 num_srcs = 1;
1335 break;
1336 case TGSI_OPCODE_TEX2:
1337 op = nir_texop_tex;
1338 num_srcs = 1;
1339 samp = 2;
1340 break;
1341 case TGSI_OPCODE_TXP:
1342 op = nir_texop_tex;
1343 num_srcs = 2;
1344 break;
1345 case TGSI_OPCODE_TXB:
1346 op = nir_texop_txb;
1347 num_srcs = 2;
1348 break;
1349 case TGSI_OPCODE_TXB2:
1350 op = nir_texop_txb;
1351 num_srcs = 2;
1352 samp = 2;
1353 break;
1354 case TGSI_OPCODE_TXL:
1355 case TGSI_OPCODE_TEX_LZ:
1356 op = nir_texop_txl;
1357 num_srcs = 2;
1358 break;
1359 case TGSI_OPCODE_TXL2:
1360 op = nir_texop_txl;
1361 num_srcs = 2;
1362 samp = 2;
1363 break;
1364 case TGSI_OPCODE_TXF:
1365 case TGSI_OPCODE_TXF_LZ:
1366 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
1367 tgsi_inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1368 op = nir_texop_txf_ms;
1369 } else {
1370 op = nir_texop_txf;
1371 }
1372 num_srcs = 2;
1373 break;
1374 case TGSI_OPCODE_TXD:
1375 op = nir_texop_txd;
1376 num_srcs = 3;
1377 samp = 3;
1378 break;
1379 case TGSI_OPCODE_LODQ:
1380 op = nir_texop_lod;
1381 num_srcs = 1;
1382 break;
1383
1384 default:
1385 fprintf(stderr, "unknown TGSI tex op %d\n", tgsi_inst->Instruction.Opcode);
1386 abort();
1387 }
1388
1389 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
1390 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1391 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
1392 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1393 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
1394 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
1395 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1396 num_srcs++;
1397 }
1398
1399 /* Deref sources */
1400 num_srcs += 2;
1401
1402 num_srcs += tgsi_inst->Texture.NumOffsets;
1403
1404 instr = nir_tex_instr_create(b->shader, num_srcs);
1405 instr->op = op;
1406
1407 get_texture_info(tgsi_inst->Texture.Texture,
1408 &instr->sampler_dim, &instr->is_shadow, &instr->is_array);
1409
1410 instr->coord_components =
1411 glsl_get_sampler_dim_coordinate_components(instr->sampler_dim);
1412
1413 if (instr->is_array)
1414 instr->coord_components++;
1415
1416 assert(tgsi_inst->Src[samp].Register.File == TGSI_FILE_SAMPLER);
1417
1418 /* TODO if we supported any opc's which take an explicit SVIEW
1419 * src, we would use that here instead. But for the "legacy"
1420 * texture opc's the SVIEW index is same as SAMP index:
1421 */
1422 sview = tgsi_inst->Src[samp].Register.Index;
1423
1424 if (op == nir_texop_lod) {
1425 instr->dest_type = nir_type_float32;
1426 } else if (sview < c->num_samp_types) {
1427 instr->dest_type = c->samp_types[sview];
1428 } else {
1429 instr->dest_type = nir_type_float32;
1430 }
1431
1432 nir_variable *var =
1433 get_sampler_var(c, sview, instr->sampler_dim,
1434 instr->is_shadow,
1435 instr->is_array,
1436 base_type_for_alu_type(instr->dest_type),
1437 op);
1438
1439 nir_deref_instr *deref = nir_build_deref_var(b, var);
1440
1441 unsigned src_number = 0;
1442
1443 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1444 instr->src[src_number].src_type = nir_tex_src_texture_deref;
1445 src_number++;
1446 instr->src[src_number].src = nir_src_for_ssa(&deref->dest.ssa);
1447 instr->src[src_number].src_type = nir_tex_src_sampler_deref;
1448 src_number++;
1449
1450 instr->src[src_number].src =
1451 nir_src_for_ssa(nir_swizzle(b, src[0], SWIZ(X, Y, Z, W),
1452 instr->coord_components));
1453 instr->src[src_number].src_type = nir_tex_src_coord;
1454 src_number++;
1455
1456 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1457 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1458 instr->src[src_number].src_type = nir_tex_src_projector;
1459 src_number++;
1460 }
1461
1462 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB) {
1463 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1464 instr->src[src_number].src_type = nir_tex_src_bias;
1465 src_number++;
1466 }
1467
1468 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB2) {
1469 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1470 instr->src[src_number].src_type = nir_tex_src_bias;
1471 src_number++;
1472 }
1473
1474 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
1475 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ) {
1476 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TEX_LZ)
1477 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1478 else
1479 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1480 instr->src[src_number].src_type = nir_tex_src_lod;
1481 src_number++;
1482 }
1483
1484 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
1485 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1486 instr->src[src_number].src_type = nir_tex_src_lod;
1487 src_number++;
1488 }
1489
1490 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF ||
1491 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ) {
1492 if (op == nir_texop_txf_ms) {
1493 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1494 instr->src[src_number].src_type = nir_tex_src_ms_index;
1495 } else {
1496 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXF_LZ)
1497 instr->src[src_number].src = nir_src_for_ssa(nir_imm_int(b, 0));
1498 else
1499 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1500 instr->src[src_number].src_type = nir_tex_src_lod;
1501 }
1502 src_number++;
1503 }
1504
1505 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
1506 instr->src[src_number].src_type = nir_tex_src_ddx;
1507 instr->src[src_number].src =
1508 nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1509 nir_tex_instr_src_size(instr, src_number)));
1510 src_number++;
1511 instr->src[src_number].src_type = nir_tex_src_ddy;
1512 instr->src[src_number].src =
1513 nir_src_for_ssa(nir_swizzle(b, src[2], SWIZ(X, Y, Z, W),
1514 nir_tex_instr_src_size(instr, src_number)));
1515 src_number++;
1516 }
1517
1518 if (instr->is_shadow) {
1519 if (instr->coord_components == 4)
1520 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[1], X));
1521 else if (instr->coord_components == 3)
1522 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], W));
1523 else
1524 instr->src[src_number].src = nir_src_for_ssa(ttn_channel(b, src[0], Z));
1525
1526 instr->src[src_number].src_type = nir_tex_src_comparator;
1527 src_number++;
1528 }
1529
1530 for (i = 0; i < tgsi_inst->Texture.NumOffsets; i++) {
1531 struct tgsi_texture_offset *tex_offset = &tgsi_inst->TexOffsets[i];
1532 /* since TexOffset ins't using tgsi_full_src_register we get to
1533 * do some extra gymnastics:
1534 */
1535 nir_alu_src src;
1536
1537 memset(&src, 0, sizeof(src));
1538
1539 src.src = ttn_src_for_file_and_index(c,
1540 tex_offset->File,
1541 tex_offset->Index,
1542 NULL, NULL, NULL,
1543 true);
1544
1545 src.swizzle[0] = tex_offset->SwizzleX;
1546 src.swizzle[1] = tex_offset->SwizzleY;
1547 src.swizzle[2] = tex_offset->SwizzleZ;
1548 src.swizzle[3] = TGSI_SWIZZLE_W;
1549
1550 instr->src[src_number].src_type = nir_tex_src_offset;
1551 instr->src[src_number].src = nir_src_for_ssa(
1552 nir_mov_alu(b, src, nir_tex_instr_src_size(instr, src_number)));
1553 src_number++;
1554 }
1555
1556 assert(src_number == num_srcs);
1557 assert(src_number == instr->num_srcs);
1558
1559 nir_ssa_dest_init(&instr->instr, &instr->dest,
1560 nir_tex_instr_dest_size(instr),
1561 32, NULL);
1562 nir_builder_instr_insert(b, &instr->instr);
1563
1564 /* Resolve the writemask on the texture op. */
1565 ttn_move_dest(b, dest, &instr->dest.ssa);
1566 }
1567
1568 /* TGSI_OPCODE_TXQ is actually two distinct operations:
1569 *
1570 * dst.x = texture\_width(unit, lod)
1571 * dst.y = texture\_height(unit, lod)
1572 * dst.z = texture\_depth(unit, lod)
1573 * dst.w = texture\_levels(unit)
1574 *
1575 * dst.xyz map to NIR txs opcode, and dst.w maps to query_levels
1576 */
1577 static void
ttn_txq(struct ttn_compile * c,nir_alu_dest dest,nir_ssa_def ** src)1578 ttn_txq(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1579 {
1580 nir_builder *b = &c->build;
1581 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1582 nir_tex_instr *txs, *qlv;
1583
1584 txs = nir_tex_instr_create(b->shader, 2);
1585 txs->op = nir_texop_txs;
1586 get_texture_info(tgsi_inst->Texture.Texture,
1587 &txs->sampler_dim, &txs->is_shadow, &txs->is_array);
1588
1589 qlv = nir_tex_instr_create(b->shader, 1);
1590 qlv->op = nir_texop_query_levels;
1591 get_texture_info(tgsi_inst->Texture.Texture,
1592 &qlv->sampler_dim, &qlv->is_shadow, &qlv->is_array);
1593
1594 assert(tgsi_inst->Src[1].Register.File == TGSI_FILE_SAMPLER);
1595 int tex_index = tgsi_inst->Src[1].Register.Index;
1596
1597 nir_variable *var =
1598 get_sampler_var(c, tex_index, txs->sampler_dim,
1599 txs->is_shadow,
1600 txs->is_array,
1601 base_type_for_alu_type(txs->dest_type),
1602 nir_texop_txs);
1603
1604 nir_deref_instr *deref = nir_build_deref_var(b, var);
1605
1606 txs->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1607 txs->src[0].src_type = nir_tex_src_texture_deref;
1608
1609 qlv->src[0].src = nir_src_for_ssa(&deref->dest.ssa);
1610 qlv->src[0].src_type = nir_tex_src_texture_deref;
1611
1612 /* lod: */
1613 txs->src[1].src = nir_src_for_ssa(ttn_channel(b, src[0], X));
1614 txs->src[1].src_type = nir_tex_src_lod;
1615
1616 nir_ssa_dest_init(&txs->instr, &txs->dest,
1617 nir_tex_instr_dest_size(txs), 32, NULL);
1618 nir_builder_instr_insert(b, &txs->instr);
1619
1620 nir_ssa_dest_init(&qlv->instr, &qlv->dest, 1, 32, NULL);
1621 nir_builder_instr_insert(b, &qlv->instr);
1622
1623 ttn_move_dest_masked(b, dest, &txs->dest.ssa, TGSI_WRITEMASK_XYZ);
1624 ttn_move_dest_masked(b, dest, &qlv->dest.ssa, TGSI_WRITEMASK_W);
1625 }
1626
1627 static enum glsl_base_type
get_image_base_type(struct tgsi_full_instruction * tgsi_inst)1628 get_image_base_type(struct tgsi_full_instruction *tgsi_inst)
1629 {
1630 const struct util_format_description *desc =
1631 util_format_description(tgsi_inst->Memory.Format);
1632
1633 if (desc->channel[0].pure_integer) {
1634 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED)
1635 return GLSL_TYPE_INT;
1636 else
1637 return GLSL_TYPE_UINT;
1638 }
1639 return GLSL_TYPE_FLOAT;
1640 }
1641
1642 static enum gl_access_qualifier
get_mem_qualifier(struct tgsi_full_instruction * tgsi_inst)1643 get_mem_qualifier(struct tgsi_full_instruction *tgsi_inst)
1644 {
1645 enum gl_access_qualifier access = 0;
1646
1647 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_COHERENT)
1648 access |= ACCESS_COHERENT;
1649 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT)
1650 access |= ACCESS_RESTRICT;
1651 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
1652 access |= ACCESS_VOLATILE;
1653 if (tgsi_inst->Memory.Qualifier & TGSI_MEMORY_STREAM_CACHE_POLICY)
1654 access |= ACCESS_STREAM_CACHE_POLICY;
1655
1656 return access;
1657 }
1658
1659 static void
ttn_mem(struct ttn_compile * c,nir_alu_dest dest,nir_ssa_def ** src)1660 ttn_mem(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
1661 {
1662 nir_builder *b = &c->build;
1663 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1664 nir_intrinsic_instr *instr = NULL;
1665 unsigned resource_index, addr_src_index, file;
1666
1667 switch (tgsi_inst->Instruction.Opcode) {
1668 case TGSI_OPCODE_LOAD:
1669 assert(!tgsi_inst->Src[0].Register.Indirect);
1670 resource_index = tgsi_inst->Src[0].Register.Index;
1671 file = tgsi_inst->Src[0].Register.File;
1672 addr_src_index = 1;
1673 break;
1674 case TGSI_OPCODE_STORE:
1675 assert(!tgsi_inst->Dst[0].Register.Indirect);
1676 resource_index = tgsi_inst->Dst[0].Register.Index;
1677 file = tgsi_inst->Dst[0].Register.File;
1678 addr_src_index = 0;
1679 break;
1680 default:
1681 unreachable("unexpected memory opcode");
1682 }
1683
1684 if (file == TGSI_FILE_BUFFER) {
1685 nir_intrinsic_op op;
1686
1687 switch (tgsi_inst->Instruction.Opcode) {
1688 case TGSI_OPCODE_LOAD:
1689 op = nir_intrinsic_load_ssbo;
1690 break;
1691 case TGSI_OPCODE_STORE:
1692 op = nir_intrinsic_store_ssbo;
1693 break;
1694 default:
1695 unreachable("unexpected buffer opcode");
1696 }
1697
1698 add_ssbo_var(c, resource_index);
1699
1700 instr = nir_intrinsic_instr_create(b->shader, op);
1701 instr->num_components = util_last_bit(tgsi_inst->Dst[0].Register.WriteMask);
1702 nir_intrinsic_set_access(instr, get_mem_qualifier(tgsi_inst));
1703 nir_intrinsic_set_align(instr, 4, 0);
1704
1705 unsigned i = 0;
1706 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1707 instr->src[i++] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1708 instr->num_components));
1709 instr->src[i++] = nir_src_for_ssa(nir_imm_int(b, resource_index));
1710 instr->src[i++] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], X));
1711
1712 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE)
1713 nir_intrinsic_set_write_mask(instr, tgsi_inst->Dst[0].Register.WriteMask);
1714
1715 } else if (file == TGSI_FILE_IMAGE) {
1716 nir_intrinsic_op op;
1717
1718 switch (tgsi_inst->Instruction.Opcode) {
1719 case TGSI_OPCODE_LOAD:
1720 op = nir_intrinsic_image_deref_load;
1721 break;
1722 case TGSI_OPCODE_STORE:
1723 op = nir_intrinsic_image_deref_store;
1724 break;
1725 default:
1726 unreachable("unexpected file opcode");
1727 }
1728
1729 instr = nir_intrinsic_instr_create(b->shader, op);
1730
1731 /* Set the image variable dereference. */
1732 enum glsl_sampler_dim dim;
1733 bool is_array;
1734 get_texture_info(tgsi_inst->Memory.Texture, &dim, NULL, &is_array);
1735
1736 enum glsl_base_type base_type = get_image_base_type(tgsi_inst);
1737 enum gl_access_qualifier access = get_mem_qualifier(tgsi_inst);
1738
1739 nir_variable *image =
1740 get_image_var(c, resource_index,
1741 dim, is_array, base_type, access,
1742 tgsi_inst->Memory.Format);
1743 nir_deref_instr *image_deref = nir_build_deref_var(b, image);
1744 const struct glsl_type *type = image_deref->type;
1745
1746 nir_intrinsic_set_access(instr, image_deref->var->data.access);
1747
1748 instr->src[0] = nir_src_for_ssa(&image_deref->dest.ssa);
1749 instr->src[1] = nir_src_for_ssa(src[addr_src_index]);
1750
1751 /* Set the sample argument, which is undefined for single-sample images. */
1752 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_MS) {
1753 instr->src[2] = nir_src_for_ssa(ttn_channel(b, src[addr_src_index], W));
1754 } else {
1755 instr->src[2] = nir_src_for_ssa(nir_ssa_undef(b, 1, 32));
1756 }
1757
1758 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_LOAD) {
1759 instr->src[3] = nir_src_for_ssa(nir_imm_int(b, 0)); /* LOD */
1760 }
1761
1762 unsigned num_components = util_last_bit(tgsi_inst->Dst[0].Register.WriteMask);
1763
1764 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE) {
1765 instr->src[3] = nir_src_for_ssa(nir_swizzle(b, src[1], SWIZ(X, Y, Z, W),
1766 num_components));
1767 instr->src[4] = nir_src_for_ssa(nir_imm_int(b, 0)); /* LOD */
1768 }
1769
1770 instr->num_components = num_components;
1771 } else {
1772 unreachable("unexpected file");
1773 }
1774
1775
1776 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_LOAD) {
1777 nir_ssa_dest_init(&instr->instr, &instr->dest, instr->num_components,
1778 32, NULL);
1779 nir_builder_instr_insert(b, &instr->instr);
1780 ttn_move_dest(b, dest, &instr->dest.ssa);
1781 } else {
1782 nir_builder_instr_insert(b, &instr->instr);
1783 }
1784 }
1785
1786 static const nir_op op_trans[TGSI_OPCODE_LAST] = {
1787 [TGSI_OPCODE_ARL] = 0,
1788 [TGSI_OPCODE_MOV] = nir_op_mov,
1789 [TGSI_OPCODE_FBFETCH] = nir_op_mov,
1790 [TGSI_OPCODE_LIT] = 0,
1791 [TGSI_OPCODE_RCP] = nir_op_frcp,
1792 [TGSI_OPCODE_RSQ] = nir_op_frsq,
1793 [TGSI_OPCODE_EXP] = 0,
1794 [TGSI_OPCODE_LOG] = 0,
1795 [TGSI_OPCODE_MUL] = nir_op_fmul,
1796 [TGSI_OPCODE_ADD] = nir_op_fadd,
1797 [TGSI_OPCODE_DP3] = 0,
1798 [TGSI_OPCODE_DP4] = 0,
1799 [TGSI_OPCODE_DST] = 0,
1800 [TGSI_OPCODE_MIN] = nir_op_fmin,
1801 [TGSI_OPCODE_MAX] = nir_op_fmax,
1802 [TGSI_OPCODE_SLT] = nir_op_slt,
1803 [TGSI_OPCODE_SGE] = nir_op_sge,
1804 [TGSI_OPCODE_MAD] = nir_op_ffma,
1805 [TGSI_OPCODE_TEX_LZ] = 0,
1806 [TGSI_OPCODE_LRP] = 0,
1807 [TGSI_OPCODE_SQRT] = nir_op_fsqrt,
1808 [TGSI_OPCODE_FRC] = nir_op_ffract,
1809 [TGSI_OPCODE_TXF_LZ] = 0,
1810 [TGSI_OPCODE_FLR] = nir_op_ffloor,
1811 [TGSI_OPCODE_ROUND] = nir_op_fround_even,
1812 [TGSI_OPCODE_EX2] = nir_op_fexp2,
1813 [TGSI_OPCODE_LG2] = nir_op_flog2,
1814 [TGSI_OPCODE_POW] = nir_op_fpow,
1815 [TGSI_OPCODE_COS] = nir_op_fcos,
1816 [TGSI_OPCODE_DDX] = nir_op_fddx,
1817 [TGSI_OPCODE_DDY] = nir_op_fddy,
1818 [TGSI_OPCODE_KILL] = 0,
1819 [TGSI_OPCODE_PK2H] = 0, /* XXX */
1820 [TGSI_OPCODE_PK2US] = 0, /* XXX */
1821 [TGSI_OPCODE_PK4B] = 0, /* XXX */
1822 [TGSI_OPCODE_PK4UB] = 0, /* XXX */
1823 [TGSI_OPCODE_SEQ] = nir_op_seq,
1824 [TGSI_OPCODE_SGT] = 0,
1825 [TGSI_OPCODE_SIN] = nir_op_fsin,
1826 [TGSI_OPCODE_SNE] = nir_op_sne,
1827 [TGSI_OPCODE_SLE] = 0,
1828 [TGSI_OPCODE_TEX] = 0,
1829 [TGSI_OPCODE_TXD] = 0,
1830 [TGSI_OPCODE_TXP] = 0,
1831 [TGSI_OPCODE_UP2H] = 0, /* XXX */
1832 [TGSI_OPCODE_UP2US] = 0, /* XXX */
1833 [TGSI_OPCODE_UP4B] = 0, /* XXX */
1834 [TGSI_OPCODE_UP4UB] = 0, /* XXX */
1835 [TGSI_OPCODE_ARR] = 0,
1836
1837 /* No function calls, yet. */
1838 [TGSI_OPCODE_CAL] = 0, /* XXX */
1839 [TGSI_OPCODE_RET] = 0, /* XXX */
1840
1841 [TGSI_OPCODE_SSG] = nir_op_fsign,
1842 [TGSI_OPCODE_CMP] = 0,
1843 [TGSI_OPCODE_TXB] = 0,
1844 [TGSI_OPCODE_DIV] = nir_op_fdiv,
1845 [TGSI_OPCODE_DP2] = 0,
1846 [TGSI_OPCODE_TXL] = 0,
1847
1848 [TGSI_OPCODE_BRK] = 0,
1849 [TGSI_OPCODE_IF] = 0,
1850 [TGSI_OPCODE_UIF] = 0,
1851 [TGSI_OPCODE_ELSE] = 0,
1852 [TGSI_OPCODE_ENDIF] = 0,
1853
1854 [TGSI_OPCODE_DDX_FINE] = nir_op_fddx_fine,
1855 [TGSI_OPCODE_DDY_FINE] = nir_op_fddy_fine,
1856
1857 [TGSI_OPCODE_CEIL] = nir_op_fceil,
1858 [TGSI_OPCODE_I2F] = nir_op_i2f32,
1859 [TGSI_OPCODE_NOT] = nir_op_inot,
1860 [TGSI_OPCODE_TRUNC] = nir_op_ftrunc,
1861 [TGSI_OPCODE_SHL] = nir_op_ishl,
1862 [TGSI_OPCODE_AND] = nir_op_iand,
1863 [TGSI_OPCODE_OR] = nir_op_ior,
1864 [TGSI_OPCODE_MOD] = nir_op_umod,
1865 [TGSI_OPCODE_XOR] = nir_op_ixor,
1866 [TGSI_OPCODE_TXF] = 0,
1867 [TGSI_OPCODE_TXQ] = 0,
1868
1869 [TGSI_OPCODE_CONT] = 0,
1870
1871 [TGSI_OPCODE_EMIT] = 0, /* XXX */
1872 [TGSI_OPCODE_ENDPRIM] = 0, /* XXX */
1873
1874 [TGSI_OPCODE_BGNLOOP] = 0,
1875 [TGSI_OPCODE_BGNSUB] = 0, /* XXX: no function calls */
1876 [TGSI_OPCODE_ENDLOOP] = 0,
1877 [TGSI_OPCODE_ENDSUB] = 0, /* XXX: no function calls */
1878
1879 [TGSI_OPCODE_NOP] = 0,
1880 [TGSI_OPCODE_FSEQ] = nir_op_feq,
1881 [TGSI_OPCODE_FSGE] = nir_op_fge,
1882 [TGSI_OPCODE_FSLT] = nir_op_flt,
1883 [TGSI_OPCODE_FSNE] = nir_op_fneu,
1884
1885 [TGSI_OPCODE_KILL_IF] = 0,
1886
1887 [TGSI_OPCODE_END] = 0,
1888
1889 [TGSI_OPCODE_F2I] = nir_op_f2i32,
1890 [TGSI_OPCODE_IDIV] = nir_op_idiv,
1891 [TGSI_OPCODE_IMAX] = nir_op_imax,
1892 [TGSI_OPCODE_IMIN] = nir_op_imin,
1893 [TGSI_OPCODE_INEG] = nir_op_ineg,
1894 [TGSI_OPCODE_ISGE] = nir_op_ige,
1895 [TGSI_OPCODE_ISHR] = nir_op_ishr,
1896 [TGSI_OPCODE_ISLT] = nir_op_ilt,
1897 [TGSI_OPCODE_F2U] = nir_op_f2u32,
1898 [TGSI_OPCODE_U2F] = nir_op_u2f32,
1899 [TGSI_OPCODE_UADD] = nir_op_iadd,
1900 [TGSI_OPCODE_UDIV] = nir_op_udiv,
1901 [TGSI_OPCODE_UMAD] = 0,
1902 [TGSI_OPCODE_UMAX] = nir_op_umax,
1903 [TGSI_OPCODE_UMIN] = nir_op_umin,
1904 [TGSI_OPCODE_UMOD] = nir_op_umod,
1905 [TGSI_OPCODE_UMUL] = nir_op_imul,
1906 [TGSI_OPCODE_USEQ] = nir_op_ieq,
1907 [TGSI_OPCODE_USGE] = nir_op_uge,
1908 [TGSI_OPCODE_USHR] = nir_op_ushr,
1909 [TGSI_OPCODE_USLT] = nir_op_ult,
1910 [TGSI_OPCODE_USNE] = nir_op_ine,
1911
1912 [TGSI_OPCODE_SWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
1913 [TGSI_OPCODE_CASE] = 0, /* not emitted by glsl_to_tgsi.cpp */
1914 [TGSI_OPCODE_DEFAULT] = 0, /* not emitted by glsl_to_tgsi.cpp */
1915 [TGSI_OPCODE_ENDSWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */
1916
1917 /* XXX: SAMPLE opcodes */
1918
1919 [TGSI_OPCODE_UARL] = nir_op_mov,
1920 [TGSI_OPCODE_UCMP] = 0,
1921 [TGSI_OPCODE_IABS] = nir_op_iabs,
1922 [TGSI_OPCODE_ISSG] = nir_op_isign,
1923
1924 [TGSI_OPCODE_LOAD] = 0,
1925 [TGSI_OPCODE_STORE] = 0,
1926
1927 /* XXX: atomics */
1928
1929 [TGSI_OPCODE_TEX2] = 0,
1930 [TGSI_OPCODE_TXB2] = 0,
1931 [TGSI_OPCODE_TXL2] = 0,
1932
1933 [TGSI_OPCODE_IMUL_HI] = nir_op_imul_high,
1934 [TGSI_OPCODE_UMUL_HI] = nir_op_umul_high,
1935
1936 [TGSI_OPCODE_TG4] = 0,
1937 [TGSI_OPCODE_LODQ] = 0,
1938
1939 [TGSI_OPCODE_IBFE] = nir_op_ibitfield_extract,
1940 [TGSI_OPCODE_UBFE] = nir_op_ubitfield_extract,
1941 [TGSI_OPCODE_BFI] = nir_op_bitfield_insert,
1942 [TGSI_OPCODE_BREV] = nir_op_bitfield_reverse,
1943 [TGSI_OPCODE_POPC] = nir_op_bit_count,
1944 [TGSI_OPCODE_LSB] = nir_op_find_lsb,
1945 [TGSI_OPCODE_IMSB] = nir_op_ifind_msb,
1946 [TGSI_OPCODE_UMSB] = nir_op_ufind_msb,
1947
1948 [TGSI_OPCODE_INTERP_CENTROID] = 0, /* XXX */
1949 [TGSI_OPCODE_INTERP_SAMPLE] = 0, /* XXX */
1950 [TGSI_OPCODE_INTERP_OFFSET] = 0, /* XXX */
1951
1952 [TGSI_OPCODE_F2D] = nir_op_f2f64,
1953 [TGSI_OPCODE_D2F] = nir_op_f2f32,
1954 [TGSI_OPCODE_DMUL] = nir_op_fmul,
1955 [TGSI_OPCODE_D2U] = nir_op_f2u32,
1956 [TGSI_OPCODE_U2D] = nir_op_u2f64,
1957
1958 [TGSI_OPCODE_U64ADD] = nir_op_iadd,
1959 [TGSI_OPCODE_U64MUL] = nir_op_imul,
1960 [TGSI_OPCODE_U64DIV] = nir_op_udiv,
1961 [TGSI_OPCODE_U64SNE] = nir_op_ine,
1962 [TGSI_OPCODE_I64NEG] = nir_op_ineg,
1963 [TGSI_OPCODE_I64ABS] = nir_op_iabs,
1964 };
1965
1966 static void
ttn_emit_instruction(struct ttn_compile * c)1967 ttn_emit_instruction(struct ttn_compile *c)
1968 {
1969 nir_builder *b = &c->build;
1970 struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
1971 unsigned i;
1972 unsigned tgsi_op = tgsi_inst->Instruction.Opcode;
1973 struct tgsi_full_dst_register *tgsi_dst = &tgsi_inst->Dst[0];
1974
1975 if (tgsi_op == TGSI_OPCODE_END)
1976 return;
1977
1978 nir_ssa_def *src[TGSI_FULL_MAX_SRC_REGISTERS];
1979 for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++) {
1980 src[i] = ttn_get_src(c, &tgsi_inst->Src[i], i);
1981 }
1982 nir_alu_dest dest = ttn_get_dest(c, tgsi_dst);
1983
1984 unsigned tgsi_dst_type = tgsi_opcode_infer_dst_type(tgsi_op, 0);
1985
1986 /* The destination bitsize of the NIR opcode (not TGSI, where it's always
1987 * 32 bits). This needs to be passed into ttn_alu() because it can't be
1988 * inferred for comparison opcodes.
1989 */
1990 unsigned dst_bitsize = tgsi_type_is_64bit(tgsi_dst_type) ? 64 : 32;
1991
1992 switch (tgsi_op) {
1993 case TGSI_OPCODE_RSQ:
1994 ttn_move_dest(b, dest, nir_frsq(b, ttn_channel(b, src[0], X)));
1995 break;
1996
1997 case TGSI_OPCODE_SQRT:
1998 ttn_move_dest(b, dest, nir_fsqrt(b, ttn_channel(b, src[0], X)));
1999 break;
2000
2001 case TGSI_OPCODE_RCP:
2002 ttn_move_dest(b, dest, nir_frcp(b, ttn_channel(b, src[0], X)));
2003 break;
2004
2005 case TGSI_OPCODE_EX2:
2006 ttn_move_dest(b, dest, nir_fexp2(b, ttn_channel(b, src[0], X)));
2007 break;
2008
2009 case TGSI_OPCODE_LG2:
2010 ttn_move_dest(b, dest, nir_flog2(b, ttn_channel(b, src[0], X)));
2011 break;
2012
2013 case TGSI_OPCODE_POW:
2014 ttn_move_dest(b, dest, nir_fpow(b,
2015 ttn_channel(b, src[0], X),
2016 ttn_channel(b, src[1], X)));
2017 break;
2018
2019 case TGSI_OPCODE_COS:
2020 ttn_move_dest(b, dest, nir_fcos(b, ttn_channel(b, src[0], X)));
2021 break;
2022
2023 case TGSI_OPCODE_SIN:
2024 ttn_move_dest(b, dest, nir_fsin(b, ttn_channel(b, src[0], X)));
2025 break;
2026
2027 case TGSI_OPCODE_ARL:
2028 ttn_arl(b, op_trans[tgsi_op], dest, src);
2029 break;
2030
2031 case TGSI_OPCODE_EXP:
2032 ttn_exp(b, op_trans[tgsi_op], dest, src);
2033 break;
2034
2035 case TGSI_OPCODE_LOG:
2036 ttn_log(b, op_trans[tgsi_op], dest, src);
2037 break;
2038
2039 case TGSI_OPCODE_DST:
2040 ttn_dst(b, op_trans[tgsi_op], dest, src);
2041 break;
2042
2043 case TGSI_OPCODE_LIT:
2044 ttn_lit(b, op_trans[tgsi_op], dest, src);
2045 break;
2046
2047 case TGSI_OPCODE_DP2:
2048 ttn_dp2(b, op_trans[tgsi_op], dest, src);
2049 break;
2050
2051 case TGSI_OPCODE_DP3:
2052 ttn_dp3(b, op_trans[tgsi_op], dest, src);
2053 break;
2054
2055 case TGSI_OPCODE_DP4:
2056 ttn_dp4(b, op_trans[tgsi_op], dest, src);
2057 break;
2058
2059 case TGSI_OPCODE_UMAD:
2060 ttn_umad(b, op_trans[tgsi_op], dest, src);
2061 break;
2062
2063 case TGSI_OPCODE_LRP:
2064 ttn_move_dest(b, dest, nir_flrp(b, src[2], src[1], src[0]));
2065 break;
2066
2067 case TGSI_OPCODE_KILL:
2068 ttn_kill(b, op_trans[tgsi_op], dest, src);
2069 break;
2070
2071 case TGSI_OPCODE_ARR:
2072 ttn_arr(b, op_trans[tgsi_op], dest, src);
2073 break;
2074
2075 case TGSI_OPCODE_CMP:
2076 ttn_cmp(b, op_trans[tgsi_op], dest, src);
2077 break;
2078
2079 case TGSI_OPCODE_UCMP:
2080 ttn_ucmp(b, op_trans[tgsi_op], dest, src);
2081 break;
2082
2083 case TGSI_OPCODE_SGT:
2084 ttn_sgt(b, op_trans[tgsi_op], dest, src);
2085 break;
2086
2087 case TGSI_OPCODE_SLE:
2088 ttn_sle(b, op_trans[tgsi_op], dest, src);
2089 break;
2090
2091 case TGSI_OPCODE_KILL_IF:
2092 ttn_kill_if(b, op_trans[tgsi_op], dest, src);
2093 break;
2094
2095 case TGSI_OPCODE_TEX:
2096 case TGSI_OPCODE_TEX_LZ:
2097 case TGSI_OPCODE_TXP:
2098 case TGSI_OPCODE_TXL:
2099 case TGSI_OPCODE_TXB:
2100 case TGSI_OPCODE_TXD:
2101 case TGSI_OPCODE_TEX2:
2102 case TGSI_OPCODE_TXL2:
2103 case TGSI_OPCODE_TXB2:
2104 case TGSI_OPCODE_TXF:
2105 case TGSI_OPCODE_TXF_LZ:
2106 case TGSI_OPCODE_TG4:
2107 case TGSI_OPCODE_LODQ:
2108 ttn_tex(c, dest, src);
2109 break;
2110
2111 case TGSI_OPCODE_TXQ:
2112 ttn_txq(c, dest, src);
2113 break;
2114
2115 case TGSI_OPCODE_LOAD:
2116 case TGSI_OPCODE_STORE:
2117 ttn_mem(c, dest, src);
2118 break;
2119
2120 case TGSI_OPCODE_NOP:
2121 break;
2122
2123 case TGSI_OPCODE_IF:
2124 nir_push_if(b, nir_fneu(b, nir_channel(b, src[0], 0), nir_imm_float(b, 0.0)));
2125 break;
2126
2127 case TGSI_OPCODE_UIF:
2128 nir_push_if(b, nir_ine(b, nir_channel(b, src[0], 0), nir_imm_int(b, 0)));
2129 break;
2130
2131 case TGSI_OPCODE_ELSE:
2132 nir_push_else(&c->build, NULL);
2133 break;
2134
2135 case TGSI_OPCODE_ENDIF:
2136 nir_pop_if(&c->build, NULL);
2137 break;
2138
2139 case TGSI_OPCODE_BGNLOOP:
2140 nir_push_loop(&c->build);
2141 break;
2142
2143 case TGSI_OPCODE_BRK:
2144 nir_jump(b, nir_jump_break);
2145 break;
2146
2147 case TGSI_OPCODE_CONT:
2148 nir_jump(b, nir_jump_continue);
2149 break;
2150
2151 case TGSI_OPCODE_ENDLOOP:
2152 nir_pop_loop(&c->build, NULL);
2153 break;
2154
2155 case TGSI_OPCODE_BARRIER:
2156 ttn_barrier(b);
2157 break;
2158
2159 default:
2160 if (op_trans[tgsi_op] != 0 || tgsi_op == TGSI_OPCODE_MOV) {
2161 ttn_alu(b, op_trans[tgsi_op], dest, dst_bitsize, src);
2162 } else {
2163 fprintf(stderr, "unknown TGSI opcode: %s\n",
2164 tgsi_get_opcode_name(tgsi_op));
2165 abort();
2166 }
2167 break;
2168 }
2169
2170 if (tgsi_inst->Instruction.Saturate) {
2171 assert(!dest.dest.is_ssa);
2172 ttn_move_dest(b, dest, nir_fsat(b, ttn_src_for_dest(b, &dest)));
2173 }
2174
2175 /* if the dst has a matching var, append store_var to move
2176 * output from reg to var
2177 */
2178 nir_variable *var = ttn_get_var(c, tgsi_dst);
2179 if (var) {
2180 unsigned index = tgsi_dst->Register.Index;
2181 unsigned offset = c->temp_regs[index].offset;
2182 struct tgsi_ind_register *indirect = tgsi_dst->Register.Indirect ?
2183 &tgsi_dst->Indirect : NULL;
2184 nir_src val = nir_src_for_reg(dest.dest.reg.reg);
2185 nir_store_deref(b, ttn_array_deref(c, var, offset, indirect),
2186 nir_ssa_for_src(b, val, 4), dest.write_mask);
2187 }
2188 }
2189
2190 /**
2191 * Puts a NIR intrinsic to store of each TGSI_FILE_OUTPUT value to the output
2192 * variables at the end of the shader.
2193 *
2194 * We don't generate these incrementally as the TGSI_FILE_OUTPUT values are
2195 * written, because there's no output load intrinsic, which means we couldn't
2196 * handle writemasks.
2197 */
2198 static void
ttn_add_output_stores(struct ttn_compile * c)2199 ttn_add_output_stores(struct ttn_compile *c)
2200 {
2201 nir_builder *b = &c->build;
2202
2203 for (int i = 0; i < c->build.shader->num_outputs; i++) {
2204 nir_variable *var = c->outputs[i];
2205 if (!var)
2206 continue;
2207
2208 nir_src src = nir_src_for_reg(c->output_regs[i].reg);
2209 src.reg.base_offset = c->output_regs[i].offset;
2210
2211 nir_ssa_def *store_value = nir_ssa_for_src(b, src, 4);
2212 if (c->build.shader->info.stage == MESA_SHADER_FRAGMENT) {
2213 /* TGSI uses TGSI_SEMANTIC_POSITION.z for the depth output
2214 * and TGSI_SEMANTIC_STENCIL.y for the stencil output,
2215 * while NIR uses a single-component output.
2216 */
2217 if (var->data.location == FRAG_RESULT_DEPTH)
2218 store_value = nir_channel(b, store_value, 2);
2219 else if (var->data.location == FRAG_RESULT_STENCIL)
2220 store_value = nir_channel(b, store_value, 1);
2221 else if (var->data.location == FRAG_RESULT_SAMPLE_MASK)
2222 store_value = nir_channel(b, store_value, 0);
2223 } else {
2224 /* FOGC, LAYER, and PSIZ are scalar values */
2225 if (var->data.location == VARYING_SLOT_FOGC ||
2226 var->data.location == VARYING_SLOT_LAYER ||
2227 var->data.location == VARYING_SLOT_PSIZ) {
2228 store_value = nir_channel(b, store_value, 0);
2229 }
2230 }
2231
2232 nir_store_deref(b, nir_build_deref_var(b, var), store_value,
2233 (1 << store_value->num_components) - 1);
2234 }
2235 }
2236
2237 /**
2238 * Parses the given TGSI tokens.
2239 */
2240 static void
ttn_parse_tgsi(struct ttn_compile * c,const void * tgsi_tokens)2241 ttn_parse_tgsi(struct ttn_compile *c, const void *tgsi_tokens)
2242 {
2243 struct tgsi_parse_context parser;
2244 ASSERTED int ret;
2245
2246 ret = tgsi_parse_init(&parser, tgsi_tokens);
2247 assert(ret == TGSI_PARSE_OK);
2248
2249 while (!tgsi_parse_end_of_tokens(&parser)) {
2250 tgsi_parse_token(&parser);
2251 c->token = &parser.FullToken;
2252
2253 switch (parser.FullToken.Token.Type) {
2254 case TGSI_TOKEN_TYPE_DECLARATION:
2255 ttn_emit_declaration(c);
2256 break;
2257
2258 case TGSI_TOKEN_TYPE_INSTRUCTION:
2259 ttn_emit_instruction(c);
2260 break;
2261
2262 case TGSI_TOKEN_TYPE_IMMEDIATE:
2263 ttn_emit_immediate(c);
2264 break;
2265 }
2266 }
2267
2268 tgsi_parse_free(&parser);
2269 }
2270
2271 static void
ttn_read_pipe_caps(struct ttn_compile * c,struct pipe_screen * screen)2272 ttn_read_pipe_caps(struct ttn_compile *c,
2273 struct pipe_screen *screen)
2274 {
2275 c->cap_samplers_as_deref = screen->get_param(screen, PIPE_CAP_NIR_SAMPLERS_AS_DEREF);
2276 c->cap_face_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL);
2277 c->cap_position_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL);
2278 c->cap_point_is_sysval = screen->get_param(screen, PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL);
2279 }
2280
2281 /**
2282 * Initializes a TGSI-to-NIR compiler.
2283 */
2284 static struct ttn_compile *
ttn_compile_init(const void * tgsi_tokens,const nir_shader_compiler_options * options,struct pipe_screen * screen)2285 ttn_compile_init(const void *tgsi_tokens,
2286 const nir_shader_compiler_options *options,
2287 struct pipe_screen *screen)
2288 {
2289 struct ttn_compile *c;
2290 struct nir_shader *s;
2291 struct tgsi_shader_info scan;
2292
2293 assert(options || screen);
2294 c = rzalloc(NULL, struct ttn_compile);
2295
2296 tgsi_scan_shader(tgsi_tokens, &scan);
2297 c->scan = &scan;
2298
2299 if (!options) {
2300 options =
2301 screen->get_compiler_options(screen, PIPE_SHADER_IR_NIR, scan.processor);
2302 }
2303
2304 c->build = nir_builder_init_simple_shader(tgsi_processor_to_shader_stage(scan.processor),
2305 options, "TTN");
2306
2307 s = c->build.shader;
2308
2309 if (screen) {
2310 ttn_read_pipe_caps(c, screen);
2311 } else {
2312 /* TTN used to be hard coded to always make FACE a sysval,
2313 * so it makes sense to preserve that behavior so users don't break. */
2314 c->cap_face_is_sysval = true;
2315 }
2316
2317 if (s->info.stage == MESA_SHADER_FRAGMENT)
2318 s->info.fs.untyped_color_outputs = true;
2319
2320 s->num_inputs = scan.file_max[TGSI_FILE_INPUT] + 1;
2321 s->num_uniforms = scan.const_file_max[0] + 1;
2322 s->num_outputs = scan.file_max[TGSI_FILE_OUTPUT] + 1;
2323 s->info.num_ssbos = util_last_bit(scan.shader_buffers_declared);
2324 s->info.num_ubos = util_last_bit(scan.const_buffers_declared >> 1);
2325 s->info.num_images = util_last_bit(scan.images_declared);
2326 s->info.num_textures = util_last_bit(scan.samplers_declared);
2327
2328 for (unsigned i = 0; i < TGSI_PROPERTY_COUNT; i++) {
2329 unsigned value = scan.properties[i];
2330
2331 switch (i) {
2332 case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
2333 break; /* handled in ttn_emit_declaration */
2334 case TGSI_PROPERTY_FS_COORD_ORIGIN:
2335 if (s->info.stage == MESA_SHADER_FRAGMENT)
2336 s->info.fs.origin_upper_left = value == TGSI_FS_COORD_ORIGIN_UPPER_LEFT;
2337 break;
2338 case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
2339 if (s->info.stage == MESA_SHADER_FRAGMENT)
2340 s->info.fs.pixel_center_integer = value == TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
2341 break;
2342 case TGSI_PROPERTY_FS_DEPTH_LAYOUT:
2343 if (s->info.stage == MESA_SHADER_FRAGMENT)
2344 s->info.fs.depth_layout = ttn_get_depth_layout(value);
2345 break;
2346 case TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION:
2347 if (s->info.stage == MESA_SHADER_VERTEX)
2348 s->info.vs.window_space_position = value;
2349 break;
2350 case TGSI_PROPERTY_NEXT_SHADER:
2351 s->info.next_stage = tgsi_processor_to_shader_stage(value);
2352 break;
2353 case TGSI_PROPERTY_VS_BLIT_SGPRS_AMD:
2354 if (s->info.stage == MESA_SHADER_VERTEX)
2355 s->info.vs.blit_sgprs_amd = value;
2356 break;
2357 case TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH:
2358 if (s->info.stage == MESA_SHADER_COMPUTE)
2359 s->info.workgroup_size[0] = value;
2360 break;
2361 case TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT:
2362 if (s->info.stage == MESA_SHADER_COMPUTE)
2363 s->info.workgroup_size[1] = value;
2364 break;
2365 case TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH:
2366 if (s->info.stage == MESA_SHADER_COMPUTE)
2367 s->info.workgroup_size[2] = value;
2368 break;
2369 case TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD:
2370 if (s->info.stage == MESA_SHADER_COMPUTE)
2371 s->info.cs.user_data_components_amd = value;
2372 break;
2373 case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
2374 s->info.clip_distance_array_size = value;
2375 break;
2376 default:
2377 if (value) {
2378 fprintf(stderr, "tgsi_to_nir: unhandled TGSI property %u = %u\n",
2379 i, value);
2380 unreachable("unhandled TGSI property");
2381 }
2382 }
2383 }
2384
2385 if (s->info.stage == MESA_SHADER_COMPUTE &&
2386 (!s->info.workgroup_size[0] ||
2387 !s->info.workgroup_size[1] ||
2388 !s->info.workgroup_size[2]))
2389 s->info.workgroup_size_variable = true;
2390
2391 c->inputs = rzalloc_array(c, struct nir_variable *, s->num_inputs);
2392 c->outputs = rzalloc_array(c, struct nir_variable *, s->num_outputs);
2393
2394 c->output_regs = rzalloc_array(c, struct ttn_reg_info,
2395 scan.file_max[TGSI_FILE_OUTPUT] + 1);
2396 c->temp_regs = rzalloc_array(c, struct ttn_reg_info,
2397 scan.file_max[TGSI_FILE_TEMPORARY] + 1);
2398 c->imm_defs = rzalloc_array(c, nir_ssa_def *,
2399 scan.file_max[TGSI_FILE_IMMEDIATE] + 1);
2400
2401 c->num_samp_types = scan.file_max[TGSI_FILE_SAMPLER_VIEW] + 1;
2402 c->samp_types = rzalloc_array(c, nir_alu_type, c->num_samp_types);
2403
2404 ttn_parse_tgsi(c, tgsi_tokens);
2405 ttn_add_output_stores(c);
2406
2407 nir_validate_shader(c->build.shader, "TTN: after parsing TGSI and creating the NIR shader");
2408
2409 return c;
2410 }
2411
2412 static void
ttn_optimize_nir(nir_shader * nir)2413 ttn_optimize_nir(nir_shader *nir)
2414 {
2415 bool progress;
2416 do {
2417 progress = false;
2418
2419 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2420
2421 if (nir->options->lower_to_scalar) {
2422 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL);
2423 NIR_PASS_V(nir, nir_lower_phis_to_scalar, false);
2424 }
2425
2426 NIR_PASS_V(nir, nir_lower_alu);
2427 NIR_PASS_V(nir, nir_lower_pack);
2428 NIR_PASS(progress, nir, nir_copy_prop);
2429 NIR_PASS(progress, nir, nir_opt_remove_phis);
2430 NIR_PASS(progress, nir, nir_opt_dce);
2431
2432 if (nir_opt_trivial_continues(nir)) {
2433 progress = true;
2434 NIR_PASS(progress, nir, nir_copy_prop);
2435 NIR_PASS(progress, nir, nir_opt_dce);
2436 }
2437
2438 NIR_PASS(progress, nir, nir_opt_if, false);
2439 NIR_PASS(progress, nir, nir_opt_dead_cf);
2440 NIR_PASS(progress, nir, nir_opt_cse);
2441 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
2442
2443 NIR_PASS(progress, nir, nir_opt_algebraic);
2444 NIR_PASS(progress, nir, nir_opt_constant_folding);
2445
2446 NIR_PASS(progress, nir, nir_opt_undef);
2447 NIR_PASS(progress, nir, nir_opt_conditional_discard);
2448
2449 if (nir->options->max_unroll_iterations) {
2450 NIR_PASS(progress, nir, nir_opt_loop_unroll);
2451 }
2452
2453 } while (progress);
2454
2455 }
2456
2457 /**
2458 * Finalizes the NIR in a similar way as st_glsl_to_nir does.
2459 *
2460 * Drivers expect that these passes are already performed,
2461 * so we have to do it here too.
2462 */
2463 static void
ttn_finalize_nir(struct ttn_compile * c,struct pipe_screen * screen)2464 ttn_finalize_nir(struct ttn_compile *c, struct pipe_screen *screen)
2465 {
2466 struct nir_shader *nir = c->build.shader;
2467
2468 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
2469 NIR_PASS_V(nir, nir_lower_regs_to_ssa);
2470
2471 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
2472 NIR_PASS_V(nir, nir_split_var_copies);
2473 NIR_PASS_V(nir, nir_lower_var_copies);
2474 NIR_PASS_V(nir, nir_lower_system_values);
2475 NIR_PASS_V(nir, nir_lower_compute_system_values, NULL);
2476
2477 if (!screen->get_param(screen, PIPE_CAP_TEXRECT)) {
2478 const struct nir_lower_tex_options opts = { .lower_rect = true, };
2479 NIR_PASS_V(nir, nir_lower_tex, &opts);
2480 }
2481
2482 if (nir->options->lower_uniforms_to_ubo)
2483 NIR_PASS_V(nir, nir_lower_uniforms_to_ubo, false, false);
2484
2485 if (!c->cap_samplers_as_deref)
2486 NIR_PASS_V(nir, nir_lower_samplers);
2487
2488 if (screen->finalize_nir) {
2489 char *msg = screen->finalize_nir(screen, nir);
2490 free(msg);
2491 } else {
2492 ttn_optimize_nir(nir);
2493 nir_shader_gather_info(nir, c->build.impl);
2494 }
2495
2496 nir->info.num_images = c->num_images;
2497 nir->info.num_textures = c->num_samplers;
2498
2499 nir_validate_shader(nir, "TTN: after all optimizations");
2500 }
2501
save_nir_to_disk_cache(struct disk_cache * cache,uint8_t key[CACHE_KEY_SIZE],const nir_shader * s)2502 static void save_nir_to_disk_cache(struct disk_cache *cache,
2503 uint8_t key[CACHE_KEY_SIZE],
2504 const nir_shader *s)
2505 {
2506 struct blob blob = {0};
2507
2508 blob_init(&blob);
2509 /* Because we cannot fully trust disk_cache_put
2510 * (EGL_ANDROID_blob_cache) we add the shader size,
2511 * which we'll check after disk_cache_get().
2512 */
2513 if (blob_reserve_uint32(&blob) != 0) {
2514 blob_finish(&blob);
2515 return;
2516 }
2517
2518 nir_serialize(&blob, s, true);
2519 *(uint32_t *)blob.data = blob.size;
2520
2521 disk_cache_put(cache, key, blob.data, blob.size, NULL);
2522 blob_finish(&blob);
2523 }
2524
2525 static nir_shader *
load_nir_from_disk_cache(struct disk_cache * cache,struct pipe_screen * screen,uint8_t key[CACHE_KEY_SIZE],unsigned processor)2526 load_nir_from_disk_cache(struct disk_cache *cache,
2527 struct pipe_screen *screen,
2528 uint8_t key[CACHE_KEY_SIZE],
2529 unsigned processor)
2530 {
2531 const nir_shader_compiler_options *options =
2532 screen->get_compiler_options(screen, PIPE_SHADER_IR_NIR, processor);
2533 struct blob_reader blob_reader;
2534 size_t size;
2535 nir_shader *s;
2536
2537 uint32_t *buffer = (uint32_t *)disk_cache_get(cache, key, &size);
2538 if (!buffer)
2539 return NULL;
2540
2541 /* Match found. No need to check crc32 or other things.
2542 * disk_cache_get is supposed to do that for us.
2543 * However we do still check if the first element is indeed the size,
2544 * as we cannot fully trust disk_cache_get (EGL_ANDROID_blob_cache) */
2545 if (buffer[0] != size) {
2546 return NULL;
2547 }
2548
2549 size -= 4;
2550 blob_reader_init(&blob_reader, buffer + 1, size);
2551 s = nir_deserialize(NULL, options, &blob_reader);
2552 free(buffer); /* buffer was malloc-ed */
2553 return s;
2554 }
2555
2556 struct nir_shader *
tgsi_to_nir(const void * tgsi_tokens,struct pipe_screen * screen,bool allow_disk_cache)2557 tgsi_to_nir(const void *tgsi_tokens,
2558 struct pipe_screen *screen,
2559 bool allow_disk_cache)
2560 {
2561 struct disk_cache *cache = NULL;
2562 struct ttn_compile *c;
2563 struct nir_shader *s = NULL;
2564 uint8_t key[CACHE_KEY_SIZE];
2565 unsigned processor;
2566 bool debug = env_var_as_boolean("TGSI_TO_NIR_DEBUG", false);
2567
2568 if (allow_disk_cache)
2569 cache = screen->get_disk_shader_cache(screen);
2570
2571 /* Look first in the cache */
2572 if (cache) {
2573 disk_cache_compute_key(cache,
2574 tgsi_tokens,
2575 tgsi_num_tokens(tgsi_tokens) * sizeof(struct tgsi_token),
2576 key);
2577 processor = tgsi_get_processor_type(tgsi_tokens);
2578 s = load_nir_from_disk_cache(cache, screen, key, processor);
2579 }
2580
2581 if (s)
2582 return s;
2583
2584 if (debug) {
2585 fprintf(stderr, "TGSI before translation to NIR:\n");
2586 tgsi_dump(tgsi_tokens, 0);
2587 }
2588
2589 /* Not in the cache */
2590
2591 c = ttn_compile_init(tgsi_tokens, NULL, screen);
2592 s = c->build.shader;
2593 ttn_finalize_nir(c, screen);
2594 ralloc_free(c);
2595
2596 if (debug) {
2597 mesa_logi("NIR after translation from TGSI:\n");
2598 nir_log_shaderi(s);
2599 }
2600
2601 if (cache)
2602 save_nir_to_disk_cache(cache, key, s);
2603
2604 return s;
2605 }
2606
2607 struct nir_shader *
tgsi_to_nir_noscreen(const void * tgsi_tokens,const nir_shader_compiler_options * options)2608 tgsi_to_nir_noscreen(const void *tgsi_tokens,
2609 const nir_shader_compiler_options *options)
2610 {
2611 struct ttn_compile *c;
2612 struct nir_shader *s;
2613
2614 c = ttn_compile_init(tgsi_tokens, options, NULL);
2615 s = c->build.shader;
2616 ralloc_free(c);
2617
2618 return s;
2619 }
2620
2621