Searched refs:CSR0_INEA (Results 1 – 4 of 4) sorted by relevance
218 #define CSR0_INEA 0x0040 /* interrupt enable (RW) */ macro443 DREG = CSR0_IDON | CSR0_STRT | CSR0_INEA; in lance_open()561 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT; in lance_start_xmit()637 REGA(CSR0) = CSR0_INEA | CSR0_TDMD | CSR0_STRT; in lance_start_xmit()712 REGA(CSR0) = CSR0_STRT | CSR0_INEA; in lance_interrupt()750 REGA(CSR0) = CSR0_STRT | CSR0_INEA; in lance_interrupt()758 REGA(CSR0) = CSR0_INEA; in lance_interrupt()923 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT; in set_multicast_list()
318 #define CSR0_INEA 0x0040 /* interrupt enable (RW) */ macro670 DREG = CSR0_INEA; in lance_open()766 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT; in lance_tx_timeout()836 DREG = CSR0_INEA | CSR0_TDMD; in lance_start_xmit()874 CSR0_TDMD | CSR0_INEA); in lance_interrupt()952 CSR0_IDON | CSR0_INEA; in lance_interrupt()1108 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT; in set_multicast_list()
28 #define CSR0_INEA 0x0040 /* Interrupt Enable (RW) */ macro
535 writereg(CSR0_INIT|CSR0_INEA,CSR0); /* trigger interrupt */ in ni65_probe1()721 int csr0 = CSR0_INEA; in ni65_stop_start()770 writedatareg(CSR0_TDMD | CSR0_INEA | csr0); in ni65_stop_start()858 writedatareg(CSR0_CLRALL | CSR0_INEA | CSR0_STRT); in ni65_lance_reinit()888 writedatareg( (csr0 & CSR0_CLRALL) | CSR0_INEA ); /* ack interrupts, interrupts enabled */ in ni65_interrupt()970 writedatareg(CSR0_INEA); in ni65_interrupt()1200 writedatareg(CSR0_TDMD | CSR0_INEA); /* enable xmit & interrupt */ in ni65_send_packet()