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/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
Dccu_div.h43 #define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \ argument
45 .shift = _shift, \
51 #define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \ argument
52 _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0)
54 #define _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _off, _max, _flags) \ argument
56 .shift = _shift, \
63 #define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \ argument
64 _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, 1, _max, _flags)
66 #define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \ argument
67 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
[all …]
Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
22 .shift = _shift, \
26 #define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \ argument
27 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, _min, 0)
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
30 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
32 #define _SUNXI_CCU_MULT(_shift, _width) \ argument
33 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, 1, 0)
Dccu_mux.h32 #define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \ argument
34 .shift = _shift, \
39 #define _SUNXI_CCU_MUX(_shift, _width) \ argument
40 _SUNXI_CCU_MUX_TABLE(_shift, _width, NULL)
51 _reg, _shift, _width, _gate, \ argument
55 .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \
66 _shift, _width, _gate, _flags) \ argument
68 _reg, _shift, _width, _gate, \
71 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
74 _reg, _shift, _width, 0, _flags)
/kernel/linux/linux-5.10/drivers/iio/dac/
Dad5686.c191 #define AD5868_CHANNEL(chan, addr, bits, _shift) { \ argument
203 .shift = (_shift), \
208 #define DECLARE_AD5693_CHANNELS(name, bits, _shift) \ argument
210 AD5868_CHANNEL(0, 0, bits, _shift), \
213 #define DECLARE_AD5686_CHANNELS(name, bits, _shift) \ argument
215 AD5868_CHANNEL(0, 1, bits, _shift), \
216 AD5868_CHANNEL(1, 2, bits, _shift), \
217 AD5868_CHANNEL(2, 4, bits, _shift), \
218 AD5868_CHANNEL(3, 8, bits, _shift), \
221 #define DECLARE_AD5676_CHANNELS(name, bits, _shift) \ argument
[all …]
/kernel/linux/linux-5.10/drivers/clk/sprd/
Dmux.h32 #define _SPRD_MUX_CLK(_shift, _width, _table) \ argument
34 .shift = _shift, \
40 _reg, _shift, _width, _flags, _fn) \ argument
42 .mux = _SPRD_MUX_CLK(_shift, _width, _table), \
52 _reg, _shift, _width, _flags) \ argument
54 _reg, _shift, _width, _flags, \
58 _shift, _width, _flags) \ argument
60 _reg, _shift, _width, _flags)
63 _reg, _shift, _width, _flags) \ argument
65 _reg, _shift, _width, _flags, \
[all …]
Ddiv.h27 #define _SPRD_DIV_CLK(_shift, _width) \ argument
29 .shift = _shift, \
39 _shift, _width, _flags, _fn) \ argument
41 .div = _SPRD_DIV_CLK(_shift, _width), \
51 _shift, _width, _flags) \ argument
53 _shift, _width, _flags, CLK_HW_INIT)
56 _shift, _width, _flags) \ argument
58 _shift, _width, _flags, CLK_HW_INIT_HW)
/kernel/linux/linux-5.10/drivers/clk/mediatek/
Dclk-mt8183-ipu_conn.c44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \ argument
45 GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \ argument
49 GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \ argument
53 GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \ argument
57 GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \ argument
61 GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
Dclk-mtk.h81 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
86 .mux_shift = _shift, \
101 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
104 _shift, _width, _gate, _flags, 0)
110 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
111 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
114 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
116 _shift, _width, CLK_SET_RATE_PARENT)
118 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument
122 .mux_shift = _shift, \
[all …]
Dclk-mt2701-aud.c18 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
23 .shift = _shift, \
27 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
32 .shift = _shift, \
36 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
41 .shift = _shift, \
45 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
50 .shift = _shift, \
Dclk-mt7622-aud.c19 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
24 .shift = _shift, \
28 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
33 .shift = _shift, \
37 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
42 .shift = _shift, \
46 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
51 .shift = _shift, \
Dclk-mux.h46 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
54 .mux_shift = _shift, \
65 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
68 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
73 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
76 _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
Dclk-mt8167.c657 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
662 .div_shift = _shift, \
687 #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ argument
692 .div_shift = _shift, \
738 #define GATE_TOP0(_id, _name, _parent, _shift) { \ argument
743 .shift = _shift, \
747 #define GATE_TOP0_I(_id, _name, _parent, _shift) { \ argument
752 .shift = _shift, \
756 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
761 .shift = _shift, \
[all …]
Dclk-mt6779-vdec.c27 #define GATE_VDEC0_I(_id, _name, _parent, _shift) \ argument
28 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
30 #define GATE_VDEC1_I(_id, _name, _parent, _shift) \ argument
31 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
Dclk-mt8167-vdec.c32 #define GATE_VDEC0_I(_id, _name, _parent, _shift) { \ argument
37 .shift = _shift, \
41 #define GATE_VDEC1_I(_id, _name, _parent, _shift) { \ argument
46 .shift = _shift, \
Dclk-mt8183-vdec.c26 #define GATE_VDEC0_I(_id, _name, _parent, _shift) \ argument
27 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
30 #define GATE_VDEC1_I(_id, _name, _parent, _shift) \ argument
31 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
Dclk-gate.h46 #define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \ argument
52 .shift = _shift, \
57 #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \ argument
58 GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0)
Dclk-mt2712-mm.c33 #define GATE_MM0(_id, _name, _parent, _shift) { \ argument
38 .shift = _shift, \
42 #define GATE_MM1(_id, _name, _parent, _shift) { \ argument
47 .shift = _shift, \
51 #define GATE_MM2(_id, _name, _parent, _shift) { \ argument
56 .shift = _shift, \
Dclk-mt2712-vdec.c27 #define GATE_VDEC0(_id, _name, _parent, _shift) { \ argument
32 .shift = _shift, \
36 #define GATE_VDEC1(_id, _name, _parent, _shift) { \ argument
41 .shift = _shift, \
Dclk-mt8516.c467 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
472 .div_shift = _shift, \
527 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
532 .shift = _shift, \
536 #define GATE_TOP2(_id, _name, _parent, _shift) { \ argument
541 .shift = _shift, \
545 #define GATE_TOP2_I(_id, _name, _parent, _shift) { \ argument
550 .shift = _shift, \
554 #define GATE_TOP3(_id, _name, _parent, _shift) { \ argument
559 .shift = _shift, \
[all …]
Dclk-mt2701-vdec.c27 #define GATE_VDEC0(_id, _name, _parent, _shift) { \ argument
32 .shift = _shift, \
36 #define GATE_VDEC1(_id, _name, _parent, _shift) { \ argument
41 .shift = _shift, \
/kernel/linux/linux-5.10/drivers/clk/actions/
Dowl-pll.h41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument
47 .shift = _shift, \
56 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
58 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
71 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
73 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
85 _shift, _width, _min_mul, _max_mul, _delay, _table, \ argument
88 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
Dowl-mux.h27 #define OWL_MUX_HW(_reg, _shift, _width) \ argument
30 .shift = _shift, \
35 _shift, _width, _flags) \ argument
37 .mux_hw = OWL_MUX_HW(_reg, _shift, _width), \
/kernel/linux/linux-5.10/drivers/net/ethernet/mellanox/mlxsw/
Dcore_acl_flex_keys.h52 #define MLXSW_AFK_ELEMENT_INFO(_type, _element, _offset, _shift, _size) \ argument
58 .shift = _shift, \
64 #define MLXSW_AFK_ELEMENT_INFO_U32(_element, _offset, _shift, _size) \ argument
66 _element, _offset, _shift, _size)
85 _shift, _size, _u32_key_diff, _avoid_size_check) \ argument
91 .shift = _shift, \
99 #define MLXSW_AFK_ELEMENT_INST_U32(_element, _offset, _shift, _size) \ argument
101 _element, _offset, _shift, _size, 0, false)
104 _shift, _size, _key_diff, \ argument
107 _element, _offset, _shift, _size, \
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-ralink/
Dpinmux.h12 #define GRP(_name, _func, _mask, _shift) \ argument
13 { .name = _name, .mask = _mask, .shift = _shift, \
17 #define GRP_G(_name, _func, _mask, _gpio, _shift) \ argument
18 { .name = _name, .mask = _mask, .shift = _shift, \
/kernel/linux/linux-5.10/drivers/clk/x86/
Dclk-cgu.h207 _shift, _width, _cf, _v) \ argument
216 .mux_shift = _shift, \
222 #define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \ argument
235 .div_shift = _shift, \
245 _shift, _cf, _v) \ argument
257 .gate_shift = _shift, \
263 _shift, _width, _cf, _freq, _v) \ argument
275 .div_shift = _shift, \
283 _shift, _width, _cf, _v, _m, _d) \ argument
295 .div_shift = _shift, \

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