| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 58 AssertSext, AssertZext, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 718 def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>;
719 class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>;
746 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>;
747 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>;
748 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>;
749 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>;
750 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>;
751 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>;
752 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>;
753 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>;
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| D | HexagonISelDAGToDAG.cpp | 1523 case ISD::AssertZext: in keepsLowBits()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 108 case ISD::AssertZext: return "AssertZext"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 57 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
224 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
546 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, in PromoteIntRes_FP_TO_XINT()
1804 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; in ExpandIntegerResult()
2558 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, in ExpandIntRes_AssertZext()
2562 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertZext()
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| D | SelectionDAGBuilder.cpp | 877 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
5531 case ISD::AssertZext: in getUnderlyingArgRegs()
8651 SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op, in lowerRangeToAssertZExt()
9384 AssertOp = ISD::AssertZext; in LowerCallTo()
9885 AssertOp = ISD::AssertZext; in LowerArguments()
9925 if (Res.getOpcode() == ISD::AssertZext) in LowerArguments()
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| D | LegalizeVectorOps.cpp | 693 NewOpc = ISD::AssertZext; in PromoteFP_TO_INT()
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| D | LegalizeDAG.cpp | 764 Result = DAG.getNode(ISD::AssertZext, dl, in LegalizeLoadOps()
2838 LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res, in ExpandNode()
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| D | SelectionDAGISel.cpp | 2806 case ISD::AssertZext: in SelectCodeCommon()
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| D | SelectionDAG.cpp | 3115 case ISD::AssertZext: { in computeKnownBits()
3530 case ISD::AssertZext: in ComputeNumSignBits()
5266 case ISD::AssertZext: { in getNode()
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| D | DAGCombiner.cpp | 1129 case ISD::AssertZext: in PromoteOperand()
1131 return DAG.getNode(ISD::AssertZext, DL, PVT, Op0, Op.getOperand(1)); in PromoteOperand()
1563 case ISD::AssertZext: return visitAssertExt(N); in visit()
4924 case ISD::AssertZext: { in SearchForAndLoads()
4927 EVT VT = Op.getOpcode() == ISD::AssertZext ? in SearchForAndLoads()
10333 Opcode == ISD::AssertZext) { in visitAssertExt()
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| D | TargetLowering.cpp | 1841 case ISD::AssertZext: { in SimplifyDemandedBits()
3530 if (Op0.getOpcode() == ISD::AssertZext && in SimplifySetCC()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 250 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 1455 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext; in convertArgType()
2160 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg, in LowerFormalArguments()
2191 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val, in LowerFormalArguments()
2210 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val, in LowerFormalArguments()
2412 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
5150 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param, in lowerImplicitZextParam()
8294 SDValue Ext = DAG.getNode(ISD::AssertZext, SL, VT, BFE, in performAndCombine()
10288 if (Op.getOpcode() == ISD::AssertZext) in isFrameIndexOp()
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| D | AMDGPUISelLowering.cpp | 501 setTargetDAGCombine(ISD::AssertZext); in AMDGPUTargetLowering()
4105 case ISD::AssertZext: in PerformDAGCombine()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 505 setTargetDAGCombine(ISD::AssertZext); in MipsTargetLowering()
3513 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
3575 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); in UnpackFromArgumentSlot()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 665 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 1103 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 617 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
1333 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall_64()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrCompiler.td | 1346 // up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper
1353 N->getOpcode() != ISD::AssertZext;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 672 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 1391 case ISD::AssertZext: { in getValueBits()
2779 (Input.getOperand(0).getOpcode() == ISD::AssertZext || in zeroExtendInputIfNeeded()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4128 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
14602 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
14605 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
14608 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 3500 ArgValue = DAG.getNode(ISD::AssertZext, DL, ArgValue.getValueType(), in LowerFormalArguments()
5806 FrameAddr = DAG.getNode(ISD::AssertZext, DL, MVT::i64, FrameAddr, in LowerFRAMEADDR()
11786 case ISD::AssertZext: { in checkValueWidth()
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